Extend GPIO SPI transactions up to 64 bits and update the X4xx FPGA
register map and RTL to support the new access width.
Migrate the GPIO SPI register definitions to SystemVerilog.
Add testbench for X4xx GPIO SPI module covering both exisiting
32bit functionality and added 64bit functionality.
Separate TB Makefiles for X4xx and X410 implementation variant.
Bump the FPGA compatibility number so host and MPM software can reject
images that do not provide the required GPIO SPI register interface.
Extend the SPI slave model to propagate simulation failures to the test
execution framework.
Extract the timing monitor from the control-port SPI testbench so it
can be shared by the GPIO SPI simulations while keeping timing checks
centralized and consistent.
Use a resources file to pass RFNoC OOT source files to Vivado TCL
scripts, avoiding ARG_MAX argument list limits.
This makes B310 consistent with other USRPs that were previously
updated in commit fa7c3604.
Use --seed only to initialize a local deterministic random number
generator. Generate a new signed 32-bit BUILD_SEED for each FPGA build
attempt instead of passing --seed directly to the first build. This
avoids accidentally using sequential pipeline attempt numbers as
BUILD_SEED values.
Using the same --seed produces the same BUILD_SEED sequence, preserving
reproducibility.
Added a state machine to fix a bug in the temporal decimation code
of the decimating halfband filter module.
Additionally added a testcase to the testbench for the issue this
change is fixing.
Reversing the order of the barrel shifter module used by the CIC
filter implementations, in order to reduce the possible bits
selectable from the last stage going into the rounding module.
This should make routing easier.
We can reduce the bus width of the comb filter stage in the CIC
interpolation filter, as it is the first module in the CIC filter and
only adds one bit per order stage. Therefore, we do not need to
immediately go to the full accumulation bit width needed for the later
integrator stages of the CIC interpolation filter, and can save some
FPGA resources by only extending to the required width for each CIC
stage.
The same logic also applies to the interpolation stage, which only adds
zeros into the bitstream and therefore does not change the bus width.
Adding a FIFO size module parameter to the comb filter module, in
order to selectively set only the last of N-order filter stages to
use a 2-stage FIFO.
Without this change, kernel 6.12 generates the following warning:
nixge 40000000.ethernet (unnamed net_device) (uninitialized): fixed link full duplex 1000Mbps not recognised
With the change, the link is correctly detected as 1G:
nixge 40000000.ethernet sfp0: configuring for fixed/gmii link mode
Fixed an issue when multiple timed DDS commands were present, where
the first one was popped and then the second command immediately
got popped as well to the stale a lookahead signal.
The fix is to clear the lookahead signal and threshold signal on
every fifo pop command.
