hero123457/uhd
1
0
Fork 0
mirror of https://github.com/EttusResearch/uhd.git synced 2026-10-25 17:36:10 +00:00
Code Issues Projects Releases Wiki Activity

fpga: lib: fixup i2c non-blocking assignments

Browse Source
This commit is contained in:
Javier Valenzuela 2026-09-03 22:05:14 -05:00 committed by Frank Dietze
parent 04a7f8c6bf
commit 7351887ab5
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
fpga/usrp3/lib/control/ctrlport_to_wb_i2c.v
View File

@ -110,19 +110,19 @@ module ctrlport_to_wb_i2c #(
end
case (s_ctrlport_req_addr)
BASE_ADDRESS + WB_PRER_LO * REG_STRIDE_SIZE: begin
wb_adr_i = WB_PRER_LO;
wb_adr_i <= WB_PRER_LO;
end
BASE_ADDRESS + WB_PRER_HI * REG_STRIDE_SIZE: begin
wb_adr_i = WB_PRER_HI;
wb_adr_i <= WB_PRER_HI;
end
BASE_ADDRESS + WB_CTR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_CTR;
wb_adr_i <= WB_CTR;
end
BASE_ADDRESS + WB_TXR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_TXR;
wb_adr_i <= WB_TXR;
end
BASE_ADDRESS + WB_CR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_CR;
wb_adr_i <= WB_CR;
end
endcase
@ -146,10 +146,10 @@ module ctrlport_to_wb_i2c #(
wb_adr_i <= WB_CTR;
end
BASE_ADDRESS + WB_RXR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_RXR;
wb_adr_i <= WB_RXR;
end
BASE_ADDRESS + WB_SR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_SR;
wb_adr_i <= WB_SR;
end
// Respond with 0
default: begin