fpga: b310: Fix synthesis-only builds

fpga/usrp3/top/b300/Makefile

@@ -38,8 +38,6 @@ BASE_DEFS= $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
 ifndef TARGET
 	ifeq ($(CHECK), 1)
 		TARGET = rtl
-	else ifeq ($(SYNTH), 1)
-		TARGET = synth
 	else ifeq ($(IP_ONLY), 1)
 		TARGET = viv_ip
 	else
@@ -53,7 +51,11 @@ vivado_build = make -f Makefile.b310.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) P
 vivado_ip    = make -f Makefile.b310.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
 
 # post_build($1=Device, $2=Option)
-ifeq ($(TARGET),bin)
+# Only export build artifacts for a full build (TARGET=bin) and not synthesis
+# only (SYNTH=1). Normalize SYNTH so that only the value 1 is treated as
+# synthesis only; 0 or unset are equivalent.
+SYNTH_ONLY := $(filter 1,$(SYNTH))
+ifeq ($(TARGET)$(SYNTH_ONLY),bin)
 	post_build = @\
 		mkdir -p $(BUILD_OUTPUT_DIR); \
 		echo "Exporting bitstream files..."; \

fpga/usrp3/top/b300/Makefile.b310.inc

@@ -104,13 +104,10 @@ bin: .prereqs
 	@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
 	$(call BUILD_VIVADO_DESIGN,$(abspath ./build_b310.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
 
-synth: .prereqs
-	$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
-
 rtl: .prereqs
 	$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
 
 viv_ip: .prereqs $$(DESIGN_SRCS) ip
 	@echo "IP build for $(NAME) DONE . . ."
 
-.PHONY: bin synth rtl viv_ip
+.PHONY: bin rtl viv_ip

fpga/usrp3/top/b300/build_b310.tcl

@@ -13,6 +13,7 @@ vivado_utils::initialize_project
 # STEP#2: Run synthesis
 vivado_utils::synthesize_design
 vivado_utils::generate_post_synth_reports
+vivado_utils::exit_if_synth_only
 
 # STEP#3: Run implementation strategy
 set b310_strategy [dict create]