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114 lines
3.4 KiB
PHP
114 lines
3.4 KiB
PHP
#
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# Copyright 2025 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include ../x300/coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/wishbone/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/io_port2/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/io_cap_gen/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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b310.sv \
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netlists/b310_jesd204b.vhd \
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netlists/b310_jesd204b.edf \
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netlists/cpld_interface_wrapper.vhd \
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netlists/cpld_interface_wrapper.edf \
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netlists/b310_g2x4_host_interface.vhd \
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netlists/b310_g2x4_host_interface.edf \
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b310_pcie_int.sv \
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core/core_regs.sv \
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core/basic_regs.sv \
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core/radio_control_regs.sv \
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core/b310_core.sv \
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b3xx_pps_sync.sv \
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b310_xadc_wrapper.sv \
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constraints/b310.xdc \
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constraints/timing.xdc \
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constraints/b310_dram.xdc \
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../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd \
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DESIGN_SRCS = $(abspath $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(EXTRAM_SRCS) \
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$(WISHBONE_SRCS) \
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$(IOPORT2_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) $(PACKET_PROC_SRCS) $(DSP_SRCS) \
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$(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(LIB_IP_XCI_SRCS) $(PCI_K7_SRCS) \
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$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS) \
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$(TOP_SRCS) \
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)
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_b310.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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viv_ip: .prereqs $$(DESIGN_SRCS) ip
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@echo "IP build for $(NAME) DONE . . ."
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.PHONY: bin rtl viv_ip
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