Max Becker 772e682503 fpga: Update SPI simulation testbenches ... Extend the SPI slave model to propagate simulation failures to the test execution framework. Extract the timing monitor from the control-port SPI testbench so it can be shared by the GPIO SPI simulations while keeping timing checks centralized and consistent.		2026-09-29 13:12:32 +02:00
..
export/x300/radio	fpga: removing deprecated FIFO IP cores	2026-08-20 01:46:19 +02:00
lib	fpga: Update SPI simulation testbenches	2026-09-29 13:12:32 +02:00
sim	fpga: Update SPI simulation testbenches	2026-09-29 13:12:32 +02:00
tools	fpga: tools: Fix --CHECK image build flag	2026-09-29 10:52:44 +02:00
top	fpga: Upgrade to Vivado 2025.2: Repair all testbenches	2026-09-29 09:09:08 +02:00
.gitignore	Move ignore of build folders into top level	2025-07-18 11:19:52 +02:00
build.py	fpga: Replace references to python -> python3	2023-12-05 15:43:08 -06:00
LICENSE.md	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00