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fpga: tools: Fix --CHECK image build flag

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Fix CHECK_VIVADO_DESIGN make target.
This fixes the --CHECK target/argument for available in the rfnoc_image_builder
This commit is contained in:
Max Becker 2026-09-16 17:35:06 +02:00 committed by Martin Braun
parent ec86cd7b2c
commit 440ed5ae76
1 changed files with 2 additions and 0 deletions
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2
fpga/usrp3/tools/make/viv_design_builder.mak
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@ -57,9 +57,11 @@ CHECK_VIVADO_DESIGN = \
export VIV_TOP_MODULE=$(2); \
export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
export VIV_MODE=$(VIVADO_MODE); \
export VIV_PROJECT=$(VIVADO_PROJECT); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
export VIV_OOT_SRCS_FILE=$(OOT_SRCS_FILE); \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \
export VIV_SECURE_KEY=$(call RESOLVE_PATH,$(abspath $(SECURE_KEY))); \
cd $(BUILD_DIR); \
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou