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fpga: Upgrade to Vivado 2025.2: Repair all testbenches

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This commit is contained in:
Max Köhler 2026-09-10 19:42:51 +02:00 committed by Max Köhler
parent 81c53bed91
commit 65b9c0270e
38 changed files with 439 additions and 310 deletions
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6
fpga/usrp3/lib/dsp/complex_multiply_iq.sv
View File

@ -134,6 +134,10 @@ module complex_multiply_iq #(
// width is the same as the product. No rounding or clipping is needed in this
// case.
if (CLIP_BITS == 0 && MULT_OUTPUT_WIDTH == WIDTH_PRODUCT) begin
// Questa Workaround for illegal output connection (vsim-3053)
logic [product.DATA_WIDTH:0] out_flop_tdata;
assign {product.tdata, product.tlast} = out_flop_tdata;
axi_fifo_flop2 #(
.WIDTH(product.DATA_WIDTH + 1)
) out_flop (
@ -143,7 +147,7 @@ module complex_multiply_iq #(
.i_tdata ({product_full.tdata, product_full.tlast}),
.i_tvalid(product_full.tvalid),
.i_tready(product_full.tready),
.o_tdata ({product.tdata, product.tlast}),
.o_tdata (out_flop_tdata),
.o_tvalid(product.tvalid),
.o_tready(product.tready),
.space (),

3
fpga/usrp3/lib/dsp/sim/axis_hb_cascade_decim_tb/axis_hb_cascade_decim_tb.sv
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@ -293,10 +293,11 @@ module axis_hb_cascade_decim_tb #(
foreach (received_sample_pkt.data[sample]) begin
// For each sample in the word, check against expected data
received_sample = received_sample_pkt.data[sample];
if (!expected_data.try_peek(expected_sample_pkt)) begin
if (expected_data.num() == 0) begin
`ASSERT_ERROR(0, $sformatf(
"Not enough expected samples for received data at sample %0d", sample));
end else begin
expected_data.peek(expected_sample_pkt);
if (received_sample_pkt.keep[sample] == 0) begin
if (VERBOSE)
$display(

29
fpga/usrp3/lib/dsp/sim/axis_hb_cascade_decim_tb/axis_hb_decim_fir_tb/axis_hb_decim_fir_tb.sv
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@ -232,11 +232,15 @@ module axis_hb_decim_fir_tb #(
if (VERBOSE) begin
$display("Received sample %0d: 0x%0h", sample, received_sample);
end
if (!expected_samples.try_get(expected_sample_pkt)) begin
if (expected_samples.num() == 0) begin
`ASSERT_ERROR(0, $sformatf(
"Not enough expected samples for received data at sample %0d", sample));
end else begin
logic [SAMP_W-1:0] expected_sample;
// Keep the peek before get: Vivado XSim can SIGSEGV during elaboration
// when the mailbox item is consumed directly after num().
expected_samples.peek(expected_sample_pkt);
expected_samples.get(expected_sample_pkt);
expected_sample = expected_sample_pkt.data[0];
`ASSERT_ERROR(received_sample == expected_sample, $sformatf(
"Data mismatch at sample %0d: expected 0x%0h, got 0x%0h",
@ -302,11 +306,18 @@ module axis_hb_decim_fir_tb #(
$sformatf("Output packet %0d: expected %0d words, received %0d",
packet, EXPECTED_LENGTHS[packet], received_pkt.data.size()));
foreach (received_pkt.data[word]) begin
`ASSERT_ERROR(expected_samples.try_get(expected_sample),
$sformatf("Output packet %0d word %0d has no expected sample", packet, word));
`ASSERT_ERROR(received_pkt.data[word] == expected_sample.data[0],
$sformatf("Output packet %0d word %0d: expected 0x%0h, received 0x%0h",
packet, word, expected_sample.data[0], received_pkt.data[word]));
if (expected_samples.num() == 0) begin
`ASSERT_ERROR(0,
$sformatf("Output packet %0d word %0d has no expected sample", packet, word));
end else begin
// Keep the peek before get: Vivado XSim can SIGSEGV during elaboration
// when the mailbox item is consumed directly after num().
expected_samples.peek(expected_sample);
expected_samples.get(expected_sample);
`ASSERT_ERROR(received_pkt.data[word] == expected_sample.data[0],
$sformatf("Output packet %0d word %0d: expected 0x%0h, received 0x%0h",
packet, word, expected_sample.data[0], received_pkt.data[word]));
end
end
end
@ -427,10 +438,14 @@ module axis_hb_decim_fir_tb #(
// 4b: Remaining samples must match the model's impulse response
foreach (received_sample_pkt.data[i]) begin
received_sample = received_sample_pkt.data[i];
if (!expected_samples.try_get(expected_sample_pkt)) begin
if (expected_samples.num() == 0) begin
`ASSERT_ERROR(0, $sformatf(
"After clear+preload: no expected sample at index %0d", i));
end else begin
// Keep the peek before get: Vivado XSim can SIGSEGV during elaboration
// when the mailbox item is consumed directly after num().
expected_samples.peek(expected_sample_pkt);
expected_samples.get(expected_sample_pkt);
`ASSERT_ERROR(received_sample == expected_sample_pkt.data[0], $sformatf(
"After clear+preload: mismatch at sample %0d: expected 0x%0h, got 0x%0h",
i, expected_sample_pkt.data[0], received_sample));

14
fpga/usrp3/lib/dsp/sim/axis_hb_cascade_intp_tb/axis_hb_intp_fir_tb/axis_hb_intp_fir_tb.sv
View File

@ -229,16 +229,20 @@ module axis_hb_intp_fir_tb #(
foreach (received_sample_pkt.data[sample]) begin
received_sample = received_sample_pkt.data[sample];
if (!samples_exp.try_get(expected_sample_pkt)) begin
if (samples_exp.num() == 0) begin
`ASSERT_ERROR(0, $sformatf(
"Not enough expected samples for received sample %0d", sample));
end else begin
// Keep the peek before get: Vivado XSim can SIGSEGV during elaboration
// when the mailbox item is consumed directly after num().
samples_exp.peek(expected_sample_pkt);
samples_exp.get(expected_sample_pkt);
`ASSERT_ERROR(received_sample == expected_sample_pkt.data[0], $sformatf(
"Data mismatch at sample %0d: expected 0x%0h, got 0x%0h",
sample, expected_sample_pkt.data[0], received_sample));
end
end
endtask : test_filter_response
//---------------------------------------------------------------------------
@ -308,10 +312,14 @@ module axis_hb_intp_fir_tb #(
// Step 4b: Remaining samples must match the model's impulse response.
foreach (received_sample_pkt.data[sample]) begin
received_sample = received_sample_pkt.data[sample];
if (!samples_exp.try_get(expected_sample_pkt)) begin
if (samples_exp.num() == 0) begin
`ASSERT_ERROR(0, $sformatf(
"After clear+preload: no expected sample at sample %0d", sample));
end else begin
// Keep the peek before get: Vivado XSim can SIGSEGV during elaboration
// when the mailbox item is consumed directly after num().
samples_exp.peek(expected_sample_pkt);
samples_exp.get(expected_sample_pkt);
`ASSERT_ERROR(received_sample == expected_sample_pkt.data[0], $sformatf(
"After clear+preload: mismatch at sample %0d: expected 0x%0h, got 0x%0h",
sample, expected_sample_pkt.data[0], received_sample));

4
fpga/usrp3/lib/dsp/sim/cic/cic_filter_interp/cic_filter_interp_tb.sv
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@ -178,8 +178,8 @@ module cic_filter_interp_tb #(
function automatic model_sample_t sign_extend_sample(sample_t samp_in);
logic signed [COMP_W-1:0] q_in = samp_in[COMP_W-1:0];
logic signed [COMP_W-1:0] i_in = samp_in[SAMP_W-1:COMP_W];
logic signed [MODEL_COMP_W-1:0] q_ext = MODEL_COMP_W'(q_in);
logic signed [MODEL_COMP_W-1:0] i_ext = MODEL_COMP_W'(i_in);
logic signed [MODEL_COMP_W-1:0] q_ext = q_in;
logic signed [MODEL_COMP_W-1:0] i_ext = i_in;
return {i_ext, q_ext};
endfunction : sign_extend_sample

18
fpga/usrp3/lib/dsp/sim/cic/comb_filter/cic_comb_filter_test_pkg.sv
View File

@ -23,7 +23,7 @@
package cic_comb_filter_test_pkg;
`include "test_exec.svh"
import cic_utils_pkg::*;
import cic_test_pkg::*;
import PkgAxiStreamBfm::*;
@ -115,7 +115,7 @@ package cic_comb_filter_test_pkg;
end
return packet_out;
endfunction : deserialize_packet
//-------------------------------------------------------------------------
// to_sample_queue: convert a single-sample AXI-Stream packet to a flat
// sample queue, preserving sample order. Useful for passing data into
@ -286,19 +286,21 @@ package cic_comb_filter_test_pkg;
input sample_queue_t samples_in,
output sample_queue_t samples_out
);
comp_t in_i, in_q, delayed_i, delayed_q;
comp_t in_i, in_q, delayed_i, delayed_q, diff_i, diff_q;
samples_out = {};
foreach (samples_in[i]) begin
in_q = comp_t'(samples_in[i][COMP_W-1:0]);
in_i = comp_t'(samples_in[i][ACCUM_W-1:COMP_W]);
in_q = samples_in[i][COMP_W-1:0];
in_i = samples_in[i][ACCUM_W-1:COMP_W];
if (i < DELAY) begin
delayed_q = '0;
delayed_i = '0;
end else begin
delayed_q = comp_t'(samples_in[i-DELAY][COMP_W-1:0]);
delayed_i = comp_t'(samples_in[i-DELAY][ACCUM_W-1:COMP_W]);
delayed_q = samples_in[i-DELAY][COMP_W-1:0];
delayed_i = samples_in[i-DELAY][ACCUM_W-1:COMP_W];
end
samples_out.push_back({comp_t'(in_i - delayed_i), comp_t'(in_q - delayed_q)});
diff_i = in_i - delayed_i;
diff_q = in_q - delayed_q;
samples_out.push_back({diff_i, diff_q});
end
endfunction : process_samples

6
fpga/usrp3/lib/dsp/sim/timed_complex_gain_tb/timed_complex_gain_tb.sv
View File

@ -136,6 +136,10 @@ module timed_complex_gain_tb #(
// DUT
//---------------------------------------------------------------------------
logic [ CTRLPORT_STS_W-1:0] dut_ctrlport_if_resp_status;
assign dut_ctrlport_if.resp.status = ctrlport_status_t'(dut_ctrlport_if_resp_status);
// Instantiate the DUT
timed_complex_gain #(
.ITEM_W (ITEM_W),
@ -156,7 +160,7 @@ module timed_complex_gain_tb #(
.s_ctrlport_req_has_time(dut_ctrlport_if.req.has_time),
.s_ctrlport_req_time (dut_ctrlport_if.req.timestamp),
.s_ctrlport_resp_ack (dut_ctrlport_if.resp.ack),
.s_ctrlport_resp_status ({dut_ctrlport_if.resp.status}),
.s_ctrlport_resp_status (dut_ctrlport_if_resp_status),
.s_ctrlport_resp_data (dut_ctrlport_if.resp.data),
.data_in (dut_in_strobe_if.data),
.data_out (dut_out_strobe_if.data),

19
fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
View File

@ -58,6 +58,17 @@ module rfnoc_block_null_src_sink_tb #(
RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl;
// DUT
// Questa Workaround for illegal output connection (vsim-3053)
logic [CHDR_W*2-1:0] m_rfnoc_chdr_tdata;
logic [1:0] m_rfnoc_chdr_tlast;
logic [1:0] m_rfnoc_chdr_tvalid;
assign {s1_chdr.tdata , s0_chdr.tdata } = m_rfnoc_chdr_tdata;
assign {s1_chdr.tlast , s0_chdr.tlast } = m_rfnoc_chdr_tlast;
assign {s1_chdr.tvalid, s0_chdr.tvalid} = m_rfnoc_chdr_tvalid;
logic [1:0] s_rfnoc_chdr_tready;
assign {m1_chdr.tready , m0_chdr.tready } = s_rfnoc_chdr_tready;
rfnoc_block_null_src_sink #(
.THIS_PORTID (THIS_PORTID),
.CHDR_W (CHDR_W),
@ -72,10 +83,10 @@ module rfnoc_block_null_src_sink_tb #(
.s_rfnoc_chdr_tdata ({m1_chdr.tdata , m0_chdr.tdata }),
.s_rfnoc_chdr_tlast ({m1_chdr.tlast , m0_chdr.tlast }),
.s_rfnoc_chdr_tvalid({m1_chdr.tvalid , m0_chdr.tvalid }),
.s_rfnoc_chdr_tready({m1_chdr.tready , m0_chdr.tready }),
.m_rfnoc_chdr_tdata ({s1_chdr.tdata , s0_chdr.tdata }),
.m_rfnoc_chdr_tlast ({s1_chdr.tlast , s0_chdr.tlast }),
.m_rfnoc_chdr_tvalid({s1_chdr.tvalid, s0_chdr.tvalid}),
.s_rfnoc_chdr_tready(s_rfnoc_chdr_tready),
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid(m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready({s1_chdr.tready, s0_chdr.tready}),
.s_rfnoc_ctrl_tdata (m_ctrl.tdata ),
.s_rfnoc_ctrl_tlast (m_ctrl.tlast ),

20
fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/align_samples_tb/align_samples_tb.sv
View File

@ -129,6 +129,13 @@ module align_samples_tb #(
i_dir <= 'X;
i_cfg_en <= 0;
// Push one sample with the new configuration to update the DUT carry
// state before normal samples are checked.
i_push <= 1;
i_data <= 'X;
i_user <= 'X;
clk_gen.clk_wait_r();
// Send number of words based on argument
for (int word_cnt=0; word_cnt < num_words;) begin
// 50% probability of changing push
@ -249,7 +256,8 @@ module align_samples_tb #(
act_user = o_user;
end
if (dir == 0 && first_reg == 1 && first == 1) begin
if (!$isunknown(exp_data) &&
dir == 0 && first_reg == 1 && first == 1) begin
// If first word is left shifted, only check data shifted to account
// for ModelSim/Vivado behavior.
for (int val_check = SPC-1; val_check > shift; val_check--) begin
@ -258,14 +266,16 @@ module align_samples_tb #(
"Expected 0x%X Read 0x%X"},
val_check, exp_data[val_check], act_data[val_check]));
end
end else begin
end else if (!$isunknown(exp_data)) begin
`ASSERT_ERROR(exp_data === act_data,
$sformatf({"Output data not equal to expected data. ",
"Expected 0x%X Read 0x%X"}, exp_data, act_data));
end
`ASSERT_ERROR(exp_user === act_user,
$sformatf({"Output user data not equal to expected user data. ",
"Expected 0x%X Read 0x%X"}, exp_user, act_user));
if (!$isunknown(exp_user)) begin
`ASSERT_ERROR(exp_user === act_user,
$sformatf({"Output user data not equal to expected user data. ",
"Expected 0x%X Read 0x%X"}, exp_user, act_user));
end
end
// Check input if config changed and set expected data to invalid

12
fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/radio_tx_core.v
View File

@ -309,13 +309,17 @@ module radio_tx_core #(
// requested timestamp. "send_early" means that the requested
// timestamp is actually one word earlier than the word with the
// matching timestamp because of the way the radio_time is aligned.
if (NSPC > 1) begin
if (NSPC > 1) begin : gen_calc_time_shift
// Workaround for Questa: Range width of 0 is not greater than zero (vopt-13448)
// For NSPC > 1, SHIFT_W = log2(NSPC) is >0, but Questa does not see that.
localparam SHIFT_W_MIN_ONE = SHIFT_W ? SHIFT_W : 1;
if (s_axis_thas_time) begin
if (radio_offset > s_axis_ttimestamp[0+:SHIFT_W]) begin
time_shift <= NSPC - (radio_offset - s_axis_ttimestamp[0+:SHIFT_W]);
if (radio_offset > s_axis_ttimestamp[0+:SHIFT_W_MIN_ONE]) begin
time_shift <= NSPC - (radio_offset - s_axis_ttimestamp[0+:SHIFT_W_MIN_ONE]);
send_early <= 1'b1;
end else begin
time_shift <= s_axis_ttimestamp[0+:SHIFT_W] - radio_offset;
time_shift <= s_axis_ttimestamp[0+:SHIFT_W_MIN_ONE] - radio_offset;
send_early <= 1'b0;
end
end else begin

14
fpga/usrp3/lib/rfnoc/core/chdr_mgmt_pkt_handler.v
View File

@ -130,6 +130,14 @@ module chdr_mgmt_pkt_handler #(
assign {bypass_tid, bypass_tdest} = {CHDR_MGMT_ROUTE_EPID, 10'h0};
// Questa Workaround for illegal output connection (vsim-3053)
wire [CHDR_W+10+2-1:0] mgmt_mux_tdata;
wire mgmt_mux_tlast;
wire mgmt_mux_tvalid;
assign {m_axis_chdr_tid, m_axis_chdr_tdest, m_axis_chdr_tdata} = mgmt_mux_tdata;
assign m_axis_chdr_tlast = mgmt_mux_tlast;
assign m_axis_chdr_tvalid = mgmt_mux_tvalid;
axi_mux #(
.WIDTH(CHDR_W+10+2), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
) mgmt_mux_i (
@ -137,9 +145,9 @@ module chdr_mgmt_pkt_handler #(
.i_tdata({m_mgmt_tid, m_mgmt_tdest, m_mgmt_tdata, bypass_tid, bypass_tdest, bypass_tdata}),
.i_tlast({m_mgmt_tlast, bypass_tlast}),
.i_tvalid({m_mgmt_tvalid, bypass_tvalid}), .i_tready({m_mgmt_tready, bypass_tready}),
.o_tdata({m_axis_chdr_tid, m_axis_chdr_tdest, m_axis_chdr_tdata}),
.o_tlast(m_axis_chdr_tlast),
.o_tvalid(m_axis_chdr_tvalid), .o_tready(m_axis_chdr_tready)
.o_tdata(mgmt_mux_tdata),
.o_tlast(mgmt_mux_tlast),
.o_tvalid(mgmt_mux_tvalid), .o_tready(m_axis_chdr_tready)
);
end else begin : gen_mgmt_only
// We are assuming that only management packets come into this module so we don't

2
fpga/usrp3/lib/rfnoc/duc.v
View File

@ -137,7 +137,7 @@ module duc #(
axi_hb47 halfband1 (
.aclk(clk),
.aresetn(~(reset | clear | reset_on_change)),
.s_axis_data_tvalid(i_tvalid),
.s_axis_data_tvalid(i_tvalid & (hb_rate != 0)),
.s_axis_data_tready(i_tready_hb1),
.s_axis_data_tdata(o_tdata_extd),
.m_axis_data_tvalid(o_tvalid_hb1),

3
fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/Makefile
View File

@ -29,10 +29,11 @@ $(RFNOC_XBAR_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
SIM_TOP = axis_pyld_ctxt_converter_tb
SIM_TOP = axis_pyld_ctxt_converter_all_tb
SIM_SRCS = \
$(abspath axis_pyld_ctxt_converter_tb.sv) \
$(abspath axis_pyld_ctxt_converter_all_tb.sv) \
# MODELSIM_USER_DO = $(abspath wave.do)

74
fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_all_tb.sv Normal file
View File

@ -0,0 +1,74 @@
//
// Copyright 2026 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: axis_pyld_ctxt_converter_all_tb
//
// Description:
//
// Instantiate the payload/context converter testbench with all supported
// parameter combinations.
//
`default_nettype none
module axis_pyld_ctxt_converter_all_tb;
axis_pyld_ctxt_converter_tb #(
.CLK_PERIOD (6.0),
.ITEM_W (64),
.NIPC (1),
.CONTEXT_FIFO_SIZE (5),
.PAYLOAD_FIFO_SIZE (7),
.CONTEXT_PREFETCH_EN (1)
) tb_0();
axis_pyld_ctxt_converter_tb #(
.CLK_PERIOD (20.0),
.ITEM_W (32),
.NIPC (6),
.CONTEXT_FIFO_SIZE (5),
.PAYLOAD_FIFO_SIZE (1),
.CONTEXT_PREFETCH_EN (1)
) tb_1();
axis_pyld_ctxt_converter_tb #(
.CLK_PERIOD (3.0),
.ITEM_W (32),
.NIPC (4),
.CONTEXT_FIFO_SIZE (1),
.PAYLOAD_FIFO_SIZE (2),
.CONTEXT_PREFETCH_EN (0)
) tb_2();
axis_pyld_ctxt_converter_tb #(
.CLK_PERIOD (10.0),
.ITEM_W (16),
.NIPC (4),
.CONTEXT_FIFO_SIZE (8),
.PAYLOAD_FIFO_SIZE (5),
.CONTEXT_PREFETCH_EN (1)
) tb_3();
axis_pyld_ctxt_converter_tb #(
.CLK_PERIOD (3.0),
.ITEM_W (32),
.NIPC (2),
.CONTEXT_FIFO_SIZE (1),
.PAYLOAD_FIFO_SIZE (7),
.CONTEXT_PREFETCH_EN (0)
) tb_4();
axis_pyld_ctxt_converter_tb #(
.CLK_PERIOD (3.0),
.ITEM_W (8),
.NIPC (13),
.CONTEXT_FIFO_SIZE (1),
.PAYLOAD_FIFO_SIZE (7),
.CONTEXT_PREFETCH_EN (0)
) tb_5();
endmodule
`default_nettype wire

354
fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_tb.sv
View File

@ -9,12 +9,19 @@
`default_nettype none
module axis_pyld_ctxt_converter_tb;
module axis_pyld_ctxt_converter_tb #(
parameter realtime CLK_PERIOD = 6.0,
parameter int ITEM_W = 64,
parameter int NIPC = 1,
parameter int CONTEXT_FIFO_SIZE = 5,
parameter int PAYLOAD_FIFO_SIZE = 7,
parameter bit CONTEXT_PREFETCH_EN = 1
);
// ----------------------------------------
// Global settings
// ----------------------------------------
// Include macros and time declarations for use with PkgTestExec
`include "test_exec.svh"
@ -28,172 +35,145 @@ module axis_pyld_ctxt_converter_tb;
localparam int CHDR_W = 64;
localparam int MTU = 7;
localparam int MTU_BITS = (1 << MTU) * CHDR_W;
localparam int NINST = 6;
localparam int START_INST = 0;
localparam int STOP_INST = NINST-1;
localparam int NUM_PKTS_PER_TEST = 100;
localparam int FAST_STALL_PROB = 0;
localparam int SLOW_STALL_PROB = 35;
localparam realtime CHDR_CLK_PERIOD = 3.0;
localparam int MAX_PYLD_W = 256;
typedef struct {
realtime clk_period;
int item_w;
int nipc;
int ctxt_fifo;
int pyld_fifo;
bit prefetch;
} inst_params_t;
// Module instances to test
localparam inst_params_t INST_PARAMS[0:NINST-1] = {
'{clk_period: 6.0, item_w:64, nipc: 1, ctxt_fifo:5, pyld_fifo:7, prefetch:1},
'{clk_period:20.0, item_w:32, nipc: 6, ctxt_fifo:5, pyld_fifo:1, prefetch:1},
'{clk_period: 3.0, item_w:32, nipc: 4, ctxt_fifo:1, pyld_fifo:2, prefetch:0},
'{clk_period:10.0, item_w:16, nipc: 4, ctxt_fifo:8, pyld_fifo:5, prefetch:1},
'{clk_period: 3.0, item_w:32, nipc: 2, ctxt_fifo:1, pyld_fifo:7, prefetch:0},
'{clk_period: 3.0, item_w:8, nipc:13, ctxt_fifo:1, pyld_fifo:7, prefetch:0}
};
// ----------------------------------------
// Interfaces and clocks
// ----------------------------------------
// Clocks and resets
bit rfnoc_chdr_clk, rfnoc_chdr_rst;
bit [NINST-1:0] rfnoc_data_clk, rfnoc_data_rst;
bit rfnoc_data_clk, rfnoc_data_rst;
// Common CHDR Clock
sim_clock_gen #(CHDR_CLK_PERIOD) chdr_clk_gen_i (rfnoc_chdr_clk, rfnoc_chdr_rst);
// Flush interface
logic [31:0] r2c_framer_errors[0:NINST-1];
logic [31:0] r2c_flush_timeout[0:NINST-1], c2r_flush_timeout[0:NINST-1];
logic [0:0] r2c_flush_en [0:NINST-1], c2r_flush_en [0:NINST-1];
wire [0:0] r2c_flush_active [0:NINST-1], c2r_flush_active [0:NINST-1];
wire [0:0] r2c_flush_done [0:NINST-1], c2r_flush_done [0:NINST-1];
logic [31:0] r2c_framer_errors;
logic [31:0] r2c_flush_timeout, c2r_flush_timeout;
logic [0:0] r2c_flush_en, c2r_flush_en;
wire [0:0] r2c_flush_active, c2r_flush_active;
wire [0:0] r2c_flush_done, c2r_flush_done;
// CHDR interface
wire [CHDR_W-1:0] chdr_tdata [0:NINST-1];
wire chdr_tlast [0:NINST-1];
wire chdr_tvalid[0:NINST-1];
wire chdr_tready[0:NINST-1];
wire [CHDR_W-1:0] chdr_tdata;
wire chdr_tlast;
wire chdr_tvalid;
wire chdr_tready;
// AXIS interfaces and BFMs
AxiStreamIf #(CHDR_W, 4) r2c_ctxt [0:NINST-1] ();
AxiStreamIf #(CHDR_W, 4) c2r_ctxt [0:NINST-1] ();
AxiStreamIf #(MAX_PYLD_W) r2c_pyld [0:NINST-1] ();
AxiStreamIf #(MAX_PYLD_W) c2r_pyld [0:NINST-1] ();
AxiStreamBfm #(CHDR_W, 4) ctxt_bfm [0:NINST-1] ;
AxiStreamBfm #(MAX_PYLD_W) pyld_bfm [0:NINST-1] ;
AxiStreamIf #(CHDR_W, 4) r2c_ctxt ();
AxiStreamIf #(CHDR_W, 4) c2r_ctxt ();
AxiStreamIf #(MAX_PYLD_W) r2c_pyld ();
AxiStreamIf #(MAX_PYLD_W) c2r_pyld ();
AxiStreamBfm #(CHDR_W, 4) ctxt_bfm;
AxiStreamBfm #(MAX_PYLD_W) pyld_bfm;
// Instantiate DUTs
genvar inst_i;
generate for (inst_i = 0; inst_i < NINST; inst_i++) begin: inst
// Assign clocks and resets to ctxt and pyld streams
assign r2c_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
assign r2c_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
assign c2r_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
assign c2r_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
assign r2c_ctxt.clk = rfnoc_data_clk;
assign r2c_ctxt.rst = rfnoc_data_rst;
assign c2r_ctxt.clk = rfnoc_data_clk;
assign c2r_ctxt.rst = rfnoc_data_rst;
assign r2c_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
assign r2c_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
assign c2r_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
assign c2r_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
assign r2c_pyld.clk = rfnoc_data_clk;
assign r2c_pyld.rst = rfnoc_data_rst;
assign c2r_pyld.clk = rfnoc_data_clk;
assign c2r_pyld.rst = rfnoc_data_rst;
// Instantiate clock generator
sim_clock_gen #(INST_PARAMS[inst_i].clk_period) dclk_gen (
rfnoc_data_clk[inst_i], rfnoc_data_rst[inst_i]
sim_clock_gen #(CLK_PERIOD) dclk_gen (
rfnoc_data_clk, rfnoc_data_rst
);
// Instantiate PyldCtxt to Chdr DUT
axis_pyld_ctxt_to_chdr #(
.CHDR_W (CHDR_W),
.ITEM_W (INST_PARAMS[inst_i].item_w),
.NIPC (INST_PARAMS[inst_i].nipc),
.SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
.CONTEXT_FIFO_SIZE (INST_PARAMS[inst_i].ctxt_fifo),
.PAYLOAD_FIFO_SIZE (INST_PARAMS[inst_i].pyld_fifo),
.ITEM_W (ITEM_W),
.NIPC (NIPC),
.SYNC_CLKS (CLK_PERIOD == CHDR_CLK_PERIOD),
.CONTEXT_FIFO_SIZE (CONTEXT_FIFO_SIZE),
.PAYLOAD_FIFO_SIZE (PAYLOAD_FIFO_SIZE),
.MTU (MTU),
.CONTEXT_PREFETCH_EN (INST_PARAMS[inst_i].prefetch)
.CONTEXT_PREFETCH_EN (CONTEXT_PREFETCH_EN)
) r2c_dut (
.axis_chdr_clk (rfnoc_chdr_clk),
.axis_chdr_rst (rfnoc_chdr_rst),
.axis_data_clk (rfnoc_data_clk[inst_i]),
.axis_data_rst (rfnoc_data_rst[inst_i]),
.m_axis_chdr_tdata (chdr_tdata[inst_i]),
.m_axis_chdr_tlast (chdr_tlast[inst_i]),
.m_axis_chdr_tvalid (chdr_tvalid[inst_i]),
.m_axis_chdr_tready (chdr_tready[inst_i]),
.s_axis_payload_tdata (r2c_pyld[inst_i].slave.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
.s_axis_payload_tkeep (r2c_pyld[inst_i].slave.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
.s_axis_payload_tlast (r2c_pyld[inst_i].slave.tlast),
.s_axis_payload_tvalid(r2c_pyld[inst_i].slave.tvalid),
.s_axis_payload_tready(r2c_pyld[inst_i].slave.tready),
.s_axis_context_tdata (r2c_ctxt[inst_i].slave.tdata),
.s_axis_context_tuser (r2c_ctxt[inst_i].slave.tuser),
.s_axis_context_tlast (r2c_ctxt[inst_i].slave.tlast),
.s_axis_context_tvalid(r2c_ctxt[inst_i].slave.tvalid),
.s_axis_context_tready(r2c_ctxt[inst_i].slave.tready),
.framer_errors (r2c_framer_errors[inst_i]),
.flush_en (r2c_flush_en[inst_i]),
.flush_timeout (r2c_flush_timeout[inst_i]),
.flush_active (r2c_flush_active[inst_i]),
.flush_done (r2c_flush_done[inst_i])
.axis_data_clk (rfnoc_data_clk),
.axis_data_rst (rfnoc_data_rst),
.m_axis_chdr_tdata (chdr_tdata),
.m_axis_chdr_tlast (chdr_tlast),
.m_axis_chdr_tvalid (chdr_tvalid),
.m_axis_chdr_tready (chdr_tready),
.s_axis_payload_tdata (r2c_pyld.slave.tdata[ITEM_W*NIPC-1:0]),
.s_axis_payload_tkeep (r2c_pyld.slave.tkeep[NIPC-1:0]),
.s_axis_payload_tlast (r2c_pyld.slave.tlast),
.s_axis_payload_tvalid(r2c_pyld.slave.tvalid),
.s_axis_payload_tready(r2c_pyld.slave.tready),
.s_axis_context_tdata (r2c_ctxt.slave.tdata),
.s_axis_context_tuser (r2c_ctxt.slave.tuser),
.s_axis_context_tlast (r2c_ctxt.slave.tlast),
.s_axis_context_tvalid(r2c_ctxt.slave.tvalid),
.s_axis_context_tready(r2c_ctxt.slave.tready),
.framer_errors (r2c_framer_errors),
.flush_en (r2c_flush_en),
.flush_timeout (r2c_flush_timeout),
.flush_active (r2c_flush_active),
.flush_done (r2c_flush_done)
);
// Instantiate Chdr to PyldCtxt DUT
chdr_to_axis_pyld_ctxt #(
.CHDR_W (CHDR_W),
.ITEM_W (INST_PARAMS[inst_i].item_w),
.NIPC (INST_PARAMS[inst_i].nipc),
.SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
.CONTEXT_FIFO_SIZE (INST_PARAMS[inst_i].ctxt_fifo),
.PAYLOAD_FIFO_SIZE (INST_PARAMS[inst_i].pyld_fifo),
.CONTEXT_PREFETCH_EN (INST_PARAMS[inst_i].prefetch)
.ITEM_W (ITEM_W),
.NIPC (NIPC),
.SYNC_CLKS (CLK_PERIOD == CHDR_CLK_PERIOD),
.CONTEXT_FIFO_SIZE (CONTEXT_FIFO_SIZE),
.PAYLOAD_FIFO_SIZE (PAYLOAD_FIFO_SIZE),
.CONTEXT_PREFETCH_EN (CONTEXT_PREFETCH_EN)
) c2r_dut (
.axis_chdr_clk (rfnoc_chdr_clk),
.axis_chdr_rst (rfnoc_chdr_rst),
.axis_data_clk (rfnoc_data_clk[inst_i]),
.axis_data_rst (rfnoc_data_rst[inst_i]),
.s_axis_chdr_tdata (chdr_tdata[inst_i]),
.s_axis_chdr_tlast (chdr_tlast[inst_i]),
.s_axis_chdr_tvalid (chdr_tvalid[inst_i]),
.s_axis_chdr_tready (chdr_tready[inst_i]),
.m_axis_payload_tdata (c2r_pyld[inst_i].master.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
.m_axis_payload_tkeep (c2r_pyld[inst_i].master.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
.m_axis_payload_tlast (c2r_pyld[inst_i].master.tlast),
.m_axis_payload_tvalid(c2r_pyld[inst_i].master.tvalid),
.m_axis_payload_tready(c2r_pyld[inst_i].master.tready),
.m_axis_context_tdata (c2r_ctxt[inst_i].master.tdata),
.m_axis_context_tuser (c2r_ctxt[inst_i].master.tuser),
.m_axis_context_tlast (c2r_ctxt[inst_i].master.tlast),
.m_axis_context_tvalid(c2r_ctxt[inst_i].master.tvalid),
.m_axis_context_tready(c2r_ctxt[inst_i].master.tready),
.flush_en (c2r_flush_en[inst_i]),
.flush_timeout (c2r_flush_timeout[inst_i]),
.flush_active (c2r_flush_active[inst_i]),
.flush_done (c2r_flush_done[inst_i])
.axis_data_clk (rfnoc_data_clk),
.axis_data_rst (rfnoc_data_rst),
.s_axis_chdr_tdata (chdr_tdata),
.s_axis_chdr_tlast (chdr_tlast),
.s_axis_chdr_tvalid (chdr_tvalid),
.s_axis_chdr_tready (chdr_tready),
.m_axis_payload_tdata (c2r_pyld.master.tdata[ITEM_W*NIPC-1:0]),
.m_axis_payload_tkeep (c2r_pyld.master.tkeep[NIPC-1:0]),
.m_axis_payload_tlast (c2r_pyld.master.tlast),
.m_axis_payload_tvalid(c2r_pyld.master.tvalid),
.m_axis_payload_tready(c2r_pyld.master.tready),
.m_axis_context_tdata (c2r_ctxt.master.tdata),
.m_axis_context_tuser (c2r_ctxt.master.tuser),
.m_axis_context_tlast (c2r_ctxt.master.tlast),
.m_axis_context_tvalid(c2r_ctxt.master.tvalid),
.m_axis_context_tready(c2r_ctxt.master.tready),
.flush_en (c2r_flush_en),
.flush_timeout (c2r_flush_timeout),
.flush_active (c2r_flush_active),
.flush_done (c2r_flush_done)
);
// Assert Reset and start BFMs
initial begin
dclk_gen.reset();
r2c_flush_en[inst_i] = 0;
c2r_flush_en[inst_i] = 0;
pyld_bfm[inst_i] = new(r2c_pyld[inst_i], c2r_pyld[inst_i]);
pyld_bfm[inst_i].run();
ctxt_bfm[inst_i] = new(r2c_ctxt[inst_i], c2r_ctxt[inst_i]);
ctxt_bfm[inst_i].run();
r2c_flush_en = 0;
c2r_flush_en = 0;
pyld_bfm = new(r2c_pyld, c2r_pyld);
pyld_bfm.run();
ctxt_bfm = new(r2c_ctxt, c2r_ctxt);
ctxt_bfm.run();
end
end endgenerate
function automatic bit pyld_pkts_equal(
ref AxiStreamPacket #(MAX_PYLD_W) exp,
ref AxiStreamPacket #(MAX_PYLD_W) act,
input int item_w,
input int nipc
ref AxiStreamPacket #(MAX_PYLD_W) act
);
if (exp.data.size() != act.data.size()) return 0;
if (exp.keep.size() != act.keep.size()) return 0;
@ -202,10 +182,11 @@ module axis_pyld_ctxt_converter_tb;
automatic bit [MAX_PYLD_W-1:0] mask = '0;
automatic bit [MAX_PYLD_W-1:0] data_exp = exp.data[i];
automatic bit [MAX_PYLD_W-1:0] data_act = act.data[i];
for (int r = 0; r < nipc; r++) begin
for (int r = 0; r < NIPC; r++) begin
if (exp.keep[i][r] === 1'b1) begin
automatic bit [MAX_PYLD_W-1:0] samp_mask = ((1<<item_w)-1);
mask |= (samp_mask << (r*item_w));
automatic bit [MAX_PYLD_W-1:0] samp_mask = '1;
samp_mask >>= (MAX_PYLD_W-ITEM_W);
mask |= (samp_mask << (r*ITEM_W));
end
end
if (exp.keep[i] !== act.keep[i]) return 0;
@ -215,39 +196,33 @@ module axis_pyld_ctxt_converter_tb;
endfunction
task automatic send_recv_data_packets(
input int inst,
input inst_params_t params, //We pass this separately to work around Vivado bug
input int num_pkts,
input int mst_stall_prob,
input int slv_stall_prob,
input bit flushing = 0
);
int nipc = params.nipc;
int item_w = params.item_w;
bit prefetch = params.prefetch;
AxiStreamPacket #(MAX_PYLD_W) pyld_pkt_arr[$] = {};
AxiStreamPacket #(CHDR_W, 4) ctxt_pkt_arr[$] = {};
// Set stall probabilities
ctxt_bfm[inst].set_master_stall_prob(mst_stall_prob);
ctxt_bfm[inst].set_slave_stall_prob(slv_stall_prob);
pyld_bfm[inst].set_master_stall_prob(mst_stall_prob);
pyld_bfm[inst].set_slave_stall_prob(slv_stall_prob);
ctxt_bfm.set_master_stall_prob(mst_stall_prob);
ctxt_bfm.set_slave_stall_prob(slv_stall_prob);
pyld_bfm.set_master_stall_prob(mst_stall_prob);
pyld_bfm.set_slave_stall_prob(slv_stall_prob);
// Generate a stream of data packets
for (int p = 0; p < num_pkts; p++) begin
int len_lines = $urandom_range((MTU_BITS/(item_w*nipc))-10, 1);
int keep_int = $urandom_range(nipc, 1);
int len_lines = $urandom_range((MTU_BITS/(ITEM_W*NIPC))-10, 1);
int keep_int = $urandom_range(NIPC, 1);
pyld_pkt_arr[p] = new();
for (int i = 0; i < len_lines; i++) begin
logic [MAX_PYLD_W-1:0] rand_samp;
logic [MAX_PYLD_W-1:0] rand_samp = '0;
logic [(MAX_PYLD_W/8)-1:0] keep_val = 'x;
for (int r = 0; r < (((nipc*item_w)+31)/32); r++)
for (int r = 0; r < (((NIPC*ITEM_W)+31)/32); r++)
rand_samp[r*32 +: 32] = $urandom();
pyld_pkt_arr[p].data.push_back(rand_samp);
pyld_pkt_arr[p].user.push_back('x);
for (int r = 0; r < nipc; r++) begin
for (int r = 0; r < NIPC; r++) begin
if (i == len_lines-1)
keep_val[r] = (r < keep_int) ? 1'b1 : 1'b0;
else
@ -265,15 +240,15 @@ module axis_pyld_ctxt_converter_tb;
automatic int num_pyld_lines = pyld_pkt_arr[p].data.size();
automatic int invalid_samps = 0;
automatic int length;
for (int r = 0; r < nipc; r++)
for (int r = 0; r < NIPC; r++)
if (pyld_pkt_arr[p].keep[num_pyld_lines-1][r] === 1'b0)
invalid_samps++;
length =
length =
(CHDR_W/8) + // header
((has_time && (CHDR_W == 64)) ? (CHDR_W/8) : 0) + // timestamp
(num_mdata * (CHDR_W/8)) + // metadata
(num_pyld_lines * nipc * (item_w/8)) + // payload
(-invalid_samps * (item_w/8)); // payload (back out empty slots)
(num_pyld_lines * NIPC * (ITEM_W/8)) + // payload
(-invalid_samps * (ITEM_W/8)); // payload (back out empty slots)
chdr_hdr = '{
vc : $urandom_range(63),
@ -308,18 +283,18 @@ module axis_pyld_ctxt_converter_tb;
timeout_t timeout;
for (int p = 0; p < num_pkts; p++) begin
test.start_timeout(timeout, 50us, "Waiting to send TX context pkt");
ctxt_bfm[inst].put(ctxt_pkt_arr[p].copy());
ctxt_bfm.put(ctxt_pkt_arr[p].copy());
test.end_timeout(timeout);
if (VERBOSE) $display("[INST%0d:TxContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
if (VERBOSE) $display("[TxContext:%0d]\n%s", p, ctxt_pkt_arr[p].sprint());
end
end
begin: tx_payload
timeout_t timeout;
for (int p = 0; p < num_pkts; p++) begin
test.start_timeout(timeout, 50us, "Waiting to send TX payload pkt");
pyld_bfm[inst].put(pyld_pkt_arr[p].copy());
pyld_bfm.put(pyld_pkt_arr[p].copy());
test.end_timeout(timeout);
if (VERBOSE) $display("[INST%0d:TxPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
if (VERBOSE) $display("[TxPayload:%0d]\n%s", p, pyld_pkt_arr[p].sprint());
end
end
begin: rx_context
@ -328,10 +303,10 @@ module axis_pyld_ctxt_converter_tb;
automatic AxiStreamPacket #(CHDR_W, 4) rx_ctxt_pkt;
for (int p = 0; p < num_pkts; p++) begin
test.start_timeout(timeout, 50us, "Waiting to recv RX context pkt");
ctxt_bfm[inst].get(rx_ctxt_pkt);
ctxt_bfm.get(rx_ctxt_pkt);
test.end_timeout(timeout);
if (VERBOSE) $display("[INST%0d:RxContext:%0d]\n%s", inst, p, rx_ctxt_pkt.sprint());
if (VERBOSE) $display("[INST%0d:ExpContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
if (VERBOSE) $display("[RxContext:%0d]\n%s", p, rx_ctxt_pkt.sprint());
if (VERBOSE) $display("[ExpContext:%0d]\n%s", p, ctxt_pkt_arr[p].sprint());
`ASSERT_ERROR(ctxt_pkt_arr[p].equal(rx_ctxt_pkt), "RX context packet did not match TX");
end
end
@ -342,11 +317,11 @@ module axis_pyld_ctxt_converter_tb;
automatic AxiStreamPacket #(MAX_PYLD_W) rx_pyld_pkt;
for (int p = 0; p < num_pkts; p++) begin
test.start_timeout(timeout, 50us, "Waiting to recv RX payload pkt");
pyld_bfm[inst].get(rx_pyld_pkt);
pyld_bfm.get(rx_pyld_pkt);
test.end_timeout(timeout);
if (VERBOSE) $display("[INST%0d:RxPayload:%0d]\n%s", inst, p, rx_pyld_pkt.sprint());
if (VERBOSE) $display("[INST%0d:ExpPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
`ASSERT_ERROR(pyld_pkts_equal(pyld_pkt_arr[p], rx_pyld_pkt, item_w, nipc), "RX payload packet did not match TX");
if (VERBOSE) $display("[RxPayload:%0d]\n%s", p, rx_pyld_pkt.sprint());
if (VERBOSE) $display("[ExpPayload:%0d]\n%s", p, pyld_pkt_arr[p].sprint());
`ASSERT_ERROR(pyld_pkts_equal(pyld_pkt_arr[p], rx_pyld_pkt), "RX payload packet did not match TX");
end
end
end
@ -366,7 +341,8 @@ module axis_pyld_ctxt_converter_tb;
// Initialize
// ----------------------------------------
test.start_tb("axis_pyld_ctxt_converter_tb");
test.start_tb($sformatf(
"axis_pyld_ctxt_converter_tb: ITEM_W:%0d NIPC:%0d", ITEM_W, NIPC));
// Reset
// ----------------------------------------
@ -381,85 +357,85 @@ module axis_pyld_ctxt_converter_tb;
`ASSERT_ERROR(!rfnoc_chdr_rst && !(|rfnoc_data_rst), "Reset did not deassert");
test.end_test();
for (int inst_num = START_INST; inst_num <= STOP_INST; inst_num++) begin
$display("-----------------------------------------------------------------------------------------------");
$display("Testing INST%0d:%p", inst_num, INST_PARAMS[inst_num]);
$display("-----------------------------------------------------------------------------------------------");
$display("-----------------------------------------------------------------------------------------------");
$display("Testing ITEM_W:%0d NIPC:%0d", ITEM_W, NIPC);
$display("-----------------------------------------------------------------------------------------------");
// Stream Random Data
// ----------------------------------------
for (int cfg = 0; cfg < 4; cfg++) begin
automatic integer mst_cfg = cfg[0];
automatic integer slv_cfg = cfg[1];
$sformat(tc_label, "INST%0d: Stream Random Data (%s Mst, %s Slv)",
inst_num,(mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
$sformat(tc_label, "Stream Random Data (%s Mst, %s Slv)",
(mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
test.start_test(tc_label);
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST,
send_recv_data_packets(NUM_PKTS_PER_TEST,
mst_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB,
slv_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB
);
`ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
`ASSERT_ERROR(r2c_framer_errors === '0, "Encountered framer errors");
test.end_test();
end
// Flush
// ----------------------------------------
$sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Idle)", inst_num);
$sformat(tc_label, "Flush PyldCtxt => CHDR (Idle)");
test.start_test(tc_label);
r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
r2c_flush_en[inst_num] = 1'b1;
r2c_flush_timeout = $urandom_range(400, 200);
r2c_flush_en = 1'b1;
repeat (100) @(posedge rfnoc_chdr_clk);
`ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
`ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
`ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
r2c_flush_en[inst_num] = 1'b0;
`ASSERT_ERROR(r2c_flush_active === 1, "Flushing did not begin on time");
`ASSERT_ERROR(r2c_flush_done === 0, "Flushing ended prematurely");
repeat (r2c_flush_timeout + 1) @(posedge rfnoc_chdr_clk);
`ASSERT_ERROR(r2c_flush_done === 1, "Flushing did not end on time");
r2c_flush_en = 1'b0;
@(posedge rfnoc_chdr_clk);
test.end_test();
$sformat(tc_label, "INST%0d: Flush CHDR => PyldCtxt (Idle)", inst_num);
$sformat(tc_label, "Flush CHDR => PyldCtxt (Idle)");
test.start_test(tc_label);
c2r_flush_timeout[inst_num] = $urandom_range(400, 200);
c2r_flush_en[inst_num] = 1'b1;
repeat (100) @(posedge rfnoc_data_clk[inst_num]);
`ASSERT_ERROR(c2r_flush_active[inst_num] === 1, "Flushing did not begin on time");
`ASSERT_ERROR(c2r_flush_done[inst_num] === 0, "Flushing ended prematurely");
repeat (c2r_flush_timeout[inst_num] + 1) @(posedge rfnoc_data_clk[inst_num]);
`ASSERT_ERROR(c2r_flush_done[inst_num] === 1, "Flushing did not end on time");
c2r_flush_en[inst_num] = 1'b0;
@(posedge rfnoc_data_clk[inst_num]);
c2r_flush_timeout = $urandom_range(400, 200);
c2r_flush_en = 1'b1;
repeat (100) @(posedge rfnoc_data_clk);
`ASSERT_ERROR(c2r_flush_active === 1, "Flushing did not begin on time");
`ASSERT_ERROR(c2r_flush_done === 0, "Flushing ended prematurely");
repeat (c2r_flush_timeout + 1) @(posedge rfnoc_data_clk);
`ASSERT_ERROR(c2r_flush_done === 1, "Flushing did not end on time");
c2r_flush_en = 1'b0;
@(posedge rfnoc_data_clk);
test.end_test();
$sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Streaming)", inst_num);
$sformat(tc_label, "Flush PyldCtxt => CHDR (Streaming)");
test.start_test(tc_label);
r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
r2c_flush_en[inst_num] = 1'b1;
r2c_flush_timeout = $urandom_range(400, 200);
r2c_flush_en = 1'b1;
repeat (100) @(posedge rfnoc_chdr_clk);
`ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
`ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
`ASSERT_ERROR(r2c_flush_active === 1, "Flushing did not begin on time");
`ASSERT_ERROR(r2c_flush_done === 0, "Flushing ended prematurely");
send_recv_data_packets(NUM_PKTS_PER_TEST/10,
FAST_STALL_PROB, FAST_STALL_PROB, 1 /*flushing*/
);
repeat (NUM_PKTS_PER_TEST/10 * (1<<MTU) * 4) @(posedge rfnoc_chdr_clk);
repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
`ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
r2c_flush_en[inst_num] = 1'b0;
repeat (r2c_flush_timeout + 1) @(posedge rfnoc_chdr_clk);
`ASSERT_ERROR(r2c_flush_done === 1, "Flushing did not end on time");
r2c_flush_en = 1'b0;
@(posedge rfnoc_chdr_clk);
test.end_test();
$sformat(tc_label, "INST%0d: Stream Data After Flush", inst_num);
$sformat(tc_label, "Stream Data After Flush");
test.start_test(tc_label);
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
send_recv_data_packets(NUM_PKTS_PER_TEST/10,
FAST_STALL_PROB, FAST_STALL_PROB
);
`ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
`ASSERT_ERROR(r2c_framer_errors === '0, "Encountered framer errors");
test.end_test();
end
// Finish Up
// ----------------------------------------
// Display final statistics and results
test.end_tb();
test.end_tb(0);
dclk_gen.kill();
chdr_clk_gen_i.kill();
end
endmodule

3
fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/ctrlport_endpoint_tb.sv
View File

@ -330,8 +330,9 @@ module ctrlport_endpoint_tb;
case (pkt.op_word.op_code)
CTRL_OP_READ: begin
pkt.data = '{};
repeat (int'(pkt.header.req_size))
repeat (pkt.header.req_size) begin
pkt.data.push_back({~base_addr[15:0], base_addr[15:0]});
end
end
CTRL_OP_BLOCK_READ: begin
pkt.data = '{};

4
fpga/usrp3/lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb/Makefile
View File

@ -85,6 +85,7 @@ IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_
sim/axi_eth_dma_bd.v \
ip/*/sim/*.h \
ip/*/sim/*.v \
ip/*/sim/*.sv \
ip/*/sim/*.vhd \
ip/*/bd_0/hdl/*.v \
ip/*/bd_0/sim/*.v \
@ -120,7 +121,8 @@ $(MISC_IP_SIM_SRCS) \
# Xilinx IP wants lots of libraries
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
MODELSIM_ARGS += glbl -t 1fs
# QuestaSim requires optimizer access enabled for this testbench to pass.
MODELSIM_ARGS += glbl -t 1fs -voptargs=+acc
# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
VLOG_ARGS += +define+SIM_SPEED_UP

28
fpga/usrp3/lib/rfnoc/xport_sv/chdr_xport_adapter.sv
View File

@ -362,6 +362,14 @@ module chdr_xport_adapter #(
logic [USER_META_W-1:0] unused_tuser;
// Questa Workaround for illegal output connection (vsim-3053)
logic [2*(eth_rx.DATA_WIDTH+USER_META_W)-1:0] rtn_demux_tdata;
logic [1:0] rtn_demux_tlast;
logic [1:0] rtn_demux_tvalid;
assign {e2e.tuser, e2e.tdata, unused_tuser, e2v.tdata} = rtn_demux_tdata;
assign {e2e.tlast, e2v.tlast} = rtn_demux_tlast;
assign {e2e.tvalid, e2v.tvalid} = rtn_demux_tvalid;
axis_switch #(
.DATA_W(eth_rx.DATA_WIDTH+USER_META_W), .DEST_W(1), .IN_PORTS(1), .OUT_PORTS(2), .PIPELINE(0)
) rtn_demux_i (
@ -369,10 +377,10 @@ module chdr_xport_adapter #(
.s_axis_tdata({e2d.tuser, e2d.tdata}), .s_axis_alloc(1'b0),
.s_axis_tdest(e2d_tid == CHDR_MGMT_RETURN_TO_SRC ? 2'b01 : 2'b00),
.s_axis_tlast(e2d.tlast), .s_axis_tvalid(e2d.tvalid), .s_axis_tready(e2d.tready),
.m_axis_tdata({e2e.tuser, e2e.tdata, unused_tuser, e2v.tdata}),
.m_axis_tdata(rtn_demux_tdata),
.m_axis_tdest(/* unused */),
.m_axis_tlast({e2e.tlast, e2v.tlast}),
.m_axis_tvalid({e2e.tvalid, e2v.tvalid}),
.m_axis_tlast(rtn_demux_tlast),
.m_axis_tvalid(rtn_demux_tvalid),
.m_axis_tready({e2e.tready, e2v.tready})
);
@ -445,6 +453,10 @@ module chdr_xport_adapter #(
// The data_fifo only takes the packet data (tdata, tlast). We use an
// axi_fifo_short module for the data_fifo because it can tolerate tvalid
// going low before a transfer completes.
// Questa Workaround for illegal output connection (vsim-3053)
logic [1+eth_rx.DATA_WIDTH-1:0] data_fifo_o_tdata;
assign {data_fifo_o.tlast, data_fifo_o.tdata} = data_fifo_o_tdata;
axi_fifo_short #(
.WIDTH (1+eth_rx.DATA_WIDTH)
) data_fifo (
@ -454,7 +466,7 @@ module chdr_xport_adapter #(
.i_tdata ({data_fifo_i.tlast, data_fifo_i.tdata}),
.i_tvalid (data_fifo_i.tvalid),
.i_tready (data_fifo_i.tready),
.o_tdata ({data_fifo_o.tlast, data_fifo_o.tdata}),
.o_tdata (data_fifo_o_tdata),
.o_tvalid (data_fifo_o.tvalid),
.o_tready (data_fifo_o.tready),
.space (),
@ -497,9 +509,13 @@ module chdr_xport_adapter #(
// transfer completes.
always_comb lookup_fifo_i.tdata = {m2e_tdest, m2e.tuser, chdr_get_dst_epid(m2e.tdata[63:0])};
always_comb {lookup_fifo_tdest, lookup_fifo_tuser, lookup_fifo_tepid} = lookup_fifo_o.tdata;
always_comb lookup_fifo_i.tvalid = m2e.tvalid && m2e.tready && m2e_hdr;
// Questa Workaround for illegal output connection (vsim-3053)
logic [1+USER_META_W+16-1:0] lookup_fifo_o_tdata;
assign lookup_fifo_o.tdata = lookup_fifo_o_tdata;
assign {lookup_fifo_tdest, lookup_fifo_tuser, lookup_fifo_tepid} = lookup_fifo_o_tdata;
axi_fifo_short #(
.WIDTH (1+USER_META_W+16)
) lookup_fifo (
@ -509,7 +525,7 @@ module chdr_xport_adapter #(
.i_tdata (lookup_fifo_i.tdata),
.i_tvalid (lookup_fifo_i.tvalid),
.i_tready (lookup_fifo_i.tready),
.o_tdata (lookup_fifo_o.tdata),
.o_tdata (lookup_fifo_o_tdata),
.o_tvalid (lookup_fifo_o.tvalid),
.o_tready (lookup_fifo_o.tready),
.space (),

2
fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile
View File

@ -50,7 +50,7 @@ $(RFNOC_CORE_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_14
MODELSIM_ARGS += glbl -t 1fs
# Define toplevel module
TB_TOP_MODULE ?= eth_ifc_all_tb

2
fpga/usrp3/lib/sim/axi/axis_load_split_merge/axis_load_split_merge_tb.sv
View File

@ -226,7 +226,7 @@ module axis_load_split_merge_tb #(
task automatic test_packets(int num_pkts = NUM_PKTS);
pkt_t::data_t data_count = 0;
mailbox pkt_mb = new();
mailbox #(pkt_t) pkt_mb = new();
// Reset the packet counters
clk_gen.clk_wait_f();

24
fpga/usrp3/lib/sim/axi/axis_shift_register/axis_shift_register_tb.sv
View File

@ -43,13 +43,13 @@ module axis_shift_register_tb();
axis_shift_register #(
.WIDTH(WIDTH), .NSPC(1), .LATENCY(2),
.SIDEBAND_DATAPATH(0), .GAPLESS(0),
.SIDEBAND_DATAPATH(0), .GAPLESS(0),
.PIPELINE("NONE")
) inst_0 (
.clk(clk), .reset(reset),
.s_axis_tdata(i_tdata[0]), .s_axis_tkeep(i_tdata[0][WIDTH]), .s_axis_tlast(i_tlast[0]),
.s_axis_tdata(i_tdata[0][WIDTH-1:0]), .s_axis_tkeep(i_tdata[0][WIDTH]), .s_axis_tlast(i_tlast[0]),
.s_axis_tvalid(i_tvalid[0]), .s_axis_tready(i_tready[0]),
.m_axis_tdata(o_tdata[0]), .m_axis_tkeep(o_tdata[0][WIDTH]), .m_axis_tlast(o_tlast[0]),
.m_axis_tdata(o_tdata[0][WIDTH-1:0]), .m_axis_tkeep(o_tdata[0][WIDTH]), .m_axis_tlast(o_tlast[0]),
.m_axis_tvalid(o_tvalid[0]), .m_axis_tready(o_tready[0]),
.stage_stb(stage_stb[0]), .stage_eop(stage_eop[0]),
.m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
@ -57,13 +57,13 @@ module axis_shift_register_tb();
axis_shift_register #(
.WIDTH(WIDTH), .NSPC(1), .LATENCY(9),
.SIDEBAND_DATAPATH(0), .GAPLESS(0),
.SIDEBAND_DATAPATH(0), .GAPLESS(0),
.PIPELINE("BOTH")
) inst_1 (
.clk(clk), .reset(reset),
.s_axis_tdata(i_tdata[1]), .s_axis_tkeep(i_tdata[1][WIDTH]), .s_axis_tlast(i_tlast[1]),
.s_axis_tdata(i_tdata[1][WIDTH-1:0]), .s_axis_tkeep(i_tdata[1][WIDTH]), .s_axis_tlast(i_tlast[1]),
.s_axis_tvalid(i_tvalid[1]), .s_axis_tready(i_tready[1]),
.m_axis_tdata(o_tdata[1]), .m_axis_tkeep(o_tdata[1][WIDTH]), .m_axis_tlast(o_tlast[1]),
.m_axis_tdata(o_tdata[1][WIDTH-1:0]), .m_axis_tkeep(o_tdata[1][WIDTH]), .m_axis_tlast(o_tlast[1]),
.m_axis_tvalid(o_tvalid[1]), .m_axis_tready(o_tready[1]),
.stage_stb(stage_stb[1]), .stage_eop(stage_eop[1]),
.m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
@ -71,13 +71,13 @@ module axis_shift_register_tb();
axis_shift_register #(
.WIDTH(WIDTH/2), .NSPC(2), .LATENCY(3),
.SIDEBAND_DATAPATH(1), .GAPLESS(0),
.SIDEBAND_DATAPATH(1), .GAPLESS(0),
.PIPELINE("NONE")
) inst_2 (
.clk(clk), .reset(reset),
.s_axis_tdata(i_tdata[2]), .s_axis_tkeep(i_tdata[2][WIDTH]), .s_axis_tlast(i_tlast[2]),
.s_axis_tdata(i_tdata[2][WIDTH-1:0]), .s_axis_tkeep(i_tdata[2][WIDTH]), .s_axis_tlast(i_tlast[2]),
.s_axis_tvalid(i_tvalid[2]), .s_axis_tready(i_tready[2]),
.m_axis_tdata(o_tdata[2]), .m_axis_tkeep(o_tdata[2][WIDTH]), .m_axis_tlast(o_tlast[2]),
.m_axis_tdata(o_tdata[2][WIDTH-1:0]), .m_axis_tkeep(o_tdata[2][WIDTH]), .m_axis_tlast(o_tlast[2]),
.m_axis_tvalid(o_tvalid[2]), .m_axis_tready(o_tready[2]),
.stage_stb(stage_stb[2]), .stage_eop(stage_eop[2]),
.m_sideband_data(sb_dout), .m_sideband_keep(sb_keep), .s_sideband_data(sb_din)
@ -85,13 +85,13 @@ module axis_shift_register_tb();
axis_shift_register #(
.WIDTH(WIDTH/8), .NSPC(8), .LATENCY(14),
.SIDEBAND_DATAPATH(0), .GAPLESS(1),
.SIDEBAND_DATAPATH(0), .GAPLESS(1),
.PIPELINE("NONE")
) inst_3 (
.clk(clk), .reset(reset),
.s_axis_tdata(i_tdata[3]), .s_axis_tkeep(i_tdata[3][WIDTH]), .s_axis_tlast(i_tlast[3]),
.s_axis_tdata(i_tdata[3][WIDTH-1:0]), .s_axis_tkeep(i_tdata[3][WIDTH]), .s_axis_tlast(i_tlast[3]),
.s_axis_tvalid(i_tvalid[3]), .s_axis_tready(i_tready[3]),
.m_axis_tdata(o_tdata[3]), .m_axis_tkeep(o_tdata[3][WIDTH]), .m_axis_tlast(o_tlast[3]),
.m_axis_tdata(o_tdata[3][WIDTH-1:0]), .m_axis_tkeep(o_tdata[3][WIDTH]), .m_axis_tlast(o_tlast[3]),
.m_axis_tvalid(o_tvalid[3]), .m_axis_tready(o_tready[3]),
.stage_stb(stage_stb[3]), .stage_eop(stage_eop[3]),
.m_sideband_data(), .m_sideband_keep(), .s_sideband_data()

1
fpga/usrp3/tools/scripts/viv_sim_project.tcl
View File

@ -115,7 +115,6 @@ set_property verilog_define $verilog_defs [get_filesets $sim_fileset]
# XSim specific settings
set_property xsim.simulate.runtime "${sim_runtime}us" -objects [get_filesets $sim_fileset]
set_property xsim.elaborate.debug_level "all" -objects [get_filesets $sim_fileset]
set_property xsim.elaborate.unifast $sim_fast -objects [get_filesets $sim_fileset]
# Set default timescale to prevent bogus warnings
set_property xsim.elaborate.xelab.more_options -value {-timescale 1ns/1ns} -objects [get_filesets $sim_fileset]

3
fpga/usrp3/tools/utils/qsim.excludes
View File

@ -13,6 +13,3 @@ top/n3xx/sim/aurora_loopback
top/n3xx/sim/one_gig_eth_loopback
top/n3xx/sim/ten_gig_eth_loopback
top/x300/sim/x300_pcie_int
# This TB doesn't pass in ModelSim
top/x300/sim/dram_fifo_bist

3
fpga/usrp3/tools/utils/testbenches.excludes
View File

@ -29,8 +29,5 @@ lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_ms
# exclude testbenches with Vivado Simulator kernel fatal errors
lib/rfnoc/blocks/rfnoc_block_radio
lib/rfnoc/blocks/rfnoc_block_switchboard
lib/rfnoc/sim/chdr_channel_mux_tb
lib/rfnoc/sim/chdr_resize_tb
lib/rfnoc/sim/chdr_stream_endpoint_tb
lib/sim/fifo

14
fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile
View File

@ -62,14 +62,14 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
xpm \
secureip \
fifo_generator_v13_2_5 \
axi_register_slice_v2_1_24 \
fifo_generator_v13_2_14 \
axi_register_slice_v2_1_36 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_24 \
axi_crossbar_v2_1_25 \
blk_mem_gen_v8_4_4 \
axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
axi_dwidth_converter_v2_1_37 \
axi_crossbar_v2_1_38 \
blk_mem_gen_v8_4_12 \
axi_data_fifo_v2_1_36 \
generic_baseblocks_v2_1_2 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)

14
fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile
View File

@ -62,14 +62,14 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
xpm \
secureip \
fifo_generator_v13_2_5 \
axi_register_slice_v2_1_24 \
fifo_generator_v13_2_14 \
axi_register_slice_v2_1_36 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_24 \
axi_crossbar_v2_1_25 \
blk_mem_gen_v8_4_4 \
axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
axi_dwidth_converter_v2_1_37 \
axi_crossbar_v2_1_38 \
blk_mem_gen_v8_4_12 \
axi_data_fifo_v2_1_36 \
generic_baseblocks_v2_1_2 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)

2
fpga/usrp3/top/x300/sim/aurora_loopback/Makefile
View File

@ -66,7 +66,7 @@ MODELSIM_LIBS += \
unisims_ver \
unimacro_ver \
secureip \
fifo_generator_v13_2_5 \
fifo_generator_v13_2_14 \
xpm \

14
fpga/usrp3/top/x300/sim/dram_fifo/Makefile
View File

@ -64,14 +64,14 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
xpm \
secureip \
fifo_generator_v13_2_5 \
axi_register_slice_v2_1_24 \
fifo_generator_v13_2_14 \
axi_register_slice_v2_1_36 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_24 \
axi_crossbar_v2_1_25 \
blk_mem_gen_v8_4_4 \
axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
axi_dwidth_converter_v2_1_37 \
axi_crossbar_v2_1_38 \
blk_mem_gen_v8_4_12 \
axi_data_fifo_v2_1_36 \
generic_baseblocks_v2_1_2 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)

4
fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile
View File

@ -59,8 +59,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
xpm \
fifo_generator_v13_2_5 \
blk_mem_gen_v8_4_4 \
fifo_generator_v13_2_14 \
blk_mem_gen_v8_4_12 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)

18
fpga/usrp3/top/x300/sim/dram_fifo_bist/dram_fifo_bist_tb.sv
View File

@ -38,7 +38,7 @@ module dram_fifo_bist_tb();
settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk));
cvita_master cvita_fifo_in (.clk(bus_clk));
cvita_slave cvita_fifo_out (.clk(bus_clk));
// AXI DRAM FIFO Topology (Inline production BIST for DRAM FIFO):
//
// User Data ====> |---------| |---------------| |-----------| ====> User Data Out
@ -54,14 +54,14 @@ module dram_fifo_bist_tb();
axis_dram_fifo_single #(
.USE_SRAM_MEMORY(`USE_SRAM_MIG),
.USE_BD_INTERCON(`USE_BD_INTERCON),
.USE_BD_INTERCON(`USE_BD_INTERCON),
.SR_BASE(SR_FIFO_BASE)
) dut_single (
.bus_clk(bus_clk),
.bus_rst(bus_rst),
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.i_tdata(cvita_fifo_in.axis.tdata),
.i_tlast(cvita_fifo_in.axis.tlast),
.i_tvalid(cvita_fifo_in.axis.tvalid),
@ -71,7 +71,7 @@ module dram_fifo_bist_tb();
.o_tlast(cvita_fifo_out.axis.tlast),
.o_tvalid(cvita_fifo_out.axis.tvalid),
.o_tready(cvita_fifo_out.axis.tready),
.set_stb(tst_set.settings_bus.set_stb),
.set_addr(tst_set.settings_bus.set_addr),
.set_data(tst_set.settings_bus.set_data),
@ -80,7 +80,7 @@ module dram_fifo_bist_tb();
.forced_bit_err(forced_bit_err),
.init_calib_complete(calib_complete)
);
assign {error, done, running} = rb_data[3:0];
//Testbench variables
@ -100,7 +100,7 @@ module dram_fifo_bist_tb();
while (bus_rst) @(posedge bus_clk);
while (sys_rst) @(posedge sys_clk);
`TEST_CASE_DONE(~bus_rst & ~sys_rst);
forced_bit_err <= 64'h0;
repeat (200) @(posedge sys_clk);
@ -253,7 +253,7 @@ module dram_fifo_bist_tb();
`ASSERT_ERROR(error==2'b00, "BIST failed!");
@(posedge bus_clk);
`TEST_CASE_DONE(done & ~running);
`TEST_CASE_START("Validate Throughput");
tst_set.write(SR_FIFO_BASE + 0, 3'd2);
xfer_cnt = rb_data;
@ -275,7 +275,7 @@ module dram_fifo_bist_tb();
fork
begin
integer curr_time = $time;
automatic time curr_time = $time;
`TEST_CASE_START("Run BIST Continuous (Early interrupt)");
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1});
@ -315,7 +315,7 @@ module dram_fifo_bist_tb();
fork
begin
integer curr_time = $time;
automatic time curr_time = $time;
`TEST_CASE_START("Run BIST Continuous");
tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0});
tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1});

19
fpga/usrp3/top/x400/dboards/fbx/sim/i2c_sync_ctrl/ctrlport_to_i2c_sync_ctrl_tb.sv
View File

@ -16,7 +16,7 @@
`define NUM_TEST_CASES 5
`include "sim_exec_report.vh"
`include "sim_clks_rsts.vh"
`define SIM_TIMEOUT_US 200000 //overwrite this def from sim_exec_report.vh
`define SIM_TIMEOUT_US 200000 //overwrite this def from sim_exec_report.vh
module ctrlport_to_i2c_sync_ctrl_tb();
@ -79,7 +79,7 @@ module ctrlport_to_i2c_sync_ctrl_tb();
`ASSERT_ERROR( s_ctrlport_resp_data == d, "CtrlPort read returned unexpected value.");
end
endtask
task cp_poll;
input [19:0] a;
input [31:0] d;
@ -104,7 +104,7 @@ module ctrlport_to_i2c_sync_ctrl_tb();
end
end
endtask
ctrlport_to_i2c_sync_ctrl #(
.BASE_ADDRESS(0)
@ -192,13 +192,12 @@ end
endmodule
module delay (in, out);
input in;
output out;
input wire in;
output reg out;
assign out = in;
specify
(in => out) = (600,600);
endspecify
// apply transport delay
always @(in) begin
out <= #600 in;
end
endmodule

2
fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc
View File

@ -12,7 +12,7 @@ axi_interconnect_eth.sv \
IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/axi_interconnect_eth_bd/, \
sim/axi_interconnect_eth_bd.v\
ip/axi_interconnect_eth_bd_xbar_0/sim/axi_interconnect_eth_bd_xbar_0.v\
ip/*/sim/*.v\
ipshared/*/simulation/fifo_generator_vlog_beh.v\
ipshared/*/hdl/*.v\
))

2
fpga/usrp3/top/x400/ip/eth_100g_bd/Makefile.inc
View File

@ -21,7 +21,7 @@ sim/eth_100g_bd.v\
ip/*/ip_0/sim/*.v\
ip/*/sim/*.h\
ip/*/sim/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v3_1_4/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v3_1_24/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/header_files/*.h\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0.v\

2
fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile
View File

@ -35,7 +35,7 @@ $(AXI4S_SV_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_14
MODELSIM_ARGS += glbl -t 1fs
# Define toplevel module
TB_TOP_MODULE ?= lbus_all_tb

2
fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv
View File

@ -319,7 +319,7 @@ module lbus_axi_tb #(
test_transfers(num_samples);
$display("Tons of 65");
num_samples.delete();
repeat(1000) begin
repeat(700) begin
num_samples.push_back(65);
end
test_transfers(num_samples);

4
fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc
View File

@ -14,10 +14,10 @@ $(IP_XGE_PCS_PMA_EXAMPLE_SRCS)
IP_XGE_PCS_PMA_HDL_SIM_SRCS = $(IP_DIR)/xge_pcs_pma/model_10gbe.sv \
$(wildcard $(addprefix $(IP_BUILD_DIR)/xge_pcs_pma/, \
xge_pcs_pma.v \
hdl/xxv_ethernet_v4_0_vl_rfs.sv \
hdl/xxv_ethernet_v5_0_vl_rfs.sv \
ip_0/hdl/*.v \
ip_0/sim/*.v \
xxv_ethernet_v4_0_0/*.v \
xxv_ethernet_v5_0_2/*.v \
))
IP_XGE_PCS_PMA_EXAMPLE_SRCS = \

2
fpga/usrp3/top/x400/rf/200m_x440/Makefile
View File

@ -59,7 +59,7 @@ $(IP_BUILD_DIR)/fir_dec3_2spc/fir_dec3*.mif \
$(IP_BUILD_DIR)/fir_inp3_1spc/fir_inp3*.mif \
))
MODELSIM_LIBS += secureip unisims_ver unimacro_ver xilinx_vip xpm fir_compiler_v7_2_76780
MODELSIM_LIBS += secureip unisims_ver unimacro_ver xilinx_vip xpm fir_compiler_v7_2_26
MODELSIM_ARGS += glbl -t 1fs
msim modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)

2
fpga/usrp3/top/x400/rf/400m_x420/Makefile
View File

@ -61,7 +61,7 @@ $(IP_BUILD_DIR)/fir_dec3_4spc/fir_dec3*.mif \
$(IP_BUILD_DIR)/fir_inp3_2spc/fir_inp3*.mif \
))
MODELSIM_LIBS += secureip unisims_ver unimacro_ver xilinx_vip xpm fir_compiler_v7_2_76780
MODELSIM_LIBS += secureip unisims_ver unimacro_ver xilinx_vip xpm fir_compiler_v7_2_26
MODELSIM_ARGS += glbl -t 1fs
msim modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)