Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

.gitmodules

@@ -1,4 +0,0 @@
-[submodule "fpga-src"]
-	path = fpga-src
-	url = https://github.com/EttusResearch/fpga.git
-	branch = master

CODING.md

@@ -159,4 +159,4 @@ the FPGA repository.
 [CppCoreGuideLines]: https://github.com/isocpp/CppCoreGuidelines/blob/master/CppCoreGuidelines.md
 [PEP8]: https://www.python.org/dev/peps/pep-0008/
 [Pep257]: https://www.python.org/dev/peps/pep-0257/
-[fpga-coding]: https://github.com/EttusResearch/fpga/blob/master/CODING.md
+[fpga-coding]: https://github.com/EttusResearch/uhd/blob/master/fpga/CODING.md

CONTRIBUTING.md

@@ -64,7 +64,7 @@ The following guidelines apply:
 - [UHD Coding Guidelines][uhd-coding] (for anything in this repository)
 - [FPGA Coding Guidelines][fpga-coding] (for any FPGA-related modifications)
 
-[fpga-coding]: https://github.com/EttusResearch/fpga/blob/master/CODING.md
+[fpga-coding]: https://github.com/EttusResearch/uhd/blob/master/fpga/CODING.md
 [uhd-coding]: https://github.com/EttusResearch/uhd/blob/master/CODING.md
 [ettus-cla]: http://files.ettus.com/licenses/Ettus_CLA.pdf
 [ettus-ml]: http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

LICENSE.md

@@ -2,10 +2,20 @@
 
 Please refer to the individual files to verify which license applies to them.
 
-UHD itself, is, by default, licensed under the GPLv3. If you wish to obtain an
-alternative license, please contact info@ettus.com.
+UHD and MPM themselves, are, by default, licensed under the GPLv3. If you wish
+to obtain an alternative license, please contact info@ettus.com. Some of UHD's
+dependencies are shipped as part of the repository
+(see https://github.com/EttusResearch/uhd/tree/master/host/lib/deps for details).
 
-## GPLv3 License Text
+The FPGA codebase (stored under fpga/) has its own
+[licensing situation][fpga-license]. See the various subdirectories therein for
+more details.
+
+Individual source files in this repository may have different licenses than
+discussed above. Please refer to individual files and directories to verify
+which license applies to which file.
+
+## GPLv3 License Text (applies to most of UHD and MPM)
 
                     GNU GENERAL PUBLIC LICENSE
                        Version 3, 29 June 2007
@@ -629,3 +639,4 @@ copy of the Program in return for a fee.
 
                      END OF TERMS AND CONDITIONS
 
+[fpga-license]: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/LICENSE.md

fpga-src

@@ -1 +0,0 @@
-Subproject commit 36a7df009554ba900435275db98c83d1b763fd97

fpga/.gitignore

@@ -0,0 +1,12 @@
+*~
+\#*\#
+a.out
+*.vcd
+*.lxt
+.metadata
+.project
+.settings
+*.swp
+*.jou
+*.log
+*.pyc

fpga/CODING.md

@@ -0,0 +1,159 @@
+# UHD FPGA Coding Standards
+
+## Preamble
+
+To quote R. W. Emerson: "A foolish consistency is the hobgoblin of little minds,
+adored by little statesmen and philosophers and divines". Ignoring the little
+statesmen for a minute, these coding standards are here to make our life
+*easier*, not simply add additional rules. They are meant as additional guidance
+for developers, and are not meant to be interpreted as law.
+
+So, ultimately, it is up to the developer to decide how much these guidelines
+should be heeded when writing code, and up to reviewers how much they are
+relevant to new submissions.
+That said, a consistent codebase is easier to maintain, read, understand, and
+extend. Choosing personal preferences over these coding guidelines is not a
+helpful move for the team and future maintainability of the UHD FPGA codebase.
+
+## General Coding Guidelines
+
+* Code layout: We use 2 spaces for indentation levels, and never tabs.
+* Never submit code with trailing whitespace.
+* Code is read more often than it's written. Code readability is thus something
+  worth optimizing for.
+* Try and keep line lengths to 79 characters, unless readability suffers.
+* Comment your code. Especially if your code is tricky or makes unique assumptions.
+* Use the following header at the top of each file:
+```verilog
+//
+// Copyright <YEAR> Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: <MODULE_NAME>
+// Description:
+// <DESCRIPTION>
+```
+
+## Verilog Style Guidelines
+
+### General Syntax
+
+* Always use `begin`and `end` statements for more complex code blocks even if the enclosing code is only
+one line.
+* Indent begin/end as follows:
+```verilog
+if (foo) begin
+  // Do something
+end else if (bar) begin
+  case(xyz)
+    1'b0: begin
+      // Handle 0
+    end
+    default: begin
+      // Handle 1
+    end
+  endcase
+end else begin
+  // Do nothing
+end
+```
+* Instantiate and declare modules as follows:
+```verilog
+dummy_module #(
+  .PARAM1(0), .PARAM2(1)
+) inst (
+  .clk(clk), .rst(rst)
+);
+```
+
+### Assignments
+
+* Sequential blocks **must** only have non-blocking assignments (`<=`)
+* Combinational blocks should only have blocking assignments (`=`)
+* Don't mix blocking and non-blocking assignments
+
+### Modules
+
+* Each module should be defined in a separate file
+* Use Verilog 2001 ANSI-C style port declarations
+```verilog
+(
+  ...
+  output reg  foo,
+  input  wire bar
+);
+```
+* Declare inputs and outputs one per line. This makes searching and commenting easier.
+* Add inline comments to input/output ports to describe their behavior
+* Be explicit about whether an input or output is a wire or reg.
+* Group signals logically instead of by direction. If a single AXI-Stream bus has multiple inputs and
+outputs, keep them together.
+* Instantiate all ports for a module even if they are tied off or unconnected. Don't let the compiler
+insert values for any signals automatically.
+```verilog
+dummy_module inst (
+  .clk(clk), .rst(1'b0), .status(/* unused */)
+);
+```
+* Don't instantiate modules using positional arguments. Use the dot form illustrated above.
+* Every module requires a header giving a synopsis of its function below the
+  copyright header.
+
+### Clocking and Resets
+
+* Name clocks as `clk`. If there are multiple clocks then use a prefix like `bus_clk` and `radio_clk`.
+* If a module has signals or input/outputs whose clock domain is not obvious, use a clock suffix
+to be explicit about the domain, for example `axi_tdata_bclk`, `axi_tdata_rclk`.
+* Try not to encode the frequency of the clock in the name unless the particular clock can
+*never* take on any other frequency.
+* Name resets as `rst`. If there are multiple clocks then use a prefix like `bus_rst` and `radio_rst`.
+* If a reset is asynchronous, call it `arst`.
+* Try to avoid asynchronous resets as much as possible.
+* Don't active low resets unless it is used to drive IO.
+
+### Parameters, defines and constants
+
+* Parametrize modules wherever possible, especially if they are designed for reuse. Bus widths, addresses,
+buffer sizes, etc are good candidates for parametrization.
+* For modules with parameters, add inline comments to describe the behavior of each parameter
+* Propagate parameters as far up the hierarchy as possible as long as it makes sense.
+* Place `` `define`` statements in Verilog header file (.vh) and include them in modules.
+* Avoid placing `` `define`` statements in modules
+* For local parameters, use `localparam` instead on hard-coding things like widths, etc.
+
+### AXI Specific
+
+We heavily use AXI buses in the design so here are some best practices for those:
+* Keep the components of an AXI-Stream or AXI-MM bus together in port/wire instantiations
+* For module ports, use the master/slave naming convention as shown below. It makes connecting modules
+easier because a master always connects to a slave
+```verilog
+  input  wire [63:0] s_axis_tdata,
+  input  wire        s_axis_tlast,
+  input  wire        s_axis_tvalid,
+  output wire        s_axis_tready,
+  output reg  [63:0] m_axis_tdata,
+  output reg         m_axis_tlast,
+  output reg         m_axis_tvalid,
+  input  wire        m_axis_tready,
+```
+* For connections between a master and slave, *do not* use the master/slave convention. Name the bus based
+on its function or underlying data.
+```verilog
+  wire [63:0] axis_eth2xbar_tdata,
+  wire        axis_eth2xbar_tlast,
+  wire        axis_eth2xbar_tvalid,
+  wire        axis_eth2xbar_tready,
+
+  // If "axis" is obvious, drop the prefix
+  wire [63:0] samp_tdata,
+  wire        samp_tlast,
+  wire        samp_tvalid,
+  wire        samp_tready,
+```
+
+
+## Design Best Practices
+
+TBD

fpga/CONTRIBUTING.md

@@ -0,0 +1,8 @@
+# Contributing to UHD/FPGA
+
+Please refer to the [UHD contribution guidelines](https://github.com/EttusResearch/uhd/blob/master/CONTRIBUTING.md),
+they also apply to this repository.
+Please note that the issue tracker for this repository has been disabled,
+issues regarding the FPGA codebase can be reported on the
+[UHD issue tracker](https://github.com/EttusResearch/uhd/issues).
+

fpga/README.md

@@ -0,0 +1,57 @@
+Ettus Research USRP FPGA HDL Source
+===================================
+
+Welcome to the USRP FPGA HDL source code tree! This repository contains
+free & open-source FPGA HDL for the Universal Software Radio Peripheral
+(USRP™) SDR platform, created and sold by Ettus Research. A large
+percentage of the source code is written in Verilog.
+
+## Product Generations
+
+This repository contains the FPGA source for the following generations of
+USRP devices.
+
+### Generation 1
+
+- Directory: __usrp1__
+- Devices: USRP Classic Only
+- Tools: Quartus from Altera
+- [Build Instructions](http://files.ettus.com/manual/md_usrp1_build_instructions.html)
+
+### Generation 2
+
+- Directory: __usrp2__
+- Devices: USRP N2X0, USRP B100, USRP E1X0, USRP2
+- Tools: ISE from Xilinx, GNU make
+- [Build Instructions](http://files.ettus.com/manual/md_usrp2_build_instructions.html)
+- [Customization Instructions](http://files.ettus.com/manual/md_usrp2_customize_signal_chain.html)
+
+### Generation 3
+
+- Directory: __usrp3__
+- Devices: USRP B2X0, USRP X Series, USRP E3X0, USRP N3xx
+- Tools: Vivado from Xilinx, ISE from Xilinx, GNU make
+- [Build Instructions](http://files.ettus.com/manual/md_usrp3_build_instructions.html)
+- [Simulation](http://files.ettus.com/manual/md_usrp3_simulation.html)
+
+
+## Pre-built FPGA Images
+
+Pre-built FPGA and Firmware images are not hosted here. Please visit the
+[FPGA and Firmware manual page](http://files.ettus.com/manual/page_images.html)
+for instructions on downloading and using pre-built images. In most cases, running the following
+command will do the right thing.
+
+    $ uhd_images_downloader
+
+## Building This Manual
+
+This FPGA manual is available on the web at http://files.ettus.com/manual/md_fpga.html for the most
+recent stable version of UHD. If you wish to read documentation for a custom/unstable branch you will
+need to build it and open it locally using a web browser. To do so please install 
+[Doxygen](http://www.stack.nl/~dimitri/doxygen/download.html#srcbin) on your system and run the following commands:
+
+    $ cd docs
+    $ make
+    $ sensible-browser html/index.html
+

fpga/docs/.gitignore

@@ -0,0 +1,3 @@
+html/
+latex/
+*.db

fpga/docs/Makefile

@@ -0,0 +1,13 @@
+#
+# Copyright 2015 Ettus Research LLC
+#
+
+manual:
+	doxygen Doxyfile
+
+clean:
+	@rm -rf html
+	@rm -rf latex
+	@rm -rf *.db
+
+.PHONY: manual clean

fpga/docs/fpga.md

@@ -0,0 +1,46 @@
+FPGA Manual
+===========
+
+Welcome to the USRP FPGA HDL source code tree! This repository contains
+free & open-source FPGA HDL for the Universal Software Radio Peripheral
+(USRP™) SDR platform, created and sold by Ettus Research. A large
+percentage of the source code is written in Verilog.
+
+## Product Generations
+
+This repository contains the FPGA source for the following generations of
+USRP devices.
+
+### Generation 1
+
+\li Directory: __usrp1__
+\li Devices: USRP Classic Only
+\li Tools: Quartus from Altera
+\li \subpage md_usrp1_build_instructions "Build Instructions"
+
+
+### Generation 2
+
+\li Directory: __usrp2__
+\li Devices: USRP N2X0, USRP B100, USRP E1X0, USRP2
+\li Tools: ISE from Xilinx, GNU make
+\li \subpage md_usrp2_build_instructions "Build Instructions"
+\li \subpage md_usrp2_customize_signal_chain "Customization Instructions"
+
+### Generation 3
+
+\li Directory: __usrp3__
+\li Devices: USRP B2X0, USRP X Series, USRP E3X0
+\li Tools: ISE from Xilinx, GNU make
+\li \subpage md_usrp3_build_instructions "Build Instructions"
+\li \subpage md_usrp3_simulation "Simulation"
+
+## Pre-built FPGA Images
+
+Pre-built FPGA and Firmware images are not hosted here. Please visit \ref page_images
+for instructions on downloading and using pre-built images. In most cases, running
+
+    $ uhd_images_downloader
+
+will do the right thing.
+

fpga/docs/usrp1_build_instructions.md

@@ -0,0 +1,7 @@
+# Generation 1 USRP Build Documentation
+
+The USRP FPGA build system requires only the Altera FPGA tools
+
+- Download [Altera Quartus](https://www.altera.com/download/sw/dnl-sw-index.jsp)
+- The top-level project is located in `usrp1/toplevel/usrp_std/`
+- Use the Quartus GUI environment to build the project

fpga/docs/usrp2/build_instructions.md

@@ -0,0 +1,55 @@
+# Generation 2 USRP Build Documentation
+
+## Dependencies and Requirements
+
+### Dependencies
+
+The USRP FPGA build system requires a UNIX-like environment with the following dependencies
+
+- [Xilinx ISE 12.2](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v12_2.html)
+- [GNU Make](https://www.gnu.org/software/make/)
+- (Recommended) [GNU Bash](https://www.gnu.org/software/bash/)
+
+The N200 will work with the WebPack version of ISE.
+
+### Requirements
+
+- [Xilinx ISE Platform Requirements](http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/irn.pdf)
+
+### What FPGA does my USRP have?
+
+- USRP N200: Spartan® 3A-DSP 1800
+- USRP N210: Spartan® 3A-DSP 3400
+
+## Build Instructions
+
+- Download and install [Xilinx ISE 12.2](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v12_2.html)
+
+- To add xtclsh to the PATH and to setup up the Xilinx build environment run
+  + `source <install_dir>/Xilinx/12.2/ISE_DS/settings64.sh` (64-bit platform)
+  + `source <install_dir>/Xilinx/12.2/ISE_DS/settings32.sh` (32-bit platform)
+
+- Navigate to `usrp2/top/{project}` where project is:
+  + N2x0: For USRP N200 and USRP N210
+
+- To build a binary configuration bitstream run `make <target>`
+  where the target is specific to each product. To get a list of supported targets run
+  `make help`.
+
+- The build output will be specific to the product and will be located in the
+  `usrp2/top/{project}/build` directory. Run `make help` for more information.
+
+### N2x0 Targets and Outputs
+
+#### Supported Targets
+- N200R3:  Builds the USRP N200 Rev 3 design.
+- N200R4:  Builds the USRP N200 Rev 4 design.
+- N210R3:  Builds the USRP N210 Rev 3 design.
+- N210R4:  Builds the USRP N210 Rev 4 design.
+
+#### Outputs
+- `build-<target>/u2plus.bit` : Configuration bitstream with header
+- `build-<target>/u2plus.bin` : Configuration bitstream without header
+- `build-<target>/u2plus.syr` : Xilinx system report
+- `build-<target>/u2plus.twr` : Xilinx timing report
+

fpga/docs/usrp2/customize_signal_chain.md

@@ -0,0 +1,49 @@
+# Customizing the Signal Chain in Generation 2 products
+
+## Adding DSP logic to Generation 2 products
+
+As part of the USRP FPGA build-framework, there are several convenient places
+for users to insert custom DSP modules into the transmit and receive chains.
+
+- Before the DDC module
+- After the DDC module
+- Replace the DDC module
+- Before the DUC module
+- After the DUC module
+- Replace the DUC module
+- As an RX packet engine
+- As an TX packet engine
+
+### Customizing the top level makefile
+
+Each USRP device has a makefile associated with it. This makefile contains all
+of the necessary build rules. When making a customized FPGA design, start by
+copying the current makefile for your device. Makefiles can be found in
+`usrp2/top/{product}/Makefile`
+
+Edit your new makefile:
+- Set BUILD_DIR to a unique directory name
+- Set CUSTOM_SRCS for your verilog sources
+- Set CUSTOM_DEFS (see section below)
+
+### Inserting custom modules
+
+CUSTOM_DEFS is a string of space-separate key-value pairs. Set the CUSTOM_DEFS
+variable so the FPGA fabric glue will substitute your custom modules into the
+DSP chain.
+
+Example:
+
+    CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine"
+
+Where `my_tx_engine` and `my_rx_engine` are the names of custom verilog modules.
+
+The following module definition keys are possible (X is a DSP number):
+
+- `TX_ENG<X>_MODULE`: Set the module for the transmit chain engine.
+- `RX_ENG<X>_MODULE`: Set the module for the receive chain engine.
+- `RX_DSP<X>_MODULE`: Set the module for the transmit dsp chain.
+- `TX_DSP<X>_MODULE`: Set the module for the receive dsp chain.
+
+Examples of custom modules can be found in the Verilog files in `usrp2/custom/`.
+

fpga/docs/usrp3/build_instructions.md

@@ -0,0 +1,240 @@
+# Generation 3 USRP Build Documentation
+
+## Dependencies and Requirements
+
+### Dependencies
+
+The USRP FPGA build system requires a UNIX-like environment with the following dependencies
+
+- [Xilinx Vivado 2019.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2019-1.html) (For 7 Series FPGAs)
+- [Xilinx ISE 14.7](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v2012_4---14_7.html) (For all other FPGAs)
+- [GNU Make 3.6+](https://www.gnu.org/software/make/)
+- [GNU Bash 4.0+](https://www.gnu.org/software/bash/)
+- [Python 2.7.x](https://www.python.org/)
+- [Doxygen](http://www.stack.nl/~dimitri/doxygen/index.html) (Optional: To build the manual)
+- [ModelSim](https://www.mentor.com/products/fv/modelsim/) (Optional: For simulation)
+
+The following USRPs work with the free WebPack versions:
+- USRP E310/E312/E313
+
+### What FPGA does my USRP have?
+
+- USRP B200: Spartan 6 XC6SLX75
+- USRP B200mini: Spartan 6 XC6SLX75
+- USRP B210: Spartan 6 XC6SLX150
+- USRP X300: Kintex 7 XC7K325T (7 Series)
+- USRP X310: Kintex 7 XC7K410T (7 Series)
+- USRP E310: Zynq-7000 XC7Z020 (7 Series)
+- USRP E320: Zynq-7000 XC7Z045 (7 Series)
+- USRP N300: Zynq-7000 XC7Z035 (7 Series)
+- USRP N310/N320: Zynq-7000 XC7Z100 (7 Series)
+
+### Requirements
+
+- [Xilinx Vivado Release Notes](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug973-vivado-release-notes-install-license.pdf)
+- [Xilinx ISE Platform Requirements](http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/irn.pdf)
+
+## Build Environment Setup
+
+### Download and Install Xilinx Tools
+
+Download and install Xilinx Vivado or Xilinx ISE based on the target USRP.
+- The recommended installation directory is `/opt/Xilinx/` for Linux and `C:\Xilinx` in Windows
+- Please check the Xilinx Requirements document above for the FPGA technology used by your USRP device.
+- You may need to acquire a synthesis and implementation license from Xilinx to build some USRP designs.
+- You may need to acquire a simulation license from Xilinx to run some testbenches
+
+### Download and Install ModelSim (Optional)
+
+Download and install Mentor ModelSim using the link above.
+- The recommended installation directory is `/opt/mentor/modelsim` for Linux and `C:\mentor\modelsim` in Windows
+- Supported versions are PE, DE, SE, DE-64 and SE-64
+- You may need to acquire a license from Mentor Graphics to run ModelSim
+
+### Setting up build dependencies on Ubuntu
+
+You can install all the dependencies through the package manager:
+
+    sudo apt-get install python bash build-essential doxygen
+
+Your actual command may differ.
+
+### Setting up build dependencies on Fedora
+
+You can install all the dependencies through the package manager:
+
+    sudo yum -y install python bash make doxygen
+
+Your actual command may differ.
+
+### Setting up build dependencies on Windows (using Cygwin)
+
+**NOTE**: Windows is only supported with Vivado. The build system does not support Xilinx ISE in Windows.
+
+Download the latest version on [Cygwin](https://cygwin.com/install.html) (64-bit is preferred on a 64-bit OS)
+and install it using [these instructions](http://x.cygwin.com/docs/ug/setup-cygwin-x-installing.html).
+The following additional packages are also required and can be selected in the GUI installer
+
+    python patch patchutils bash make doxygen
+
+## Build Instructions (Xilinx Vivado only)
+
+### Makefile based Builder
+
+- Navigate to `usrp3/top/{project}` where project is:
+  + x300: For USRP X300 and USRP X310
+  + e31x: For USRP E310
+  + e320: For USRP E320
+  + n3xx: For USRP N300/N310/N320
+
+- To add vivado to the PATH and to setup up the Ettus Xilinx build environment run
+  + `source setupenv.sh` (If Vivado is installed in the default path /opt/Xilinx/Vivado) _OR_
+  + `source setupenv.sh --vivado-path=<VIVADO_PATH>` (where VIVADO_PATH is a non-default installation path)
+
+- To build a binary configuration bitstream run `make <target>`
+  where the target is specific to each product. To get a list of supported targets run
+  `make help`.
+
+- The build output will be specific to the product and will be located in the
+  `usrp3/top/{project}/build` directory. Run `make help` for more information.
+
+### Environment Utilies
+
+The build environment also defines many ease-of-use utilites. Please use the \subpage md_usrp3_vivado_env_utils "Vivado Utility Reference" page for
+a list and usage information
+
+## Build Instructions (Xilinx ISE only)
+
+### Makefile based Builder
+
+- To add xtclsh to the PATH and to setup up the Xilinx build environment run
+  + `source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh` (64-bit platform)
+  + `source <install_dir>/Xilinx/14.7/ISE_DS/settings32.sh` (32-bit platform)
+
+- Navigate to `usrp3/top/{project}` where project is:
+  + b200: For USRP B200 and USRP B210
+  + b200mini: For USRP B200mini
+
+- To build a binary configuration bitstream run `make <target>`
+  where the target is specific to each product. To get a list of supported targets run
+  `make help`.
+
+- The build output will be specific to the product and will be located in the
+  `usrp3/top/{project}/build` directory. Run `make help` for more information.
+
+## Targets and Outputs
+
+### B2x0 Targets and Outputs
+
+#### Supported Targets
+- B200:  Builds the USRP B200 design.
+- B210:  Builds the USRP B210 design.
+
+#### Outputs
+- `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
+- `build/usrp_<product>_fpga.bin` : Configuration bitstream without header
+- `build/usrp_<product>_fpga.syr` : Xilinx system report
+- `build/usrp_<product>_fpga.twr` : Xilinx timing report
+
+### X3x0 Targets and Outputs
+
+#### Supported Targets
+- X310_1G:  USRP X310. 1GigE on both SFP+ ports. DRAM TX FIFO (experimental!).
+- X300_1G:  USRP X300. 1GigE on both SFP+ ports. DRAM TX FIFO (experimental!).
+- X310_HG:  USRP X310. 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. DRAM TX FIFO (experimental!).
+- X300_HG:  USRP X300. 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. DRAM TX FIFO (experimental!).
+- X310_XG:  USRP X310. 10GigE on both SFP+ ports. DRAM TX FIFO (experimental!).
+- X300_XG:  USRP X300. 10GigE on both SFP+ ports. DRAM TX FIFO (experimental!).
+- X310_HA:  USRP X310. 1GigE on SFP+ Port0, Aurora on SFP+ Port1. DRAM TX FIFO.
+- X300_HA:  USRP X300. 1GigE on SFP+ Port0, Aurora on SFP+ Port1. DRAM TX FIFO.
+- X310_XA:  USRP X310. 10GigE on SFP+ Port0, Aurora on SFP+ Port1. DRAM TX FIFO.
+- X300_XA:  USRP X300. 10GigE on SFP+ Port0, Aurora on SFP+ Port1. DRAM TX FIFO.
+- X310_RFNOC_HG:  USRP X310. 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. RFNoC CEs enabled
+- X300_RFNOC_HG:  USRP X300. 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. RFNoC CEs enabled
+- X310_RFNOC_XG:  USRP X310. 10GigE on both SFP+ ports. RFNoC CEs enabled.
+- X300_RFNOC_XG:  USRP X300. 10GigE on both SFP+ ports. RFNoC CEs enabled.
+- X310_RFNOC_HLS_HG:  USRP X310. 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. RFNoC CEs enabled + Vivado HLS
+- X300_RFNOC_HLS_HG:  USRP X300. 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. RFNoC CEs enabled + Vivado HLS
+
+#### Outputs
+- `build/usrp_<product>_fpga_<image_type>.bit` :    Configuration bitstream with header
+- `build/usrp_<product>_fpga_<image_type>.bin` :    Configuration bitstream without header
+- `build/usrp_<product>_fpga_<image_type>.lvbitx` : Configuration bitstream for PCIe (NI-RIO)
+- `build/usrp_<product>_fpga_<image_type>.rpt` :    System, utilization and timing summary report
+
+### E310 Targets and Outputs
+
+#### Supported Targets
+- E310_SG1 or E310 :  Builds the USRP E310 speed grade 1.
+- E310_SG3 or E310_sg3:  Builds the USRP E310 speed grade 3.
+- E310_SG1_RFNOC or E310_RFNOC:  Builds the USRP E310 RFNoC image for speed grade 1.
+- E310_SG3_RFNOC or E310_RFNOC_sg3:  Builds the USRP E310 RFNoC image for speed grade 3.
+
+#### Outputs
+- `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
+- `build/usrp_<product>_fpga.dts` : Device tree overlay
+- `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
+
+### E320 Targets and Outputs
+
+#### Supported Targets
+- E320_1G: 1GigE on SFP+ Port.
+- E320_XG: 10GigE on SFP+ Port.
+- E320_AA: Aurora on SFP+ Port.
+- E320_RFNOC_1G: 1GigE on SFP+ Port. RFNOC CEs enabled.
+- E320_RFNOC_XG: 10GigE on SFP+ Port. RFNOC CEs enabled.
+- E320_RFNOC_AA: Aurora on SFP+ Port. RFNOC CEs enabled.
+
+#### Outputs
+- `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
+- `build/usrp_<product>_fpga.dts` : Device tree overlay
+- `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
+
+### N3XX Targets and Outputs
+
+#### Supported Targets
+
+The targets depend on the actual hardware the FPGA image is being deployed to.
+Unlike the X300 Series, the daughterboards are an integral part of the module
+and not meant to be removed. Therefore, the target is specific to the
+combination of motherboard and daughterboards.
+
+- N300_AA: Aurora on both SFP+ ports
+- N300_HA: 1GigE on SFP0, Aurora on SFP1
+- N300_HG: 1GigE on SFP0, 10GigE on SFP1
+- N300_WX: White Rabbing on SFP0, 10GigE on SFP1
+- N300_XA: 10GigE on SFP0, Aurora on SFP1
+- N300_XG: 10GigE on both SFP+ ports
+- N310_AA: Aurora on both SFP+ ports
+- N310_HA: 1GigE on SFP0, Aurora on SFP1
+- N310_HG: 1GigE on SFP0, 10GigE on SFP1
+- N310_WX: White Rabbing on SFP0, 10GigE on SFP1
+- N310_XA: 10GigE on SFP0, Aurora on SFP1
+- N310_XG: 10GigE on both SFP+ ports
+- N320_AQ: 10GigE on both SFP+ ports, Aurora on QSFP+ ports
+- N320_HG: 1GigE on SFP0, 10GigE on SFP1
+- N320_XG: 10GigE on both SFP+ ports
+- N320_XQ: White Rabbit on SFP0, 10 GigE on QSFP0 and QSFP1
+
+For the N320 targets see also the N320 manual page on the UHD manual.
+
+All targets also support an RFNOC version (e.g. `N300_RFNOC_XG`), which enables
+custom selection of RFNoC blocks.
+
+
+#### Outputs
+- `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
+- `build/usrp_<product>_fpga.dts` : Device tree overlay
+- `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
+
+### Additional Build Options
+
+It is possible to make a target and specific additional options in the form VAR=VALUE in
+the command. For example: `make B210 PROJECT_ONLY=1`
+
+Here are the supported options:
+
+- `PROJECT_ONLY=1` : Only create a Xilinx project for the specified target(s). Useful for use with the ISE GUI. (*NOTE*: this option is only valid for Xilinx ISE)
+- `EXPORT_ONLY=1` :  Export build targets from a GUI build to the build directory. Requires the project in build-\*_\* to be built. (*NOTE*: this option is only valid for Xilinx ISE)
+- `GUI=1` : Run the Vivado build in GUI mode instead of batch mode. After the build is complete, Vivado provides an option to save the fully configured project for customization (*NOTE*: this option is only valid for Xilinx Vivado)
+

fpga/docs/usrp3/sim/libs_axi.md

@@ -0,0 +1,266 @@
+# AXI Interface Libraries
+
+## AXI4 Stream (sim\_axis\_lib.vh)
+
+Defines ``axis_t``, an AXI Stream bus interface that implements several tasks to send and 
+receive data on the bus.
+
+### Definition
+
+    interface axis_t #(parameter DWIDTH = 64)
+                      (input clk);
+      logic [DWIDTH-1:0]  tdata;
+      logic               tvalid;
+      logic               tlast;
+      logic               tready;
+  
+    modport master (output tdata, output tvalid, output tlast, input tready);
+    modport slave (input tdata, input tvalid, input tlast, output tready);
+
+
+### Operations
+
+#### push\_word
+
+    // Push a word onto the AXI-Stream bus and wait for it to transfer
+    // Args:
+    // - word: The data to push onto the bus
+    // - eop (optional): End of packet (asserts tlast)
+
+#### push\_bubble
+
+    // Push a bubble cycle onto the AXI-Stream bus
+
+#### pull\_word
+
+    // Wait for a sample to be transferred on the AXI Stream
+    // bus and return the data and last
+    // Args:
+    // - word: The data pulled from the bus
+    // - eop: End of packet (tlast)
+
+#### wait\_for\_bubble
+
+    // Wait for a bubble cycle on the AXI Stream bus
+
+#### wait\_for\_pkt
+
+    // Wait for a packet to finish on the bus
+
+#### push\_rand\_pkt
+
+    // Push a packet with random data onto to the AXI Stream bus
+    // Args:
+    // - num_samps: Packet size.
+
+#### push\_ramp\_pkt
+
+    // Push a packet with a ramp on to the AXI Stream bus
+    // Args:
+    // - num_samps: Packet size.
+    // - ramp_start: Start value for the ramp
+    // - ramp_inc: Increment per clock cycle
+
+## Compressed VITA [CHDR] (sim\_chdr\_lib.vh)
+
+Defines ``cvita_stream_t``, an AXI Stream bus interface that implements the CHDR protocol and 
+several tasks to send and receive data on the bus.
+
+### CHDR
+
+    typedef enum logic [1:0] {
+      DATA=2'b00, FC=2'b01, CMD=2'b10, RESP=2'b11
+    } cvita_pkt_t;
+      
+    typedef struct packed {
+      logic [31:0]  sid;
+      logic [15:0]  length;
+      logic [11:0]  seqno;
+      logic         eob;
+      logic         has_time;
+      cvita_pkt_t   pkt_type;
+      logic [63:0]  timestamp;
+    } cvita_hdr_t;
+
+#### Operations
+
+ - ``flatten_chdr_no_ts``: Flatten header struct to a 64-bit bus. No timestamp.
+ - ``unflatten_chdr_no_ts``: Decode a 64-bit header and populate the ``cvita_hdr_t`` struct. No timestamp.
+ - ``unflatten_chdr``: Decode a 64-bit header and populate the ``cvita_hdr_t`` struct. Timestamp supported.
+
+### CVITA Stream Type
+
+#### Definition
+
+    interface cvita_stream_t (input clk);
+      axis_t #(.DWIDTH(64)) axis (.clk(clk));
+
+#### push\_hdr
+
+    // Push a CVITA header into the stream
+    // Args:
+    // - hdr: The header to push
+  
+#### push\_data
+
+    // Push a word onto the AXI-Stream bus and wait for it to transfer
+    // Args:
+    // - word: The data to push onto the bus
+    // - eop: End of packet (asserts tlast)
+
+#### push\_bubble
+
+    // Push a bubble cycle on the AXI-Stream bus
+
+#### pull\_word
+
+    // Wait for a sample to be transferred on the AXI Stream
+    // bus and return the data and last
+    // Args:
+    // - word: The data pulled from the bus
+    // - eop: End of packet (tlast)
+
+#### wait\_for\_bubble
+
+    // Wait for a bubble cycle on the AXI Stream bus
+
+#### wait\_for\_pkt
+
+    // Wait for a packet to finish on the bus
+
+#### wait\_for\_pkt\_get\_info
+
+    // Wait for a packet to finish on the bus and extract the header and payload statistics.
+    
+    typedef struct packed {
+      logic [31:0]  count;
+      logic [63:0]  sum;
+      logic [63:0]  min;
+      logic [63:0]  max;
+      logic [63:0]  crc;
+    } cvita_stats_t;
+
+#### push\_rand\_pkt
+
+    // Push a packet with random data onto to the AXI Stream bus
+    // Args:
+    // - num_samps: Packet size.
+    // - hdr: Header to attach to packet (length will be ignored)
+    // - timestamp: Optional timestamp
+
+#### push\_ramp\_pkt
+
+    // Push a packet with a ramp on to the AXI Stream bus
+    // Args:
+    // - num_samps: Packet size.
+    // - ramp_start: Start value for the ramp
+    // - ramp_inc: Increment per clock cycle
+    // - hdr: Header to attach to packet (length will be ignored)
+    // - timestamp: Optional timestamp
+
+## Memory Mapped AXI4 (sim\_axi4\_lib.vh)
+
+Defines the following interfaces to group signals in the AXI4 bus.
+WIP: No functions or tasks implemented yet.
+
+#### Address
+
+    interface axi4_addr_t #(parameter AWIDTH=32, parameter IDWIDTH=4)
+                           (input clk);
+    
+      logic [IDWIDTH-1:0] id;
+      logic [AWIDTH-1:0]  addr;
+      logic [7:0]         len;
+      logic [2:0]         size;
+      logic [1:0]         burst;
+      logic               lock;
+      logic [3:0]         cache;
+      logic [2:0]         prot;
+      logic [3:0]         qos;
+      logic [3:0]         region;
+      logic               user;
+      logic               valid;
+      logic               ready;
+    
+      modport master (output id,addr,len,size,burst,lock,cache,prot,qos,valid, input ready);
+      modport slave (input id,addr,len,size,burst,lock,cache,prot,qos,valid, output ready);
+    
+    endinterface
+    
+#### Write Data
+
+    interface axi4_wdata_t #(parameter DWIDTH=64)
+                           (input clk);
+    
+      logic [DWIDTH-1:0]      data;
+      logic [(DWIDTH/8)-1:0]  strb;
+      logic                   last;
+      logic                   user;
+      logic                   valid;
+      logic                   ready;
+    
+      modport master(output data,strb,last,valid, input ready);
+      modport slave(input data,strb,last,valid, output ready);
+    
+    endinterface
+
+#### Write Response
+
+    interface axi4_resp_t #(parameter IDWIDTH=4)
+                           (input clk);
+    
+      logic               ready;
+      logic [IDWIDTH-1:0] id;
+      logic [1:0]         resp;
+      logic               user;
+      logic               valid;
+    
+      modport master(output ready, input id,resp,valid);
+      modport slave(input ready, output id,resp,valid);
+    
+    endinterface
+
+#### Read Data
+
+    interface axi4_rdata_t #(parameter DWIDTH=64, parameter IDWIDTH=4)
+                           (input clk);
+    
+      logic               ready;
+      logic [IDWIDTH-1:0] id;
+      logic [DWIDTH-1:0]  data;
+      logic [1:0]         resp;
+      logic               user;
+      logic               last;
+      logic               valid;
+    
+      modport master(output ready, input id,data,resp,last,valid);
+      modport slave(input ready, output id,data,resp,last,valid);
+    
+    endinterface
+
+#### Meta: AXI4 Writer
+
+    interface axi4_wr_t #(parameter DWIDTH=64, parameter AWIDTH=32, parameter IDWIDTH=4)
+                         (input clk);
+    
+      axi4_addr_t  #(.AWIDTH(AWIDTH), .IDWIDTH(IDWIDTH)) addr (.clk(clk));
+      axi4_wdata_t #(.DWIDTH(DWIDTH))                    data (.clk(clk));
+      axi4_resp_t  #(.IDWIDTH(IDWIDTH))                  resp (.clk(clk));
+    
+      modport master(output addr, output data, input resp);
+      modport slave(input addr, input data, output resp);
+    
+    endinterface
+    
+#### Meta: AXI4 Reader
+
+    interface axi4_rd_t #(parameter DWIDTH=64, parameter AWIDTH=32, parameter IDWIDTH=4)
+                         (input clk);
+    
+      axi4_addr_t  #(.AWIDTH(AWIDTH), .IDWIDTH(IDWIDTH)) addr (.clk(clk));
+      axi4_rdata_t #(.DWIDTH(DWIDTH), .IDWIDTH(IDWIDTH)) data (.clk(clk));
+    
+      modport master(output addr, output data);
+      modport slave(input addr, input data);
+    
+    endinterface

fpga/docs/usrp3/sim/libs_general.md

@@ -0,0 +1,188 @@
+# General Purpose Libraries
+
+## Execution and Reporting (sim\_exec\_report.vh)
+
+Macros to do boilerplate testbench initialization and utilities to define test cases
+
+#### TEST\_BENCH\_INIT
+
+    // Initializes state for a test bench.
+    // This macro *must be* called within the testbench module but 
+    // outside the primary initial block
+    // Its sets up boilerplate code for:
+    // - Logging to console
+    // - Test execution tracking
+    // - Gathering test results
+    // - Bounding execution time based on the SIM_RUNTIME_US vdef
+    //
+    // Usage: `TEST_BENCH_INIT(test_name,min_tc_run_count,ns_per_tick)
+    // where
+    //  - tb_name:          Name of the testbench. (Only used during reporting)
+    //  - min_tc_run_count: Number of test cases in testbench. (Used to detect stalls and inf-loops)
+    //  - ns_per_tick:      The time_unit_base from the timescale declaration
+    //
+
+#### TEST\_CASE\_START
+
+    // Indicates the start of a test case
+    // This macro *must be* called inside the primary initial block
+    //
+    // Usage: `TEST_CASE_START(test_name)
+    // where
+    //  - test_name:        The name of the test.
+    //
+
+#### TEST\_CASE\_DONE
+    // Indicates the end of a test case
+    // This macro *must be* called inside the primary initial block
+    // The pass/fail status of test case is determined based on the
+    // the user specified outcome and the number of fatal or error
+    // ASSERTs triggered in the test case.
+    //
+    // Usage: `TEST_CASE_DONE(test_result)
+    // where
+    //  - test_result:  User specified outcome
+    //
+
+#### ASSERT\_FATAL
+
+    // Wrapper around a an assert.
+    // ASSERT_FATAL throws an error assertion and halts the simulator
+    // if cond is not satisfied
+    //
+    // Usage: `ASSERT_FATAL(cond,msg)
+    // where
+    //  - cond: Condition for the assert
+    //  - msg:  Message for the assert
+    //
+
+#### ASSERT\_ERROR
+
+    // Wrapper around a an assert.
+    // ASSERT_ERROR throws an error assertion and fails the test case
+    // if cond is not satisfied. The simulator will *not* halt
+    //
+    // Usage: `ASSERT_ERROR(cond,msg)
+    // where
+    //  - cond: Condition for the assert
+    //  - msg:  Message for the assert
+    //
+
+#### ASSERT\_WARNING
+
+    // Wrapper around a an assert.
+    // ASSERT_WARNING throws an warning assertion but does not fail the
+    // test case if cond is not satisfied. The simulator will *not* halt
+    //
+    // Usage: `ASSERT_WARNING(cond,msg)
+    // where
+    //  - cond: Condition for the assert
+    //  - msg:  Message for the assert
+    //
+
+## Clocks and Resets (sim\_clks\_rsts.vh)
+
+Shortcut macros to create typical clock and reset signals.
+
+#### DEFINE\_CLK
+
+    // Generates a persistent clock that starts at t=0 and runs forever
+    //
+    // Usage: `DEFINE_CLK(clk_name,period,duty_cycle)
+    // where
+    //  - clk_name:   The clock net to be generated
+    //  - period:     Period of the clock in simulator ticks
+    //  - duty_cycle: Percentage duty cycle
+    //
+
+#### DEFINE\_LATE\_START\_CLK
+
+    // Generates a clock that starts at the specified time and runs forever
+    //
+    // Usage: `DEFINE_LATE_START_CLK(clk_name,period,duty_cycle,start_time,start_time_res)
+    // where
+    //  - clk_name:   The clock net to be generated
+    //  - period:     Period of the clock in simulator ticks
+    //  - duty_cycle: Percentage duty cycle
+    //  - start_time: Start time for clock in simulator ticks
+    //  - start_time_res: Start time resolution (must be > timescale increment and < start_time)
+    //
+
+#### DEFINE_RESET
+
+    // Generates an active high reset
+    //
+    // Usage: `DEFINE_RESET(reset_name,reset_time,reset_duration)
+    // where
+    //  - reset_name:     The reset net to be generated
+    //  - reset_time:     Time at which reset will be asserted (i.e. rst=1)
+    //  - reset_duration: Duration of reset assertion
+    //
+
+#### DEFINE_RESET_N
+
+    // Generates an active low reset
+    //
+    // Usage: `DEFINE_RESET_N(reset_name,reset_time,reset_duration)
+    // where
+    //  - reset_name:     The reset net to be generated
+    //  - reset_time:     Time at which reset will be asserted (i.e. rst=0)
+    //  - reset_duration: Duration of reset assertion
+    //
+
+## File I/O (sim\_file\_io.sv)
+
+### interface data\_file\_t
+
+Defines a ``data_file_t`` interface with the following functions:
+
+#### ctor
+
+    // Create a handle to a data_file with
+    // - FILENAME: Name of the file
+    // - FORMAT: Data format (HEX, DEC, OCT, BIN, FLOAT)
+    // - DWIDTH: Width of each element stored in the file (one line per word)
+    //
+
+#### open
+
+    // Open the data file for reading or writing.
+    //
+    // Usage: open(mode)
+    // where
+    //  - mode: RW mode (Choose from: READ, WRITE, APPEND)
+    //
+
+#### close
+
+    // Close an open data file. No-op if file isn't already open
+    //
+    // Usage: close()
+    //
+
+#### is_eof
+
+    // Is end-of-file reached.
+    //
+    // Usage: is_eof() Returns eof
+    // where
+    // - eof: A boolean
+    //
+
+#### readline
+
+    // Read a line from the datafile
+    //
+    // Usage: readline() Returns data
+    // where
+    // - data: A logic array of width DWIDTH containing the read word
+    //
+
+#### writeline
+
+    // Write a line to the datafile
+    //
+    // Usage: writeline(data) 
+    // where
+    // - data: A logic array of width DWIDTH to write to the file
+    //

fpga/docs/usrp3/sim/running_testbenches.md

@@ -0,0 +1,133 @@
+# Running a Testbench
+
+Each executable testbench has its own Makefile that automatically pulls in support
+for all supported simulators. The build infrastructure supports the following simulators:
+
+ - Xilinx Vivado (XSim)
+ - Mentor Graphics ModelSim (may require an additional license)
+
+
+In general running ``make <sim_target>`` will run the
+simulation and report results in the console. Running ``make help`` will print out
+all supported simulator targets. Currently, the following targets will work:
+
+    Supported Targets:
+    ipclean:    Cleanup all IP intermediate files
+    clean:      Cleanup all simulator intermediate files
+    cleanall:   Cleanup everything!
+    xsim:       Run the simulation using the Xilinx Vivado Simulator
+    xclean:     Cleanup Xilinx Vivado Simulator intermediate files
+    vsim:       Run the simulation using Modelsim
+    vclean:     Cleanup Modelsim intermediate files
+
+
+## Using Xilinx Vivado XSim
+
+XSim is the built-in simulator in the Xilinx Vivado toolchain. If you already met the
+prerequisites for building an FPGA image, then you don't need to install anything else.
+
+Follow these steps to run a testbench:
+
+ - Navigate to the directory that contains the top level testbench and Makefile
+ - Run the setenv.sh script for the USRP product that you are trying to simulate
+
+   ``$ source <repo>/usrp3/top/<product>/setupenv.sh``
+
+   This step is required even if the simulation is generic because the toolchain requires
+   an FPGA part number to load simulation models.
+ - Run the simulator specific target
+
+   ``$ make xsim``
+
+
+## Using Mentor Graphics ModelSim
+
+ModelSim is a third-party simulation tool that is compatible with Vivado and the USRP
+FPGA build infrastructure.
+
+Use the following one-time setup to install and configure Modelsim on your system
+
+ - Install Modelsim from the [Mentor Graphics](http://www.mentor.com/) website. 
+   It is recommended that you install it to the default location (/opt/mentor/modelsim)
+ - Run the setenv.sh script for the USRP product that you are trying to simulate
+
+   ``$ source <repo>/usrp3/top/<product>/setupenv.sh``
+
+   This step is required even if the simulation is generic because the toolchain requires
+   an FPGA part number to load simulation models.
+ - Build the Xilinx simulation libraries
+   ``$ build_simlibs``
+
+
+To validate that everything was install properly run ``setupenv.sh`` again. You should see the following
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    - Modelsim: Found (/opt/mentor/modelsim/modeltech/bin)
+    - Modelsim Compiled Libs: Found (/opt/Xilinx/Vivado/2014.4/modelsim)
+    
+    Environment successfully initialized.
+
+Follow these steps to run a testbench:
+
+ - Navigate to the directory that contains the top level testbench and Makefile
+ - Run the setenv.sh script for the USRP product that you are trying to simulate
+
+   ``$ source <repo>/usrp3/top/<product>/setupenv.sh``
+
+   This step is required even if the simulation is generic because the toolchain requires
+   an FPGA part number to load simulation models.
+ - Run the simulator specific target
+
+   ``$ make vsim``
+
+
+## Troubleshooting
+
+#### Vivado Not Found
+
+If running the setupenv.sh script return an error like the following:
+
+    Vivado: Not found! (ERROR.. Builds and simulations will not work)
+
+then it is possible that Vivado was not installed or it was not installed in the default
+location. If Vivado is installed in a non-default location, just run the following:
+
+  ``$ source <repo>/usrp3/top/<product>/setupenv.sh --vivado-path=<PATH>``
+
+#### Modelsim Not Found
+
+If running the setupenv.sh script return an error like the following:
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    - Modelsim: Not found! (WARNING.. Simulations with vsim will not work)
+    
+    Environment successfully initialized.
+
+or something like this (even when Modelsim is installed)
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    
+    Environment successfully initialized.
+
+then it is possible that Modelsim was not installed or it was not installed in the default
+location. If Modelsim is installed in a non-default location, just run the following:
+
+  ``$ source <repo>/usrp3/top/<product>/setupenv.sh --modelsim-path=<PATH>``
+
+#### Modelsim Simulation Libraries Not Found
+
+If running the setupenv.sh script return an error like the following:
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    - Modelsim: Found (/opt/mentor/modelsim/modeltech/bin)
+    - Modelsim Compiled Libs: Not found! (Run build_simlibs to generate them.)
+    
+    Environment successfully initialized.
+
+just run the following
+
+    $ build_simlibs

fpga/docs/usrp3/sim/writing_testbenches.md

@@ -0,0 +1,471 @@
+# Writing a Testbench
+
+Writing a unit test or system level test is easy with the Vivado makefile infrastructure! 
+Most of the overhead of building and running a testbench is handled by the build tools. 
+Even recurring tasks like reporting and monitoring are implemented by framework libraries.
+
+Each executable FPGA unit test must have the following components:
+
+1. A Makefile
+2. A Testbench top-level module
+
+## Testbench Makefile
+
+The Testbench Makefile tell the build tools what to build, where to build it, dependency information and runtime information.
+The build infrastructure will handle the how-to part for each supported simulation tool.
+
+Here is a sample Makefile (you are encouraged to use this as a starting point)
+
+    #
+    # Copyright 2015 Ettus Research LLC
+    #
+    
+    #-------------------------------------------------
+    # Top-of-Makefile
+    #-------------------------------------------------
+    # Define BASE_DIR to point to the "top" dir
+    BASE_DIR = $(abspath ../../..)
+    # Include viv_sim_preample after defining BASE_DIR
+    include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+    
+    #-------------------------------------------------
+    # Design Specific
+    #-------------------------------------------------
+    # Define part using PART_ID (<device>/<package>/<speedgrade>)
+    ARCH = kintex7
+    PART_ID = xc7k410t/ffg900/-2
+    
+    # Include makefiles and sources for the DUT and its dependencies
+    include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+    include $(BASE_DIR)/../lib/axi/Makefile.srcs
+    include $(BASE_DIR)/../lib/control/Makefile.srcs
+    
+    DESIGN_SRCS = $(abspath \
+    $(FIFO_SRCS) \
+    $(AXI_SRCS) \
+    $(CONTROL_LIB_SRCS) \
+    )
+    
+    #-------------------------------------------------
+    # IP Specific
+    #-------------------------------------------------
+    # If simulation contains IP, define the IP_DIR and point
+    # it to the base level IP directory
+    IP_DIR = ../../ip
+    
+    # Include makefiles and sources for all IP components
+    # *after* defining the IP_DIR
+    include $(IP_DIR)/ddr3_32bit/Makefile.inc
+    include $(IP_DIR)/axi_intercon_2x64_128/Makefile.inc
+    include $(IP_DIR)/fifo_short_2clk/Makefile.inc
+    include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
+    include $(IP_DIR)/axi4_bram_1kx64/Makefile.inc
+    
+    DESIGN_SRCS += $(abspath \
+    $(IP_DDR3_32BIT_SRCS) \
+    $(IP_AXI_INTERCON_2X64_128_SRCS) \
+    $(IP_FIFO_4K_2CLK_SRCS) \
+    $(IP_FIFO_SHORT_2CLK_SRCS) \
+    $(IP_AXI4_BRAM_1KX64_SRCS) \
+    )
+    
+    #-------------------------------------------------
+    # Testbench Specific
+    #-------------------------------------------------
+    include $(BASE_DIR)/../sim/general/Makefile.srcs
+    include $(BASE_DIR)/../sim/axi/Makefile.srcs
+    
+    # Define only one toplevel module
+    SIM_TOP = dram_fifo_tb
+    # Simulation runtime in microseconds
+    SIM_RUNTIME_US = 80
+    
+    SIM_SRCS = \
+    $(abspath dram_fifo_tb.sv) \
+    $(abspath axis_dram_fifo_single.sv) \
+    $(IP_DDR3_32BIT_SIM_OUTS) \
+    $(SIM_GENERAL_SRCS) \
+    $(SIM_AXI_SRCS)
+    
+    #-------------------------------------------------
+    # Bottom-of-Makefile
+    #-------------------------------------------------
+    # Include all simulator specific makefiles here
+    # Each should define a unique target to simulate
+    # e.g. xsim, vsim, etc and a common "clean" target
+    include $(BASE_DIR)/../tools/make/viv_simulator.mak
+
+You will notice that the Makefile has 5 distinct sections.
+
+### Section 1: Boilerplate
+
+    #-------------------------------------------------
+    # Top-of-Makefile
+    #-------------------------------------------------
+    # Define BASE_DIR to point to the "top" dir
+    BASE_DIR = $(abspath ../../..)
+    # Include viv_sim_preample after defining BASE_DIR
+    include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+Before declaring any variables or using any recipes, the following must be done (in order):
+
+- Define `BASE_DIR` to tell the build system where the `<repo>/usrp3/top` directory is relative to the
+  current testbench directory.
+- Include `viv_sim_preamble.mak` to initialize boilerplate variables and functions
+
+### Section 2: Design Specific
+
+    #-------------------------------------------------
+    # Design Specific
+    #-------------------------------------------------
+    # Define part using PART_ID (<device>/<package>/<speedgrade>)
+    ARCH = kintex7
+    PART_ID = xc7k410t/ffg900/-2
+    
+    # Include makefiles and sources for the DUT and its dependencies
+    include $(BASE_DIR)/../lib/fifo/Makefile.srcs
+    include $(BASE_DIR)/../lib/axi/Makefile.srcs
+    include $(BASE_DIR)/../lib/control/Makefile.srcs
+    
+    DESIGN_SRCS = $(abspath \
+    $(FIFO_SRCS) \
+    $(AXI_SRCS) \
+    $(CONTROL_LIB_SRCS) \
+    )
+
+This section contains pointers to sources and other variables for the DUT to function. In the 
+example above, we are including all sources from the lib/fifo, lib/axi, lib/control directories.
+
+The following makefile variables are special and must be defined:
+
+- `ARCH`: The architecture targeted for the simulation.
+- `PART_ID`: The exact part targeted for the simulation. Format: `<device>/<package>/<speedgrade>` 
+- `DESIGN_SRCS`: Space-separated paths to the DUT and all of its dependencies.
+
+### Section 3: IP Specific
+
+    #-------------------------------------------------
+    # IP Specific
+    #-------------------------------------------------
+    # If simulation contains IP, define the IP_DIR and point
+    # it to the base level IP directory
+    IP_DIR = ../../ip
+    
+    # Include makefiles and sources for all IP components
+    # *after* defining the IP_DIR
+    include $(IP_DIR)/ddr3_32bit/Makefile.inc
+    include $(IP_DIR)/axi_intercon_2x64_128/Makefile.inc
+    include $(IP_DIR)/fifo_short_2clk/Makefile.inc
+    include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
+    include $(IP_DIR)/axi4_bram_1kx64/Makefile.inc
+    
+    DESIGN_SRCS += $(abspath \
+    $(IP_DDR3_32BIT_SRCS) \
+    $(IP_AXI_INTERCON_2X64_128_SRCS) \
+    $(IP_FIFO_4K_2CLK_SRCS) \
+    $(IP_FIFO_SHORT_2CLK_SRCS) \
+    $(IP_AXI4_BRAM_1KX64_SRCS) \
+    )
+
+If the DUT depends on any Xilinx IP then this section is required. It tell the tools
+which IP cores need to be built in order to run the simulation. The IP specific Makefile
+includes handle the "how" part of building IP. As long as the correct Mafefile is included
+and the IP XCI sources are added to `DESIGN_SRCS`, the IP intermediates will be built correctly.
+
+The `IP_DIR` variable must be defined to point to the base ip directory that contains XCI sources. 
+
+### Section 4: Testbench Specific
+
+    #-------------------------------------------------
+    # Testbench Specific
+    #-------------------------------------------------
+    include $(BASE_DIR)/../sim/general/Makefile.srcs
+    include $(BASE_DIR)/../sim/axi/Makefile.srcs
+    
+    # Define only one toplevel module
+    SIM_TOP = dram_fifo_tb
+    # Simulation runtime in microseconds
+    SIM_RUNTIME_US = 80
+    
+    SIM_SRCS = \
+    $(abspath dram_fifo_tb.sv) \
+    $(abspath axis_dram_fifo_single.sv) \
+    $(IP_DDR3_32BIT_SIM_OUTS) \
+    $(SIM_GENERAL_SRCS) \
+    $(SIM_AXI_SRCS)
+
+This section contains all sources and parameters for the actual testbench. Any simulation
+dependency makefiles can be included here.
+
+The following variables must be defined:
+
+- `SIM_TOP`: The toplevel module name for the simulation project
+- `SIM_RUNTIME_US`: The maximum runtime of the simulation in microseconds. At this time $finish will be called to terminate the testbench.
+- `SIM_SRCS`: This is similar to DESIGN_SRCS except that that should contain a path to `SIM_TOP` and all of its dependencies.
+
+### Section 5: Tool Support
+
+    #-------------------------------------------------
+    # Bottom-of-Makefile
+    #-------------------------------------------------
+    # Include all simulator specific makefiles here
+    # Each should define a unique target to simulate
+    # e.g. xsim, vsim, etc and a common "clean" target
+    include $(BASE_DIR)/../tools/make/viv_simulator.mak
+
+Now that the Makefile knows all the basic information about the testbench, include tool-specific
+makefiles to implement simulation targets. Currently the following simulator makefiles exits:
+
+- ``<repo>/tools/make/viv_simulator.mak``
+
+Please refer to the next section for more information about targets
+
+
+## Testbench Top Level
+
+The top-level module will instantiate the DUT and implement self-checking behavior. 
+Test benches could be written in any language (SystemVerilog, Verilog, VHDL) but 
+to take advantage of our repository of simulation libraries, it is recommended that SystemVerilog be used.
+
+Here is a sample SystemVerilog top module (you are encouraged to use this as a starting point)
+
+    //
+    // Copyright 2015 Ettus Research LLC
+    //
+    
+    `timescale 1ns/1ps
+    `define NS_PER_TICK     1
+    `define NUM_TEST_CASES  3
+    
+    `include "sim_clks_rsts.vh"
+    `include "sim_exec_report.vh"
+    `include "sim_cvita_lib.sv"
+    
+    module example_fifo_tb();
+      `TEST_BENCH_INIT("example_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK)
+    
+      // Define all clocks and resets
+      `DEFINE_CLK(bus_clk, 1000/166.6667, 50) //166MHz bus_clk
+      `DEFINE_RESET(bus_rst, 0, 100)          //100ns for GSR to deassert
+    
+      cvita_stream_t chdr_i (.clk(bus_clk));
+      cvita_stream_t chdr_o (.clk(bus_clk));
+    
+      // Initialize DUT
+      axi_fifo #(.WIDTH(65), .SIZE(24)) dut_single (
+        .clk(bus_clk),
+        .reset(bus_rst),
+        .clear(1'b0),
+        
+        .i_tdata({chdr_i.axis.tlast, chdr_i.axis.tdata}),
+        .i_tvalid(chdr_i.axis.tvalid),
+        .i_tready(chdr_i.axis.tready),
+      
+        .o_tdata({chdr_o.axis.tlast, chdr_o.axis.tdata}),
+        .o_tvalid(chdr_o.axis.tvalid),
+        .o_tready(chdr_o.axis.tready),
+        
+        .space(),
+        .occupied()
+      );
+    
+      //Testbench variables
+      cvita_hdr_t   header, header_out;
+      cvita_stats_t stats;
+
+      //------------------------------------------
+      //Main thread for testbench execution
+      //------------------------------------------
+      initial begin : tb_main
+    
+        `TEST_CASE_START("Wait for reset");
+        while (bus_rst) @(posedge bus_clk);
+        `TEST_CASE_DONE((~bus_rst));
+        
+        repeat (200) @(posedge bus_clk);
+    
+        header = '{
+          pkt_type:DATA, has_time:0, eob:0, seqno:12'h666,
+          length:0, sid:$random, timestamp:64'h0};
+    
+        `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
+          chdr_o.axis.tready = 0;
+          chdr_i.push_ramp_pkt(16, 64'd0, 64'h100, header);
+          chdr_o.axis.tready = 1;
+          chdr_o.wait_for_pkt_get_info(header_out, stats);
+          `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");
+          `ASSERT_ERROR(header.sid==header_out.sid, "Bad packet: Wrong SID");
+          `ASSERT_ERROR(chdr_i.axis.tready,         "Bus not ready");
+        `TEST_CASE_DONE(1);
+
+        header = '{
+          pkt_type:DATA, has_time:1, eob:0, seqno:12'h666, 
+          length:0, sid:$random, timestamp:64'h0};
+    
+        `TEST_CASE_START("Concurrent read and write (single packet)");
+          chdr_o.axis.tready = 1;
+          fork
+              begin
+                chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header);
+              end
+              begin
+                chdr_o.wait_for_pkt_get_info(header_out, stats);
+              end
+          join
+        `ASSERT_ERROR(stats.count==20,      "Bad packet: Length mismatch");
+        `TEST_CASE_DONE(1);
+      end
+    endmodule
+
+
+Each testbench should have the following basic components:
+
+### Timescale Defines and Includes
+
+    `timescale 1ns/1ps
+    `define NS_PER_TICK     1
+    `define NUM_TEST_CASES  3
+    
+    `include "sim_clks_rsts.vh"
+    `include "sim_exec_report.vh"
+    `include "sim_cvita_lib.sv"
+
+In addition to the timescale, the infrastructure needs to know the number of 
+nanoseconds per simulator tick. This can be a floating point number.
+
+
+In addition to the timescale, you may include any Verilog/SystemVerilog headers here.
+
+### Main Module Definition
+
+    `include "sim_exec_report.vh"
+
+    module example_fifo_tb();
+      `TEST_BENCH_INIT("example_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK)
+
+      ...
+
+      //------------------------------------------
+      //Main thread for testbench execution
+      //------------------------------------------
+      initial begin : tb_main
+
+        ...
+
+      end
+    endmodule
+
+The name of the main module must match the ``SIM_TOP`` variable value in the Makefile.
+To register this module with the framework, the ``TEST_BENCH_INIT`` macro must be called.
+This macro is defined in ``<repo>/usrp3/sim/general/sim_exec_report.vh``.
+
+``TEST_BENCH_INIT``:
+
+    // Initializes state for a test bench.
+    // This macro *must be* called within the testbench module but 
+    // outside the primary initial block
+    // Its sets up boilerplate code for:
+    // - Logging to console
+    // - Test execution tracking
+    // - Gathering test results
+    // - Bounding execution time based on the SIM_RUNTIME_US vdef
+    //
+    // Usage: `TEST_BENCH_INIT(test_name,min_tc_run_count,ns_per_tick)
+    // where
+    //  - tb_name:          Name of the testbench. (Only used during reporting)
+    //  - min_tc_run_count: Number of test cases in testbench. (Used to detect stalls and inf-loops)
+    //  - ns_per_tick:      The time_unit_base from the timescale declaration
+
+The testbench must also have at least one initial block that consists tests cases (covered later). 
+For the sake of convention it should be called ``tb_main``. *All test cases must live in ``tb_main``*. You may
+have other initial block but they must not call macros from ``sim_exec_report.vh`` because the code
+there is not thread-safe.
+
+### Test Cases
+
+A test case in this context is defined as an independent entity that validates an aspect of the DUT behavior
+and which is independent from other test cases i.e. the result of one test case should ideally not affect others.
+
+
+Test cases are wrapped in the ``TEST_CASE_START`` and ``TEST_CASE_DONE`` macros:
+
+    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
+      chdr_o.axis.tready = 0;
+      chdr_i.push_ramp_pkt(16, 64'd0, 64'h100, header);
+      chdr_o.axis.tready = 1;
+      chdr_o.wait_for_pkt_get_info(header_out, stats);
+      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");
+      `ASSERT_ERROR(header.sid==header_out.sid, "Bad packet: Wrong SID");
+      `ASSERT_ERROR(chdr_i.axis.tready,         "Bus not ready");
+    `TEST_CASE_DONE(1);
+
+Here are the signatures of the two macros:
+
+``TEST_CASE_START``:
+
+    // Indicates the start of a test case
+    // This macro *must be* called inside the primary initial block
+    //
+    // Usage: `TEST_CASE_START(test_name)
+    // where
+    //  - test_name:        The name of the test.
+    //
+
+``TEST_CASE_DONE``:
+
+    // Indicates the end of a test case
+    // This macro *must be* called inside the primary initial block
+    // The pass/fail status of test case is determined based on the
+    // the user specified outcome and the number of fatal or error
+    // ASSERTs triggered in the test case.
+    //
+    // Usage: `TEST_CASE_DONE(test_result)
+    // where
+    //  - test_result:  User specified outcome
+    //
+
+In addition to the test case status, it is also possible to have asserts within
+a test case. We have wrappers for the different kinds of SystemVerilog asserts
+that additionally fail the test case in case the assert fails. An assert triggered
+in a test case will not affect the outcome of another (except for a fatal assert which
+halts the simulator). Supported assert macros:
+
+    // Wrapper around a an assert.
+    // ASSERT_FATAL throws an error assertion and halts the simulator
+    // if cond is not satisfied
+    //
+    // Usage: `ASSERT_FATAL(cond,msg)
+    // where
+    //  - cond: Condition for the assert
+    //  - msg:  Message for the assert
+    //
+    
+    
+    // Wrapper around a an assert.
+    // ASSERT_ERROR throws an error assertion and fails the test case
+    // if cond is not satisfied. The simulator will *not* halt
+    //
+    // Usage: `ASSERT_ERROR(cond,msg)
+    // where
+    //  - cond: Condition for the assert
+    //  - msg:  Message for the assert
+    //
+    
+    
+    // Wrapper around a an assert.
+    // ASSERT_WARNING throws an warning assertion but does not fail the
+    // test case if cond is not satisfied. The simulator will *not* halt
+    //
+    // Usage: `ASSERT_WARNING(cond,msg)
+    // where
+    //  - cond: Condition for the assert
+    //  - msg:  Message for the assert
+    //
+
+### Optional Libraries
+
+It is encouraged to use (and create) reusable libraries in product specific 
+test benches. Libraries can provide macros, modules, tasks and functions for
+ease-of-use with particular protocols and subsystems.
+
+The \ref md_usrp3_sim_writing_testbenches page has more information.

fpga/docs/usrp3/simulation.md

@@ -0,0 +1,11 @@
+# Simulation
+
+## Instructions
+
+ - \subpage md_usrp3_sim_running_testbenches "Running Testbenches"
+ - \subpage md_usrp3_sim_writing_testbenches "Writing Testbenches"
+
+## Library Reference
+
+ - \subpage md_usrp3_sim_libs_general "General Purpose"
+ - \subpage md_usrp3_sim_libs_axi "AXI"

fpga/docs/usrp3/vivado_env_utils.md

@@ -0,0 +1,87 @@
+# Vivado Environment Utilities
+
+## Environment Setup
+
+- Navigate to `usrp3/top/{project}` where project is:
+  + x300: For USRP X300 and USRP X310
+  + e3xx: For USRP E310
+  + e320: For USRP E320
+  + n3xx: For USRP N300/N310/N320
+
+- To setup up the Ettus Research Xilinx build environment run
+  + `source setupenv.sh` (If Vivado is installed in the default path /opt/Xilinx/Vivado) _OR_
+  + `source setupenv.sh --vivado-path=<VIVADO_PATH>` (where VIVADO_PATH is a non-default installation path)
+
+- This should not only enable building USRP FPGAs but also make the following utlities available
+
+## ModelSim Specific
+
+The setupenv.sh script will search the system for ModelSim installations and setup everything to run it natively and
+within Vivado. The currently support versions of ModelSim are PE, DE, SE, DE-64, SE-64.
+
+The following functions are also available in the environment:
+
+    build_simlibs: Build ModelSim simulation libraries for Vivado
+
+## IP Management
+
+### Create Vivado IP
+
+    viv_create_new_ip: Create a new Vivado IP instance and a Makefile for it
+
+    Usage: viv_create_new_ip <IP Name> <IP Location> <IP VLNV> <Product>
+    - <IP Name>: Name of the IP instance
+    - <IP Location>: Base location for IP
+    - <IP VLNV>: The vendor, library, name, and version (VLNV) string for the IP as defined by Xilinx
+    - <Product>: Product to generate IP for
+
+### Modify existing Vivado IP
+
+    viv_modify_ip: Modify an existing Vivado IP instance
+
+    Usage: viv_modify_ip <IP XCI Path>
+    - <IP XCI Path>: Path to the IP XCI file.
+
+### List supported Vivado IP
+
+    viv_ls_ip: List the items in the Vivado IP catalog
+
+    Usage: viv_ls_ip <Product>
+    - <Product>: Product to generate IP for.
+
+### Upgrade IP to the environment version of Vivado
+
+    viv_upgrade_ip: Upgrade one or more Xilinx IP targets
+
+    Usage: viv_upgrade_ip <IP Directory> [--recursive]
+    - <IP Directory>: Path to the IP XCI file.
+
+## Hardware Management
+
+### Launch Vivado Hardware Console
+
+    viv_hw_console: Launch the Tcl hardware console
+
+    Usage: viv_upgrade_ip
+
+### List connected JTAG devices
+
+    viv_jtag_list: List all devices (and their addresses) that are connected to the system using the Xilinx platform cable
+
+    Usage: viv_jtag_list
+
+### Program device over JTAG
+
+    viv_jtag_program: Downloads a bitfile to an FPGA device using Vivado
+
+    Usage: viv_jtag_program <Bitfile Path> [<Device Address> = 0:0]
+    - <Bitfile Path>: Path to a .bit FPGA configuration file
+    - <Device Address>: Address to the device in the form <Target>:<Device>
+                        Run viv_jtag_list to get a list of connected devices
+
+### Probe Xilinx bitfile
+
+    probe_bitfile: Probe a Xilinx bit file and report header information
+
+    Usage: probe_bitfile <Bitfile Path>
+    - <Bitfile Path>: Path to a .bit FPGA configuration file

fpga/usrp1/Makefile.am

@@ -0,0 +1,24 @@
+#
+# Copyright 2004,2005,2006 Free Software Foundation, Inc.
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+SUBDIRS = rbf
+
+include Makefile.extra

fpga/usrp1/Makefile.extra

@@ -0,0 +1,181 @@
+EXTRA_DIST =                                         \
+	gen_makefile_extra.py                        \
+	inband_lib/chan_fifo_reader.v                \
+	inband_lib/channel_demux.v                   \
+	inband_lib/channel_ram.v                     \
+	inband_lib/cmd_reader.v                      \
+	inband_lib/packet_builder.v                  \
+	inband_lib/register_io.v                     \
+	inband_lib/rx_buffer_inband.v                \
+	inband_lib/tx_buffer_inband.v                \
+	inband_lib/tx_packer.v                       \
+	inband_lib/usb_packet_fifo.v                 \
+	megacells/accum32.bsf                        \
+	megacells/accum32.cmp                        \
+	megacells/accum32.inc                        \
+	megacells/accum32.v                          \
+	megacells/accum32_bb.v                       \
+	megacells/accum32_inst.v                     \
+	megacells/add32.bsf                          \
+	megacells/add32.cmp                          \
+	megacells/add32.inc                          \
+	megacells/add32.v                            \
+	megacells/add32_bb.v                         \
+	megacells/add32_inst.v                       \
+	megacells/addsub16.bsf                       \
+	megacells/addsub16.cmp                       \
+	megacells/addsub16.inc                       \
+	megacells/addsub16.v                         \
+	megacells/addsub16_bb.v                      \
+	megacells/addsub16_inst.v                    \
+	megacells/bustri.bsf                         \
+	megacells/bustri.cmp                         \
+	megacells/bustri.inc                         \
+	megacells/bustri.v                           \
+	megacells/bustri_bb.v                        \
+	megacells/bustri_inst.v                      \
+	megacells/clk_doubler.v                      \
+	megacells/clk_doubler_bb.v                   \
+	megacells/dspclkpll.v                        \
+	megacells/dspclkpll_bb.v                     \
+	megacells/fifo_1kx16.bsf                     \
+	megacells/fifo_1kx16.cmp                     \
+	megacells/fifo_1kx16.inc                     \
+	megacells/fifo_1kx16.v                       \
+	megacells/fifo_1kx16_bb.v                    \
+	megacells/fifo_1kx16_inst.v                  \
+	megacells/fifo_2k.v                          \
+	megacells/fifo_2k_bb.v                       \
+	megacells/fifo_4k.v                          \
+	megacells/fifo_4k_18.v                       \
+	megacells/fifo_4k_bb.v                       \
+	megacells/fifo_4kx16_dc.bsf                  \
+	megacells/fifo_4kx16_dc.cmp                  \
+	megacells/fifo_4kx16_dc.inc                  \
+	megacells/fifo_4kx16_dc.v                    \
+	megacells/fifo_4kx16_dc_bb.v                 \
+	megacells/fifo_4kx16_dc_inst.v               \
+	megacells/mylpm_addsub.bsf                   \
+	megacells/mylpm_addsub.cmp                   \
+	megacells/mylpm_addsub.inc                   \
+	megacells/mylpm_addsub.v                     \
+	megacells/mylpm_addsub_bb.v                  \
+	megacells/mylpm_addsub_inst.v                \
+	megacells/pll.v                              \
+	megacells/pll_bb.v                           \
+	megacells/pll_inst.v                         \
+	megacells/sub32.bsf                          \
+	megacells/sub32.cmp                          \
+	megacells/sub32.inc                          \
+	megacells/sub32.v                            \
+	megacells/sub32_bb.v                         \
+	megacells/sub32_inst.v                       \
+	models/bustri.v                              \
+	models/fifo.v                                \
+	models/fifo_1c_1k.v                          \
+	models/fifo_1c_2k.v                          \
+	models/fifo_1c_4k.v                          \
+	models/fifo_1k.v                             \
+	models/fifo_2k.v                             \
+	models/fifo_4k.v                             \
+	models/fifo_4k_18.v                          \
+	models/pll.v                                 \
+	models/ssram.v                               \
+	sdr_lib/adc_interface.v                      \
+	sdr_lib/atr_delay.v                          \
+	sdr_lib/bidir_reg.v                          \
+	sdr_lib/cic_dec_shifter.v                    \
+	sdr_lib/cic_decim.v                          \
+	sdr_lib/cic_int_shifter.v                    \
+	sdr_lib/cic_interp.v                         \
+	sdr_lib/clk_divider.v                        \
+	sdr_lib/cordic.v                             \
+	sdr_lib/cordic_stage.v                       \
+	sdr_lib/ddc.v                                \
+	sdr_lib/dpram.v                              \
+	sdr_lib/duc.v                                \
+	sdr_lib/ext_fifo.v                           \
+	sdr_lib/gen_cordic_consts.py                 \
+	sdr_lib/gen_sync.v                           \
+	sdr_lib/hb/acc.v                             \
+	sdr_lib/hb/coeff_rom.v                       \
+	sdr_lib/hb/halfband_decim.v                  \
+	sdr_lib/hb/halfband_interp.v                 \
+	sdr_lib/hb/hbd_tb/test_hbd.v                 \
+	sdr_lib/hb/mac.v                             \
+	sdr_lib/hb/mult.v                            \
+	sdr_lib/hb/ram16_2port.v                     \
+	sdr_lib/hb/ram16_2sum.v                      \
+	sdr_lib/hb/ram32_2sum.v                      \
+	sdr_lib/io_pins.v                            \
+	sdr_lib/master_control.v                     \
+	sdr_lib/master_control_multi.v               \
+	sdr_lib/phase_acc.v                          \
+	sdr_lib/ram.v                                \
+	sdr_lib/ram16.v                              \
+	sdr_lib/ram32.v                              \
+	sdr_lib/ram64.v                              \
+	sdr_lib/rssi.v                               \
+	sdr_lib/rx_buffer.v                          \
+	sdr_lib/rx_chain.v                           \
+	sdr_lib/rx_chain_dual.v                      \
+	sdr_lib/rx_dcoffset.v                        \
+	sdr_lib/serial_io.v                          \
+	sdr_lib/setting_reg.v                        \
+	sdr_lib/setting_reg_masked.v                 \
+	sdr_lib/sign_extend.v                        \
+	sdr_lib/strobe_gen.v                         \
+	sdr_lib/tx_buffer.v                          \
+	sdr_lib/tx_chain.v                           \
+	sdr_lib/tx_chain_hb.v                        \
+	tb/cbus_tb.v                                 \
+	tb/cordic_tb.v                               \
+	tb/decim_tb.v                                \
+	tb/fullchip_tb.v                             \
+	tb/interp_tb.v                               \
+	tb/justinterp_tb.v                           \
+	tb/usrp_tasks.v                              \
+	toplevel/include/common_config_1rxhb_1tx.vh  \
+	toplevel/include/common_config_2rx_0tx.vh    \
+	toplevel/include/common_config_2rxhb_0tx.vh  \
+	toplevel/include/common_config_2rxhb_2tx.vh  \
+	toplevel/include/common_config_4rx_0tx.vh    \
+	toplevel/include/common_config_bottom.vh     \
+	toplevel/mrfm/biquad_2stage.v                \
+	toplevel/mrfm/biquad_6stage.v                \
+	toplevel/mrfm/mrfm.csf                       \
+	toplevel/mrfm/mrfm.esf                       \
+	toplevel/mrfm/mrfm.psf                       \
+	toplevel/mrfm/mrfm.py                        \
+	toplevel/mrfm/mrfm.qpf                       \
+	toplevel/mrfm/mrfm.qsf                       \
+	toplevel/mrfm/mrfm.v                         \
+	toplevel/mrfm/mrfm.vh                        \
+	toplevel/mrfm/mrfm_compensator.v             \
+	toplevel/mrfm/mrfm_fft.py                    \
+	toplevel/mrfm/mrfm_proc.v                    \
+	toplevel/mrfm/shifter.v                      \
+	toplevel/sizetest/sizetest.csf               \
+	toplevel/sizetest/sizetest.psf               \
+	toplevel/sizetest/sizetest.v                 \
+	toplevel/usrp_inband_usb/config.vh           \
+	toplevel/usrp_inband_usb/usrp_inband_usb.csf \
+	toplevel/usrp_inband_usb/usrp_inband_usb.esf \
+	toplevel/usrp_inband_usb/usrp_inband_usb.psf \
+	toplevel/usrp_inband_usb/usrp_inband_usb.qpf \
+	toplevel/usrp_inband_usb/usrp_inband_usb.qsf \
+	toplevel/usrp_inband_usb/usrp_inband_usb.v   \
+	toplevel/usrp_multi/config.vh                \
+	toplevel/usrp_multi/usrp_multi.csf           \
+	toplevel/usrp_multi/usrp_multi.esf           \
+	toplevel/usrp_multi/usrp_multi.psf           \
+	toplevel/usrp_multi/usrp_multi.qpf           \
+	toplevel/usrp_multi/usrp_multi.qsf           \
+	toplevel/usrp_multi/usrp_multi.v             \
+	toplevel/usrp_std/config.vh                  \
+	toplevel/usrp_std/usrp_std.csf               \
+	toplevel/usrp_std/usrp_std.esf               \
+	toplevel/usrp_std/usrp_std.psf               \
+	toplevel/usrp_std/usrp_std.qpf               \
+	toplevel/usrp_std/usrp_std.qsf               \
+	toplevel/usrp_std/usrp_std.v

fpga/usrp1/TODO

@@ -0,0 +1,23 @@
+
+
+Area Reduction
+==============
+Reduce one or both stages of dec/interp to max rate of 8 instead of 16
+Optimize CICs to minimize registers
+Reduce width of RX CORDIC
+Fix CORDIC wasted logic cells from bad synthesis
+Progressively narrow x,y,z on CORDIC
+16-bit wide FIFOs, split IQ/channels on other side (?)
+
+Enhancements
+============
+Halfband filter in Spartan 3
+Muxing of inputs
+Switch over to newfc
+RAM interface?
+
+Other
+=====
+Capture/Transmit straight samples (no DUC/DDC)
+
+

fpga/usrp1/common/fpga_regs_common.v

@@ -0,0 +1,117 @@
+//
+// This file is machine generated from ./fpga_regs_common.h
+// Do not edit by hand; your edits will be overwritten.
+//
+
+// This file defines registers common to all FPGA configurations.
+// Registers 0 to 31 are reserved for use in this file.
+
+
+// The FPGA needs to know the rate that samples are coming from and
+// going to the A/D's and D/A's.  div = 128e6 / sample_rate
+
+`define FR_TX_SAMPLE_RATE_DIV     7'd0
+`define FR_RX_SAMPLE_RATE_DIV     7'd1
+
+// 2 and 3 are defined in the ATR section
+
+`define FR_MASTER_CTRL            7'd4	// master enable and reset controls
+
+// i/o direction registers for pins that go to daughterboards.
+// Setting the bit makes it an output from the FPGA to the d'board.
+// top 16 is mask, low 16 is value
+
+`define FR_OE_0                   7'd5	// slot 0
+`define FR_OE_1                   7'd6
+`define FR_OE_2                   7'd7
+`define FR_OE_3                   7'd8
+
+// i/o registers for pins that go to daughterboards.
+// top 16 is a mask, low 16 is value
+
+`define FR_IO_0                   7'd9	// slot 0
+`define FR_IO_1                   7'd10
+`define FR_IO_2                   7'd11
+`define FR_IO_3                   7'd12
+
+`define FR_MODE                   7'd13
+
+
+// If the corresponding bit is set, internal FPGA debug circuitry
+// controls the i/o pins for the associated bank of daughterboard
+// i/o pins.  Typically used for debugging FPGA designs.
+
+`define FR_DEBUG_EN               7'd14
+
+
+// If the corresponding bit is set, enable the automatic DC
+// offset correction control loop.
+//
+// The 4 low bits are significant:
+//
+//   ADC0 = (1 << 0)
+//   ADC1 = (1 << 1)
+//   ADC2 = (1 << 2)
+//   ADC3 = (1 << 3)
+//
+// This control loop works if the attached daugherboard blocks DC.
+// Currently all daughterboards do block DC.  This includes:
+// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
+
+`define FR_DC_OFFSET_CL_EN        7'd15			// DC Offset Control Loop Enable
+
+
+// offset corrections for ADC's and DAC's (2's complement)
+
+`define FR_ADC_OFFSET_0           7'd16
+`define FR_ADC_OFFSET_1           7'd17
+`define FR_ADC_OFFSET_2           7'd18
+`define FR_ADC_OFFSET_3           7'd19
+
+
+// ------------------------------------------------------------------------
+// Automatic Transmit/Receive switching
+//
+// If automatic transmit/receive (ATR) switching is enabled in the
+// FR_ATR_CTL register, the presence or absence of data in the FPGA
+// transmit fifo selects between two sets of values for each of the 4
+// banks of daughterboard i/o pins.
+//
+// Each daughterboard slot has 3 16-bit registers associated with it:
+//   FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
+//
+// FR_ATR_MASK_{0,1,2,3}: 
+//
+//   These registers determine which of the daugherboard i/o pins are
+//   affected by ATR switching.  If a bit in the mask is set, the
+//   corresponding i/o bit is controlled by ATR, else it's output
+//   value comes from the normal i/o pin output register:
+//   FR_IO_{0,1,2,3}.
+//
+// FR_ATR_TXVAL_{0,1,2,3}:
+// FR_ATR_RXVAL_{0,1,2,3}:
+//
+//   If the Tx fifo contains data, then the bits from TXVAL that are
+//   selected by MASK are output.  Otherwise, the bits from RXVAL that
+//   are selected by MASK are output.
+                      
+`define FR_ATR_MASK_0             7'd20	// slot 0
+`define FR_ATR_TXVAL_0            7'd21
+`define FR_ATR_RXVAL_0            7'd22
+
+`define FR_ATR_MASK_1             7'd23	// slot 1
+`define FR_ATR_TXVAL_1            7'd24
+`define FR_ATR_RXVAL_1            7'd25
+
+`define FR_ATR_MASK_2             7'd26	// slot 2
+`define FR_ATR_TXVAL_2            7'd27
+`define FR_ATR_RXVAL_2            7'd28
+
+`define FR_ATR_MASK_3             7'd29	// slot 3
+`define FR_ATR_TXVAL_3            7'd30
+`define FR_ATR_RXVAL_3            7'd31
+
+// Clock ticks to delay rising and falling edge of T/R signal
+`define FR_ATR_TX_DELAY           7'd2
+`define FR_ATR_RX_DELAY           7'd3
+

fpga/usrp1/common/fpga_regs_standard.v

@@ -0,0 +1,256 @@
+//
+// This file is machine generated from ./fpga_regs_standard.h
+// Do not edit by hand; your edits will be overwritten.
+//
+
+// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
+// Registers 64 to 79 are available for custom FPGA builds.
+
+
+// DDC / DUC
+
+`define FR_INTERP_RATE            7'd32	// [1,1024]
+`define FR_DECIM_RATE             7'd33	// [1,256]
+
+// DDC center freq
+
+`define FR_RX_FREQ_0              7'd34
+`define FR_RX_FREQ_1              7'd35
+`define FR_RX_FREQ_2              7'd36
+`define FR_RX_FREQ_3              7'd37
+
+// See below for DDC Starting Phase
+
+// ------------------------------------------------------------------------
+//  configure FPGA Rx mux
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------+-------+-------+-------+-------+-+-----+
+// |      must be zero     | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
+// +-----------------------+-------+-------+-------+-------+-+-----+
+//
+// There are a maximum of 4 digital downconverters in the the FPGA.
+// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
+//
+// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
+//
+//   0 = DDC input is from ADC 0
+//   1 = DDC input is from ADC 1
+//   2 = DDC input is from ADC 2
+//   3 = DDC input is from ADC 3
+//
+// If Z == 1, all DDC Q inputs are set to zero
+// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
+//
+// NCH specifies the number of complex channels that are sent across
+// the USB.  The legal values are 1, 2 or 4, corresponding to 2, 4 or
+// 8 16-bit values.
+
+`define FR_RX_MUX                 7'd38
+
+// ------------------------------------------------------------------------
+//  configure FPGA Tx Mux.
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------+-------+-------+-------+-------+-+-----+
+// |                       | DAC3  | DAC2  | DAC1  |  DAC0 |0| NCH |
+// +-----------------------------------------------+-------+-+-----+
+//
+// NCH specifies the number of complex channels that are sent across
+// the USB.  The legal values are 1 or 2, corresponding to 2 or 4
+// 16-bit values.
+//
+// There are two interpolators with complex inputs and outputs.
+// There are four DACs.  (We use the DUC in each AD9862.)
+//
+// Each 4-bit DACx field specifies the source for the DAC and
+// whether or not that DAC is enabled.  Each subfield is coded
+// like this: 
+//
+//    3 2 1 0
+//   +-+-----+
+//   |E|  N  |
+//   +-+-----+
+//
+// Where E is set if the DAC is enabled, and N specifies which
+// interpolator output is connected to this DAC.
+//
+//  N   which interp output
+// ---  -------------------
+//  0   chan 0 I
+//  1   chan 0 Q
+//  2   chan 1 I
+//  3   chan 1 Q
+
+`define FR_TX_MUX                 7'd39
+
+// ------------------------------------------------------------------------
+// REFCLK control
+//
+// Control whether a reference clock is sent to the daughterboards,
+// and what frequency.  The refclk is sent on d'board i/o pin 0.
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------------+-+------------+
+// |             Reserved (Must be zero)           |E|   DIVISOR  |
+// +-----------------------------------------------+-+------------+
+
+//
+// Bit 7  -- 1 turns on refclk, 0 allows IO use
+// Bits 6:0 Divider value
+
+`define FR_TX_A_REFCLK            7'd40
+`define FR_RX_A_REFCLK            7'd41
+`define FR_TX_B_REFCLK            7'd42
+`define FR_RX_B_REFCLK            7'd43
+
+
+// ------------------------------------------------------------------------
+// DDC Starting Phase
+
+`define FR_RX_PHASE_0             7'd44
+`define FR_RX_PHASE_1             7'd45
+`define FR_RX_PHASE_2             7'd46
+`define FR_RX_PHASE_3             7'd47
+
+// ------------------------------------------------------------------------
+// Tx data format control register
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-------------------------------------------------------+-------+
+// |                    Reserved (Must be zero)            |  FMT  |
+// +-------------------------------------------------------+-------+
+//
+//  FMT values:
+
+`define FR_TX_FORMAT              7'd48
+
+// ------------------------------------------------------------------------
+// Rx data format control register
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------+-+-+---------+-------+
+// |          Reserved (Must be zero)        |B|Q|  WIDTH  | SHIFT |
+// +-----------------------------------------+-+-+---------+-------+
+//
+//  FMT values:
+
+`define FR_RX_FORMAT              7'd49
+
+
+// The valid combinations currently are:
+//
+//   B  Q  WIDTH  SHIFT
+//   0  1    16     0
+//   0  1     8     8
+
+
+// Possible future values of WIDTH = {4, 2, 1}
+// 12 takes a bit more work, since we need to know packet alignment.
+
+// ------------------------------------------------------------------------
+// FIXME register numbers 50 to 63 are available
+
+// ------------------------------------------------------------------------
+// Registers 64 to 95 are reserved for user custom FPGA builds.
+// The standard USRP software will not touch these.
+
+`define FR_USER_0                 7'd64
+`define FR_USER_1                 7'd65
+`define FR_USER_2                 7'd66
+`define FR_USER_3                 7'd67
+`define FR_USER_4                 7'd68
+`define FR_USER_5                 7'd69
+`define FR_USER_6                 7'd70
+`define FR_USER_7                 7'd71
+`define FR_USER_8                 7'd72
+`define FR_USER_9                 7'd73
+`define FR_USER_10                7'd74
+`define FR_USER_11                7'd75
+`define FR_USER_12                7'd76
+`define FR_USER_13                7'd77
+`define FR_USER_14                7'd78
+`define FR_USER_15                7'd79
+`define FR_USER_16                7'd80
+`define FR_USER_17                7'd81
+`define FR_USER_18                7'd82
+`define FR_USER_19                7'd83
+`define FR_USER_20                7'd84
+`define FR_USER_21                7'd85
+`define FR_USER_22                7'd86
+`define FR_USER_23                7'd87
+`define FR_USER_24                7'd88
+`define FR_USER_25                7'd89
+`define FR_USER_26                7'd90
+`define FR_USER_27                7'd91
+`define FR_USER_28                7'd92
+`define FR_USER_29                7'd93
+`define FR_USER_30                7'd94
+`define FR_USER_31                7'd95
+
+//Registers needed for multi usrp master/slave configuration
+//
+//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
+//
+`define FR_RX_MASTER_SLAVE        7'd64
+`define bitnoFR_RX_SYNC           0
+`define bitnoFR_RX_SYNC_MASTER    1
+`define bitnoFR_RX_SYNC_SLAVE     2
+
+
+//Caution The master settings will output values on the io lines.
+//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
+//If you set the slave bits then your usrp won't do anything if you don't connect a master.
+// Rx Master/slave control register
+//
+// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
+// This can be done with basic_rx boards or dbsrx boards
+//dbsrx: connect master-J25 to slave-J25
+//basic rx: connect J25 to slave-J25
+//CAUTION: pay attention to the lineup of your connector.
+//The red line (pin1) should be at the same side of the daughterboards on master and slave.
+//If you turnaround the cable on one end you will burn your usrp.
+
+//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
+//You can still link them but you must use only a 2pin or 1pin cable
+//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
+//You can use a cable like the ones found with the leds on the mainbord of a PC.
+//Make sure you don't twist the cable, otherwise you connect the sync output to ground.
+//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
+
+
+// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
+// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
+// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
+`define bitnoFR_RX_SYNC_INPUT_IOPIN 15
+`define bmFR_RX_SYNC_INPUT_IOPIN  (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
+//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
+`define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
+`define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
+// =======================================================================
+// READBACK Registers
+// =======================================================================
+
+`define FR_RB_IO_RX_A_IO_TX_A     7'd1	// read back a-side i/o pins
+`define FR_RB_IO_RX_B_IO_TX_B     7'd2	// read back b-side i/o pins
+
+// ------------------------------------------------------------------------
+// FPGA Capability register
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------------+-+-----+-+-----+
+// |                    Reserved (Must be zero)    |T|NDUC |R|NDDC |
+// +-----------------------------------------------+-+-----+-+-----+
+//
+// Bottom 4-bits are Rx capabilities
+// Next   4-bits are Tx capabilities
+
+`define FR_RB_CAPS                7'd3
+
+

fpga/usrp1/gen_makefile_extra.py

@@ -0,0 +1,67 @@
+#!/usr/bin/env python
+#
+# Copyright 2006 Free Software Foundation, Inc.
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+"""
+Generate Makefile.extra
+"""
+
+import sys
+import os.path
+
+extensions_we_like = (
+    '.v', '.vh',
+    '.csf', '.esf', '.psf', '.qpf', '.qsf', 
+    '.inc', '.cmp', '.bsf',
+    '.py')
+
+def visit(keepers, dirname, names):
+    if 'rbf' in names:
+        names.remove('rbf')
+    if 'CVS' in names:
+        names.remove('CVS')
+    
+    if dirname == '.':
+        dirname = ''
+    if dirname.startswith('./'):
+        dirname = dirname[2:]
+    
+    for n in names:
+        base, ext = os.path.splitext(n)
+        if ext in extensions_we_like:
+            keepers.append(os.path.join(dirname, n))
+
+def generate(f):
+    keepers = []
+    os.path.walk('.', visit, keepers)
+    keepers.sort()
+    write_keepers(keepers, f)
+
+def write_keepers(files, outf):
+    m = reduce(max, map(len, files), 0)
+    e = 'EXTRA_DIST ='
+    outf.write('%s%s \\\n' % (e, (m-len(e)+8) * ' '))
+    for f in files[:-1]:
+        outf.write('\t%s%s \\\n' % (f, (m-len(f)) * ' '))
+    outf.write('\t%s\n' % (files[-1],))
+
+if __name__ == '__main__':
+    generate(open('Makefile.extra','w'))

fpga/usrp1/inband_lib/chan_fifo_reader.v

@@ -0,0 +1,219 @@
+module chan_fifo_reader 
+   (reset, tx_clock, tx_strobe, timestamp_clock, samples_format,
+    fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
+    underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
+
+   input   wire                     reset ;
+   input   wire                     tx_clock ;
+   input   wire                     tx_strobe ; //signal to output tx_i and tx_q
+   input   wire              [31:0] timestamp_clock ; //current time
+   input   wire               [3:0] samples_format ;// not useful at this point
+   input   wire              [31:0] fifodata ; //the data input
+   input   wire                     pkt_waiting ; //signal the next packet is ready
+   output  reg                      rdreq ; //actually an ack to the current fifodata
+   output  reg                      skip ; //finish reading current packet
+   output  reg               [15:0] tx_q ; //top 16 bit output of fifodata
+   output  reg               [15:0] tx_i ; //bottom 16 bit output of fifodata
+   output  reg                      underrun ; 
+   output  reg                      tx_empty ; //cause 0 to be the output
+   input   wire		     [31:0] rssi;
+   input   wire		     [31:0] threshhold;
+   input   wire		     [31:0] rssi_wait;
+
+   output wire [14:0] debug;
+   assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
+   
+   //Samples format
+   // 16 bits interleaved complex samples
+   `define QI16                     4'b0
+    
+   // States
+   parameter IDLE           =     3'd0;    
+   parameter HEADER         =     3'd1;
+   parameter TIMESTAMP      =     3'd2;
+   parameter WAIT           =     3'd3;
+   parameter WAITSTROBE     =     3'd4;
+   parameter SEND           =     3'd5;
+
+   // Header format
+   `define PAYLOAD                  8:2
+   `define ENDOFBURST               27
+   `define STARTOFBURST             28
+   `define RSSI_FLAG                26
+	
+
+   /* State registers */
+   reg                        [2:0] reader_state;
+   /* Local registers */  
+   reg                        [6:0] payload_len;
+   reg                        [6:0] read_len;
+   reg                       [31:0] timestamp;
+   reg                              burst;
+   reg                              trash;
+   reg                              rssi_flag;
+   reg			     [31:0] time_wait;
+   
+   always @(posedge tx_clock)
+     begin
+       if (reset) 
+         begin
+           reader_state <= IDLE;
+           rdreq <= 0;
+           skip <= 0;
+           underrun <= 0;
+           burst <= 0;
+           tx_empty <= 1;
+           tx_q <= 0;
+           tx_i <= 0;
+           trash <= 0;
+           rssi_flag <= 0;
+           time_wait <= 0;
+         end
+       else 
+         begin
+           case (reader_state)
+             IDLE:
+               begin
+               /*
+		* reset all the variables and wait for a tx_strobe
+		* it is assumed that the ram connected to this fifo_reader 
+		* is a short hand fifo meaning that the header to the next packet
+		* is already available to this fifo_reader when pkt_waiting is on
+		*/
+                 skip <=0;
+                 time_wait <= 0;
+                 if (pkt_waiting == 1)
+                   begin
+                     reader_state <= HEADER;
+                     rdreq <= 1;
+                     underrun <= 0;
+                   end
+                 if (burst == 1 && pkt_waiting == 0)
+                     underrun <= 1;
+                 if (tx_strobe == 1)
+                     tx_empty <= 1 ;
+               end
+
+               /* Process header */
+               HEADER:
+                 begin
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                   
+                   rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
+                   //Check Start/End burst flag
+                   if  (fifodata[`STARTOFBURST] == 1 
+                       && fifodata[`ENDOFBURST] == 1)
+                       burst <= 0;
+                   else if (fifodata[`STARTOFBURST] == 1)
+                       burst <= 1;
+                   else if (fifodata[`ENDOFBURST] == 1)
+                       burst <= 0;
+
+                   if (trash == 1 && fifodata[`STARTOFBURST] == 0)
+                     begin
+                       skip <= 1;
+                       reader_state <= IDLE;
+                       rdreq <= 0;
+                     end 
+                   else
+                     begin   
+                       payload_len <= fifodata[`PAYLOAD] ;
+                       read_len <= 0;
+                       rdreq <= 1;
+                       reader_state <= TIMESTAMP;
+                     end
+                 end
+
+               TIMESTAMP: 
+                 begin
+                   timestamp <= fifodata;
+                   reader_state <= WAIT;
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                   rdreq <= 0;
+                 end
+				
+               // Decide if we wait, send or discard samples
+               WAIT: 
+                 begin
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                    
+                   time_wait <= time_wait + 32'd1;
+                   // Outdated
+                   if ((timestamp < timestamp_clock) ||
+                      (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
+                     begin
+                       trash <= 1;
+                       reader_state <= IDLE;
+                       skip <= 1;
+                     end  
+                   // Let's send it					
+                   else if (timestamp == timestamp_clock 
+                             || timestamp == 32'hFFFFFFFF)
+                     begin
+                       if (rssi <= threshhold || rssi_flag == 0)
+                         begin
+                           trash <= 0;
+                           reader_state <= WAITSTROBE; 
+                         end
+                       else
+                         reader_state <= WAIT;
+                     end
+                   else
+                       reader_state <= WAIT;
+                 end
+                 
+               // Wait for the transmit chain to be ready
+               WAITSTROBE:
+                 begin
+                   // If end of payload...
+                   if (read_len == payload_len)
+                     begin
+                       reader_state <= IDLE;
+                       skip <= 1;
+                       if (tx_strobe == 1)
+                           tx_empty <= 1 ;
+                     end  
+                   else if (tx_strobe == 1)
+                     begin
+                       reader_state <= SEND;
+                       rdreq <= 1;
+                     end
+                 end
+               
+               // Send the samples to the tx_chain
+               SEND:
+                 begin
+                   reader_state <= WAITSTROBE; 
+                   read_len <= read_len + 7'd1;
+                   tx_empty <= 0;
+                   rdreq <= 0;
+                   
+                   case(samples_format)
+                       `QI16:
+                        begin
+                            tx_i <= fifodata[15:0];
+                            tx_q <= fifodata[31:16];
+                        end
+                        
+                        // Assume 16 bits complex samples by default
+                        default:
+                        begin
+                            tx_i <= fifodata[15:0];
+                            tx_q <= fifodata[31:16];
+                        end 
+                   endcase
+                 end
+               
+               default:
+                 begin
+                   //error handling
+                   reader_state <= IDLE;
+                 end
+           endcase
+       end
+   end
+ 
+endmodule

fpga/usrp1/inband_lib/channel_demux.v

@@ -0,0 +1,78 @@
+module channel_demux
+ #(parameter NUM_CHAN = 2) (     //usb Side
+   input [31:0]usbdata_final,
+   input WR_final, 
+   // TX Side
+   input reset,
+   input txclk,
+   output reg [NUM_CHAN:0] WR_channel,
+   output reg [31:0] ram_data,
+   output reg [NUM_CHAN:0] WR_done_channel );
+   /* Parse header and forward to ram */
+	
+    reg [2:0]reader_state;
+    reg [4:0]channel ;
+    reg [6:0]read_length ;
+	
+	 // States
+    parameter IDLE      =    3'd0;
+    parameter HEADER    =    3'd1;
+    parameter WAIT      =    3'd2;
+    parameter FORWARD   =    3'd3;
+	
+	`define CHANNEL 20:16
+	`define PKT_SIZE 127
+	wire [4:0] true_channel;
+	assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
+							NUM_CHAN : (usbdata_final[`CHANNEL]);
+	
+	always @(posedge txclk)
+	  begin
+	    if (reset)
+	      begin
+	       reader_state <= IDLE;
+	       WR_channel <= 0;
+	       WR_done_channel <= 0;
+	      end
+	      else
+	        case (reader_state)
+	        IDLE: begin
+	            if (WR_final)
+	                reader_state <= HEADER; 
+	            end
+	       
+            // Store channel and forware header
+	        HEADER: begin
+	            channel <= true_channel;
+	            WR_channel[true_channel] <= 1;
+	            ram_data <= usbdata_final;
+				read_length <= 7'd0 ;
+				
+                reader_state <= WAIT;
+	        end
+	       
+	        WAIT: begin
+	           WR_channel[channel] <= 0;
+	
+			   if (read_length == `PKT_SIZE)
+	               reader_state <= IDLE;
+	           else if (WR_final)
+	               reader_state <= FORWARD;
+	        end
+	       
+	        FORWARD: begin
+	           WR_channel[channel] <= 1;
+	           ram_data <= usbdata_final;
+	           read_length <= read_length + 7'd1;
+	           
+	           reader_state <= WAIT;
+	        end
+	
+			default:
+               begin
+					//error handling
+                   reader_state <= IDLE;
+               end
+	       endcase
+	   end
+endmodule

fpga/usrp1/inband_lib/channel_ram.v

@@ -0,0 +1,107 @@
+module channel_ram 
+   ( // System
+     input txclk, input reset,
+     // USB side
+     input [31:0] datain, input WR, input WR_done, output have_space,
+     // Reader side 
+     output [31:0] dataout, input RD, input RD_done, output packet_waiting);
+	
+   reg [6:0] wr_addr, rd_addr;
+   reg [1:0] which_ram_wr, which_ram_rd;
+   reg [2:0] nb_packets;
+	
+   reg [31:0] ram0 [0:127];
+   reg [31:0] ram1 [0:127];
+   reg [31:0] ram2 [0:127];
+   reg [31:0] ram3 [0:127];
+	
+   reg [31:0] dataout0;
+   reg [31:0] dataout1;
+   reg [31:0] dataout2;
+   reg [31:0] dataout3;
+	
+   wire wr_done_int;
+   wire rd_done_int;
+   wire [6:0] rd_addr_final;
+   wire [1:0] which_ram_rd_final;
+	
+   // USB side
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
+			
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
+
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
+
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
+
+   assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
+   
+   always @(posedge txclk)
+       if(reset)
+           wr_addr <= 0;
+       else if (WR_done)
+           wr_addr <= 0;
+       else if (WR) 
+           wr_addr <= wr_addr + 7'd1;
+		
+   always @(posedge txclk)
+      if(reset)
+          which_ram_wr <= 0;
+      else if (wr_done_int) 
+          which_ram_wr <= which_ram_wr + 2'd1;
+	
+   assign have_space = (nb_packets < 3'd3);
+		
+   // Reader side
+   // short hand fifo
+   // rd_addr_final is what rd_addr is going to be next clock cycle
+   // which_ram_rd_final is what which_ram_rd is going to be next clock cycle
+   always @(posedge txclk)  dataout0 <= ram0[rd_addr_final];
+   always @(posedge txclk)  dataout1 <= ram1[rd_addr_final];
+   always @(posedge txclk)  dataout2 <= ram2[rd_addr_final];
+   always @(posedge txclk)  dataout3 <= ram3[rd_addr_final];
+	
+   assign dataout = (which_ram_rd_final[1]) ? 
+                    (which_ram_rd_final[0] ? dataout3 : dataout2) :
+                    (which_ram_rd_final[0] ? dataout1 : dataout0);
+
+   //RD_done is the only way to signal the end of one packet
+   assign rd_done_int = RD_done;   
+
+   always @(posedge txclk)
+       if (reset)
+           rd_addr <= 0;
+       else if (RD_done)
+           rd_addr <= 0;
+       else if (RD) 
+           rd_addr <= rd_addr + 7'd1;
+			
+   assign rd_addr_final = (reset|RD_done) ? (6'd0) : 
+	                  ((RD)?(rd_addr+7'd1):rd_addr); 
+	
+   always @(posedge txclk)
+       if (reset)
+           which_ram_rd <= 0;
+       else if (rd_done_int)
+           which_ram_rd <= which_ram_rd + 2'd1;
+
+   assign which_ram_rd_final = (reset) ? (2'd0):
+	                       ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
+	                        
+   //packet_waiting is set to zero if rd_done_int is high
+   //because there is no guarantee that nb_packets will be pos.
+
+   assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
+   always @(posedge txclk)
+       if (reset)
+           nb_packets <= 0;
+       else if (wr_done_int & ~rd_done_int)
+           nb_packets <= nb_packets + 3'd1;
+       else if (rd_done_int & ~wr_done_int)
+           nb_packets <= nb_packets - 3'd1;
+			
+endmodule

fpga/usrp1/inband_lib/cmd_reader.v

@@ -0,0 +1,305 @@
+module cmd_reader
+   (//System
+    input reset, input txclk, input [31:0] timestamp_clock,
+    //FX2 Side
+    output reg skip, output reg rdreq, 
+    input [31:0] fifodata, input pkt_waiting,
+    //Rx side
+    input rx_WR_enabled, output reg [15:0] rx_databus,
+    output reg rx_WR, output reg rx_WR_done,
+    //register io
+    input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
+    output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
+    output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
+	
+   // States
+   parameter IDLE                       =   4'd0;
+   parameter HEADER                     =   4'd1;
+   parameter TIMESTAMP                  =   4'd2;
+   parameter WAIT          	        =   4'd3;
+   parameter TEST                       =   4'd4;
+   parameter SEND                       =   4'd5;
+   parameter PING                       =   4'd6;
+   parameter WRITE_REG                  =   4'd7;
+   parameter WRITE_REG_MASKED           =   4'd8;
+   parameter READ_REG                   =   4'd9;
+   parameter DELAY                      =   4'd14;		
+
+   `define OP_PING_FIXED                    8'd0
+   `define OP_PING_FIXED_REPLY              8'd1
+   `define OP_WRITE_REG	                    8'd2
+   `define OP_WRITE_REG_MASKED              8'd3
+   `define OP_READ_REG                      8'd4
+   `define OP_READ_REG_REPLY                8'd5
+   `define OP_DELAY                         8'd12
+	
+   reg [6:0]   payload;
+   reg [6:0]   payload_read;
+   reg [3:0]   state;
+   reg [15:0]  high;
+   reg [15:0]  low;
+   reg         pending;
+   reg [31:0]  value0;
+   reg [31:0]  value1;
+   reg [31:0]  value2;
+   reg [1:0]   lines_in;
+   reg [1:0]   lines_out;
+   reg [1:0]   lines_out_total;
+	
+   `define JITTER                           5
+   `define OP_CODE                          31:24
+   `define PAYLOAD                          8:2
+	
+   wire [7:0] ops;
+   assign ops = value0[`OP_CODE];
+   assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
+	
+   always @(posedge txclk)
+       if (reset)
+         begin
+           pending <= 0;
+           state <= IDLE;
+           skip <= 0;
+           rdreq <= 0;
+           rx_WR <= 0;
+           reg_io_enable <= 0;
+           reg_data_in <= 0;
+           reg_addr <= 0;
+           stop <= 0;
+          end
+        else case (state)
+          IDLE : 
+            begin
+              payload_read <= 0;
+              skip <= 0;
+              lines_in <= 0;
+              if(pkt_waiting)
+                begin
+                  state <= HEADER;
+                  rdreq <= 1;
+                end
+             end
+          
+          HEADER : 
+            begin
+              payload <= fifodata[`PAYLOAD];
+              state <= TIMESTAMP;
+            end
+          
+          TIMESTAMP : 
+            begin
+              value0 <= fifodata;
+              state <= WAIT;
+              rdreq <= 0;
+            end
+			
+          WAIT : 
+            begin
+              // Let's send it
+              if ((value0 <= timestamp_clock + `JITTER 
+                 && value0 > timestamp_clock)
+                 || value0 == 32'hFFFFFFFF)
+                  state <= TEST;
+              // Wait a little bit more
+              else if (value0 > timestamp_clock + `JITTER)
+                  state <= WAIT; 
+              // Outdated
+              else if (value0 < timestamp_clock)
+                begin
+                  state <= IDLE;
+                  skip <= 1;
+                end
+            end
+			
+          TEST : 
+            begin
+              reg_io_enable <= 0;
+              rx_WR <= 0;
+              rx_WR_done <= 1;
+              stop <= 0;
+              if (payload_read == payload)
+                begin
+                  skip <= 1;
+                  state <= IDLE;
+                  rdreq <= 0;
+                end
+              else
+                begin
+                  value0 <= fifodata;
+                  lines_in <= 2'd1;
+                  rdreq <= 1;
+                  payload_read <= payload_read + 7'd1;
+                  lines_out <= 0;
+                  case (fifodata[`OP_CODE])
+                    `OP_PING_FIXED: 
+                      begin
+                        state <= PING;
+                      end
+                    `OP_WRITE_REG: 
+                      begin
+                        state <= WRITE_REG;
+                        pending <= 1;
+                      end
+                    `OP_WRITE_REG_MASKED: 
+                      begin
+                        state <= WRITE_REG_MASKED;
+                        pending <= 1;
+                      end
+                    `OP_READ_REG: 
+                      begin
+                        state <= READ_REG;
+                      end
+                    `OP_DELAY: 
+                      begin
+                        state <= DELAY;
+                      end
+                    default: 
+                      begin
+                      //error, skip this packet
+                        skip <= 1;
+                        state <= IDLE;
+                      end
+                  endcase
+                end
+              end
+			
+            SEND: 
+              begin
+                rdreq <= 0;
+                rx_WR_done <= 0;
+                if (pending)
+                  begin
+                    rx_WR <= 1;
+                    rx_databus <= high;
+                    pending <= 0;
+                    if (lines_out == lines_out_total)
+                        state <= TEST;
+                    else case (ops)
+                        `OP_READ_REG: 
+                          begin
+                            state <= READ_REG;
+                          end
+                         default: 
+                           begin
+                             state <= TEST;
+                           end
+                    endcase
+                  end
+                else
+                  begin
+                    if (rx_WR_enabled)
+                      begin
+                        rx_WR <= 1;
+                        rx_databus <= low;
+                        pending <= 1;
+                        lines_out <= lines_out + 2'd1;
+                      end
+                    else
+                        rx_WR <= 0;
+                  end
+                end
+			
+            PING: 
+              begin
+                rx_WR <= 0;
+                rdreq <= 0;
+                rx_WR_done <= 0;
+                lines_out_total <= 2'd1;
+                pending <= 0; 
+                state <= SEND;
+                high <= {`OP_PING_FIXED_REPLY, 8'd2};
+                low <= value0[15:0];	
+              end
+			
+            READ_REG: 
+              begin
+                rx_WR <= 0;
+                rx_WR_done <= 0;
+                rdreq <= 0;
+                lines_out_total <= 2'd2;
+                pending <= 0;
+                state <= SEND;
+                if (lines_out == 0)
+                  begin
+                    high <= {`OP_READ_REG_REPLY, 8'd6};
+                    low <= value0[15:0];
+                    reg_io_enable <= 2'd3;
+                    reg_addr <= value0[6:0];
+                  end
+                else
+                  begin		
+                    high <= reg_data_out[31:16];
+                    low <= reg_data_out[15:0];
+                  end
+             end    
+			
+            WRITE_REG: 
+              begin
+                rx_WR <= 0;
+                if (pending)
+                    pending <= 0;
+                else
+                  begin
+                    if (lines_in == 2'd1)
+                      begin
+                        payload_read <= payload_read + 7'd1;
+                        lines_in <= lines_in + 2'd1;
+                        value1 <= fifodata;
+                        rdreq <= 0;
+                      end
+                    else
+                      begin
+                        reg_io_enable <= 2'd2;
+                        reg_data_in <= value1;
+                        reg_addr <= value0[6:0];
+                        state <= TEST;
+                      end
+                  end
+              end
+			
+            WRITE_REG_MASKED: 
+              begin
+                rx_WR <= 0;
+                if (pending)
+                    pending <= 0;
+                else
+                  begin
+                    if (lines_in == 2'd1)
+                      begin
+                        rdreq <= 1;
+                        payload_read <= payload_read + 7'd1;
+                        lines_in <= lines_in + 2'd1;
+                        value1 <= fifodata;
+                      end
+                    else if (lines_in == 2'd2)
+                      begin
+                        rdreq <= 0;
+                        payload_read <= payload_read + 7'd1;
+                        lines_in <= lines_in + 2'd1;
+                        value2 <= fifodata;
+                      end
+                    else
+                      begin
+                        reg_io_enable <= 2'd2;
+                        reg_data_in <= (value1 & value2);
+                        reg_addr <= value0[6:0];
+                        state <= TEST;
+                      end
+                  end
+              end
+			
+            DELAY : 
+              begin
+                rdreq <= 0;
+                stop <= 1;
+                stop_time <= value0[15:0];
+                state <= TEST;
+              end
+			
+            default : 
+              begin
+                //error state handling
+                state <= IDLE;
+              end
+        endcase
+endmodule

fpga/usrp1/inband_lib/packet_builder.v

@@ -0,0 +1,152 @@
+module packet_builder #(parameter NUM_CHAN = 2)(
+    // System
+    input rxclk,
+    input reset,
+	 input [31:0] timestamp_clock,
+	 input [3:0] channels,
+    // ADC side
+    input [15:0]chan_fifodata,
+    input [NUM_CHAN:0]chan_empty,
+    input [9:0]chan_usedw,
+    output reg [3:0]rd_select,
+    output reg chan_rdreq,
+    // FX2 side
+    output reg WR,
+    output reg [15:0]fifodata,
+    input have_space, 
+    input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
+    input wire [31:0]rssi_3, output wire [7:0] debugbus,
+    input [NUM_CHAN:0] underrun);
+    
+    
+    // States
+    `define IDLE                     3'd0
+    `define HEADER1                  3'd1
+    `define HEADER2                  3'd2
+    `define TIMESTAMP                3'd3
+    `define FORWARD                  3'd4
+	
+    `define MAXPAYLOAD 504
+    
+    `define PAYLOAD_LEN 8:0
+    `define TAG 12:9
+    `define MBZ 15:13
+    
+    `define CHAN 4:0
+    `define RSSI 10:5
+    `define BURST 12:11
+    `define DROPPED 13
+    `define UNDERRUN 14
+    `define OVERRUN 15
+    
+    reg [NUM_CHAN:0] overrun;
+    reg [2:0] state;
+    reg [8:0] read_length;
+    reg [8:0] payload_len;
+    reg timestamp_complete;
+    reg [3:0] check_next;
+	
+    wire [31:0] true_rssi;
+    wire [4:0] true_channel;
+    wire ready_to_send;
+
+    assign debugbus = {chan_empty[0], rd_select[0], have_space, 
+                       (chan_usedw >= 10'd504), (chan_usedw ==0),  
+                       ready_to_send, state[1:0]};
+
+    assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+							((rd_select[0]) ? rssi_1:rssi_0);
+    assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
+    assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) || 
+                           ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
+		
+    always @(posedge rxclk)
+    begin
+        if (reset)
+          begin
+            overrun <= 0;
+            WR <= 0;
+            rd_select <= 0;
+            chan_rdreq <= 0;
+            timestamp_complete <= 0;
+            check_next <= 0;
+            state <= `IDLE;
+          end
+        else case (state)
+            `IDLE: begin
+		chan_rdreq <= #1 0;
+		//check if the channel is full
+		if(~chan_empty[check_next])
+		  begin
+                    if (have_space)
+                      begin
+                        //transmit if the usb buffer have space
+                       //check if we should send
+                       if (ready_to_send)
+                           state <= #1 `HEADER1;
+						    
+                       overrun[check_next] <= 0;
+                      end
+                  else
+                    begin
+                      state <= #1 `IDLE;
+                      overrun[check_next] <= 1;
+                    end
+                  rd_select <= #1 check_next;
+                end
+                check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
+            end
+            
+            `HEADER1: begin
+                fifodata[`PAYLOAD_LEN] <= #1 9'd504;
+                payload_len <= #1 9'd504;
+                fifodata[`TAG] <= #1 0;
+                fifodata[`MBZ] <= #1 0;
+                WR <= #1 1;
+                
+                state <= #1 `HEADER2;
+                read_length <= #1 0;
+            end
+            
+            `HEADER2: begin
+                fifodata[`CHAN] <= #1 true_channel;
+                fifodata[`RSSI] <= #1 true_rssi[5:0];
+                fifodata[`BURST] <= #1 0;
+                fifodata[`DROPPED] <= #1 0;
+                fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
+                fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
+                state <= #1 `TIMESTAMP;
+            end
+            
+            `TIMESTAMP: begin
+                fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]);
+                timestamp_complete <= #1 ~timestamp_complete;
+                
+                if (~timestamp_complete)
+                    chan_rdreq <= #1 1;
+                
+                state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
+            end
+            
+            `FORWARD: begin
+                read_length <= #1 read_length + 9'd2;
+                fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
+                
+                if (read_length >= `MAXPAYLOAD)
+                  begin
+                    WR <= #1 0;
+                    state <= #1 `IDLE;
+					chan_rdreq <= #1 0;
+                  end
+                else if (read_length == payload_len - 4)
+                    chan_rdreq <= #1 0;
+            end
+            
+            default: begin
+				//handling error state
+                state <= `IDLE;
+            end
+            endcase
+    end
+endmodule
+

fpga/usrp1/inband_lib/register_io.v

@@ -0,0 +1,82 @@
+module register_io
+	(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
+	 rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3, 
+     debug_en, misc, txmux);   
+	
+	input clk;
+	input reset;
+	input wire [1:0] enable;
+	input wire [6:0] addr; 
+	input wire [31:0] datain;
+	output reg [31:0] dataout;
+	output wire [15:0] debugbus;
+	output reg [6:0] addr_wr;
+	output reg [31:0] data_wr;
+	output wire strobe_wr; 
+	input wire [31:0] rssi_0;
+	input wire [31:0] rssi_1;
+	input wire [31:0] rssi_2; 
+	input wire [31:0] rssi_3; 
+	output wire [31:0] threshhold;
+	output wire [31:0] rssi_wait;
+	input wire [15:0] reg_0;
+	input wire [15:0] reg_1; 
+	input wire [15:0] reg_2; 
+	input wire [15:0] reg_3;
+	input wire [3:0]  debug_en;
+	input wire [7:0]  misc;
+	input wire [31:0] txmux;
+	
+	reg strobe;
+	wire [31:0] out[2:1];
+	assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
+	assign threshhold = out[1];
+	assign rssi_wait = out[2];
+	assign strobe_wr = strobe;
+	
+	always @(*)
+        if (reset | ~enable[1])
+           begin
+             strobe <= 0;
+		     dataout <= 0;
+		   end
+		else
+		   begin
+	         if (enable[0])
+	           begin
+	             //read
+				if (addr <= 7'd52 && addr > 7'd50)
+					dataout <= out[addr-7'd50];
+				else
+					dataout <= 32'hFFFFFFFF; 	
+	            strobe <= 0;
+              end
+             else
+               begin
+                 //write
+	             dataout <= dataout;
+                 strobe <= 1;
+				 data_wr <= datain;
+				 addr_wr <= addr;
+               end
+          end
+
+//register declarations
+    /*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/
+    setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
+    setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
+    /*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
+    setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
+    setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
+    setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
+    setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/
+
+endmodule	

fpga/usrp1/inband_lib/rx_buffer_inband.v

@@ -0,0 +1,209 @@
+//`include "../common/fpga_regs_common.v"
+//`include "../common/fpga_regs_standard.v"
+module rx_buffer_inband
+  ( input usbclk,
+    input bus_reset,
+    input reset,  // DSP side reset (used here), do not reset registers
+    input reset_regs, //Only reset registers
+    output [15:0] usbdata,
+    input RD,
+    output wire have_pkt_rdy,
+    output reg rx_overrun,
+    input wire [3:0] channels,
+    input wire [15:0] ch_0,
+    input wire [15:0] ch_1,
+    input wire [15:0] ch_2,
+    input wire [15:0] ch_3,
+    input wire [15:0] ch_4,
+    input wire [15:0] ch_5,
+    input wire [15:0] ch_6,
+    input wire [15:0] ch_7,
+    input rxclk,
+    input rxstrobe,
+    input clear_status,
+    input [6:0] serial_addr, 
+    input [31:0] serial_data, 
+    input serial_strobe,
+    output wire [15:0] debugbus,
+	
+    //Connection with tx_inband
+    input rx_WR,
+    input [15:0] rx_databus,
+    input rx_WR_done,
+    output reg rx_WR_enabled,
+    //signal strength
+    input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+    input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+    input wire [1:0] tx_underrun
+    );
+    
+    parameter NUM_CHAN = 1;
+    genvar i ;
+    
+    // FX2 Bug Fix
+    reg [8:0] read_count;
+    always @(negedge usbclk)
+        if(bus_reset)
+            read_count <= #1 9'd0;
+        else if(RD & ~read_count[8])
+            read_count <= #1 read_count + 9'd1;
+        else
+            read_count <= #1 RD ? read_count : 9'b0;
+       
+	// Time counter
+	reg [31:0] timestamp_clock;
+	always @(posedge rxclk)
+		if (reset)
+			timestamp_clock <= 0;
+		else
+			timestamp_clock <= timestamp_clock + 1;
+     
+  // USB side fifo
+  wire [11:0] rdusedw;
+  wire [11:0] wrusedw;
+  wire [15:0] fifodata;
+  wire [15:0] fifodata_il[0:NUM_CHAN];
+  wire WR;
+  wire have_space;
+  reg sel;
+  reg wr;
+
+  always@(posedge rxclk)
+    begin
+      if(reset)
+        begin
+          sel<=1;
+          wr<=0;
+        end
+      else if(rxstrobe)
+        begin
+          sel<=0;
+          wr<=1;
+        end
+      else if(wr&~sel)
+          sel<=1;
+      else if(wr&sel)
+          wr<=0;
+      else
+          wr<=0;
+    end
+
+  assign fifodata_il[0] = (sel)?ch_1:ch_0;
+  assign fifodata_il[1] = (sel)?ch_3:ch_2;
+
+  fifo_4kx16_dc	rx_usb_fifo (
+    .aclr ( reset ),
+    .data ( fifodata ),
+    .rdclk ( ~usbclk ),
+    .rdreq ( RD & ~read_count[8] ),
+    .wrclk ( rxclk ),
+    .wrreq ( WR ),
+    .q ( usbdata ),
+    .rdempty (  ),
+    .rdusedw ( rdusedw ),
+    .wrfull (  ),
+    .wrusedw ( wrusedw ) );
+    
+  assign have_pkt_rdy = (rdusedw >= 12'd256);
+  assign have_space = (wrusedw < 12'd760);
+	 
+  // Rx side fifos
+  // These are of size [NUM_CHAN:0] because the extra channel is used for the
+  // RX command channel.  If there were no command channel, they would be
+  // NUM_CHAN-1.
+  wire chan_rdreq;
+  wire [15:0] chan_fifodata;
+  wire [9:0] chan_usedw;
+  wire [NUM_CHAN:0] chan_empty;
+  wire [3:0] rd_select;
+  wire [NUM_CHAN:0] rx_full;
+	 
+  packet_builder #(NUM_CHAN) rx_pkt_builer (
+    .rxclk ( rxclk ),
+    .reset ( reset ),
+    .timestamp_clock ( timestamp_clock ),
+    .channels ( NUM_CHAN ),
+    .chan_rdreq ( chan_rdreq ),
+    .chan_fifodata ( chan_fifodata ),
+    .chan_empty ( chan_empty ),
+    .rd_select ( rd_select ),
+    .chan_usedw ( chan_usedw ),
+    .WR ( WR ),
+    .fifodata ( fifodata ),
+    .have_space ( have_space ),
+      .rssi_0(rssi_0), .rssi_1(rssi_1),
+      .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+      .underrun(tx_underrun));
+	 
+  // Detect overrun
+  always @(posedge rxclk)
+    if(reset)
+      rx_overrun <= 1'b0;
+    else if(rx_full[0])
+      rx_overrun <= 1'b1;
+    else if(clear_status)
+      rx_overrun <= 1'b0;
+
+		
+  // FIXME: what is the purpose of these two lines?
+  wire [15:0]ch[NUM_CHAN:0];
+  assign ch[0] = ch_0;
+	
+  wire cmd_empty;
+	
+  always @(posedge rxclk)
+    if(reset)
+      rx_WR_enabled <= 1;
+    else if(cmd_empty)
+      rx_WR_enabled <= 1;
+    else if(rx_WR_done)
+      rx_WR_enabled <= 0;
+
+
+  // Of Size 0:NUM_CHAN due to extra command channel.
+  wire [15:0] dataout [0:NUM_CHAN];
+  wire [9:0]  usedw	[0:NUM_CHAN];
+  wire empty[0:NUM_CHAN];
+	
+  generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+    begin : generate_channel_fifos
+
+      wire rdreq;
+
+      assign rdreq = (rd_select == i) & chan_rdreq;
+
+      fifo_1kx16 rx_chan_fifo (
+      .aclr ( reset ),
+      .clock ( rxclk ),
+      .data ( fifodata_il[i] ),
+      .rdreq ( rdreq ),
+      .wrreq ( ~rx_full[i] & wr),
+      .empty (empty[i]),
+      .full (rx_full[i]),
+      .q ( dataout[i]),
+      .usedw ( usedw[i]),
+      .almost_empty(chan_empty[i])
+      );
+    end
+  endgenerate
+	
+  wire [7:0] debug;
+	 
+  fifo_1kx16 rx_cmd_fifo (
+    .aclr ( reset ),
+    .clock ( rxclk ),
+    .data ( rx_databus ),
+    .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+    .wrreq ( rx_WR & rx_WR_enabled),
+    .empty ( cmd_empty),
+    .full ( rx_full[NUM_CHAN] ),
+    .q ( dataout[NUM_CHAN]),
+    .usedw ( usedw[NUM_CHAN] )
+  );
+	
+  assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+  assign chan_fifodata = dataout[rd_select];
+  assign chan_usedw = usedw[rd_select];
+  assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
+
+endmodule

fpga/usrp1/inband_lib/tx_buffer_inband.v

@@ -0,0 +1,143 @@
+module tx_buffer_inband
+  ( //System
+    input wire usbclk, input wire bus_reset, input wire reset, 
+    input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, 
+    //output transmit signals
+    output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, 
+    output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
+    output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, 
+    output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, 
+    input wire txclk, input wire txstrobe, input wire WR,
+    input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, 
+    //command reader io
+    output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, 
+    input wire rx_WR_enabled,
+    //register io 
+    output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
+    input wire [31:0] reg_data_out,  
+    //input characteristic signals
+    input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, 
+    input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, 
+    output wire [1:0] tx_underrun, 
+    //system stop
+    output wire stop, output wire [15:0] stop_time);
+	
+   parameter NUM_CHAN	 =      1 ;
+    
+   /* To generate channel readers */
+   genvar i ;
+    
+   /* These will eventually be external register */
+   reg                  [31:0] timestamp_clock ;
+   wire                 [7:0]  txstrobe_rate [NUM_CHAN-1:0] ;
+   wire			        [31:0] rssi [3:0];
+   assign rssi[0] = rssi_0;
+   assign rssi[1] = rssi_1;
+   assign rssi[2] = rssi_2;
+   assign rssi[3] = rssi_3;
+   
+   always @(posedge txclk)
+       if (reset)
+           timestamp_clock <= 0;
+       else
+           timestamp_clock <= timestamp_clock + 1;
+
+
+    /* Connections between tx_usb_fifo_reader and
+       cnannel/command processing blocks */
+   wire                  [31:0] tx_data_bus ;
+   wire            [NUM_CHAN:0] chan_WR ;
+   wire            [NUM_CHAN:0] chan_done ;
+    
+    /* Connections between data block and the
+       FX2/TX chains */
+   wire            [NUM_CHAN:0] chan_underrun;
+   wire            [NUM_CHAN:0] chan_txempty;
+   
+   /* Conections between tx_data_packet_fifo and
+       its reader + strobe generator */
+   wire                 [31:0] chan_fifodata [NUM_CHAN:0] ;
+   wire                        chan_pkt_waiting [NUM_CHAN:0] ;
+   wire                        chan_rdreq [NUM_CHAN:0] ;
+   wire                        chan_skip [NUM_CHAN:0] ;
+   wire                        chan_have_space [NUM_CHAN:0] ;
+
+   wire		            [14:0] debug [NUM_CHAN:0];
+    
+   /* Outputs to transmit chains */
+   wire                 [15:0] tx_i [NUM_CHAN:0] ;
+   wire                 [15:0] tx_q [NUM_CHAN:0] ;
+
+   assign tx_i[NUM_CHAN] = 0;
+   assign tx_q[NUM_CHAN] = 0;
+    
+   assign have_space = chan_have_space[0] & chan_have_space[1];
+   assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
+
+   assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
+   assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
+   assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
+   assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
+        
+   assign tx_q_2 = 16'b0 ;
+   assign tx_i_2 = 16'b0 ;
+   assign tx_q_3 = 16'b0 ;
+   assign tx_i_3 = 16'b0 ;
+   assign tx_i_3 = 16'b0 ;
+	
+   assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, 
+                      chan_pkt_waiting[0], chan_pkt_waiting[1],
+                      chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
+
+   wire [31:0] usbdata_final;
+   wire		WR_final;
+
+   tx_packer tx_usb_packer
+   (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
+    .usbdata(usbdata), .reset(reset), .txclk(txclk),
+    .usbdata_final(usbdata_final), .WR_final(WR_final));
+	
+   channel_demux #(NUM_CHAN) channel_demuxer
+   (.usbdata_final(usbdata_final), .WR_final(WR_final),
+    .reset(reset), .txclk(txclk), .WR_channel(chan_WR),
+    .WR_done_channel(chan_done), .ram_data(tx_data_bus));
+	
+   generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+     begin : generate_channel_readers
+       assign tx_underrun[i] = chan_underrun[i];
+
+       channel_ram tx_data_packet_fifo 
+       (.reset(reset), .txclk(txclk), .datain(tx_data_bus),
+        .WR(chan_WR[i]), .WR_done(chan_done[i]),
+        .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
+        .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
+        .RD_done(chan_skip[i]));
+
+       chan_fifo_reader tx_chan_reader 
+       (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
+        .timestamp_clock(timestamp_clock), .samples_format(4'b0),          
+        .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
+        .skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
+        .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
+        .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
+        .threshhold(threshhold), .rssi_wait(rssi_wait));	         
+    end
+    endgenerate
+
+
+   channel_ram tx_cmd_packet_fifo 
+   (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
+    .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
+    .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
+    .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
+
+   cmd_reader tx_cmd_reader
+   (.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]),
+    .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
+    .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
+    .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
+    .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
+    .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
+				   
+endmodule // tx_buffer
+

fpga/usrp1/inband_lib/tx_packer.v

@@ -0,0 +1,119 @@
+module tx_packer
+   (     //FX2 Side
+			input bus_reset, 
+			input usbclk, 
+			input WR_fx2, 
+			input [15:0]usbdata,
+			
+			// TX Side
+			input reset,
+			input txclk,
+			output reg [31:0] usbdata_final,
+			output reg WR_final);
+
+	reg [8:0] write_count;
+
+	/* Fix FX2 bug */
+	always @(posedge usbclk)
+	begin
+    	if(bus_reset)        // Use bus reset because this is on usbclk
+       		write_count <= #1 0;
+    	else if(WR_fx2 & ~write_count[8])
+    		write_count <= #1 write_count + 9'd1;
+    	else
+    		write_count <= #1 WR_fx2 ? write_count : 9'b0;
+	end
+	
+	reg WR_fx2_fixed;
+	reg [15:0]usbdata_fixed;
+	
+	always @(posedge usbclk) 
+	begin
+	   WR_fx2_fixed <= WR_fx2 & ~write_count[8];
+	   usbdata_fixed <= usbdata;
+	end
+
+	/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
+    reg                             word_complete ;
+    reg     [15:0]         			usbdata_delayed ;
+    reg                             writing ;
+	wire	[31:0]					usbdata_packed ;    
+	wire							WR_packed ;
+   
+    always @(posedge usbclk)
+    begin
+        if (bus_reset)
+          begin
+            word_complete <= 0 ;
+            writing <= 0 ;
+          end
+        else if (WR_fx2_fixed)
+          begin
+            writing <= 1 ;
+            if (word_complete)
+                word_complete <= 0 ;
+            else
+              begin
+                usbdata_delayed <= usbdata_fixed ;
+                word_complete <= 1 ;
+              end
+          end
+        else
+            writing <= 0 ;
+	end
+    
+	assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
+    assign WR_packed = word_complete & writing ;
+
+	/* Make sure data are sync with usbclk */
+ 	reg [31:0]usbdata_usbclk;
+	reg WR_usbclk; 
+    
+    always @(posedge usbclk)
+    begin
+    	if (WR_packed)
+    		usbdata_usbclk <= usbdata_packed;
+        WR_usbclk <= WR_packed;
+    end
+
+	/* Cross clock boundaries */
+	reg [31:0] usbdata_tx ;
+	reg WR_tx;
+    reg WR_1;
+    reg WR_2;
+  
+	always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
+
+    always @(posedge txclk) 
+    	if (reset)
+    		WR_1 <= 0;
+    	else
+       		WR_1 <= WR_usbclk;
+
+    always @(posedge txclk) 
+    	if (reset)
+       		WR_2 <= 0;
+    	else
+      		WR_2 <= WR_1;
+
+	always @(posedge txclk)
+	begin
+		if (reset)
+			WR_tx <= 0;
+		else
+		   WR_tx <= WR_1 & ~WR_2;
+	end
+	
+	always @(posedge txclk)
+	begin
+	   if (reset)
+	      WR_final <= 0;
+	   else
+	   begin
+	      WR_final <= WR_tx; 
+	      if (WR_tx)
+	         usbdata_final <= usbdata_tx;
+	   end
+	end
+
+endmodule

fpga/usrp1/inband_lib/usb_packet_fifo.v

@@ -0,0 +1,112 @@
+module usb_packet_fifo 
+  ( input       reset,
+    input       clock_in,
+    input       clock_out,
+    input       [15:0]ram_data_in,
+    input       write_enable,
+    output  reg [15:0]ram_data_out,
+    output  reg pkt_waiting,
+    output  reg have_space,
+    input       read_enable,
+    input       skip_packet          ) ;
+
+    /* Some parameters for usage later on */
+    parameter DATA_WIDTH = 16 ;
+    parameter NUM_PACKETS = 4 ;
+
+    /* Create the RAM here */
+    reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+
+    /* Create the address signals */
+    reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
+    reg [7:0] usb_ram_offset ;
+    reg [1:0] usb_ram_packet ;
+
+    wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+    reg isfull;
+
+    assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
+    
+    // Check if there is one full packet to process
+    always @(usb_ram_ain, usb_ram_aout)
+    begin
+        if (reset)
+            pkt_waiting <= 0;
+        else if (usb_ram_ain == usb_ram_aout)
+            pkt_waiting <= isfull;
+        else if (usb_ram_ain > usb_ram_aout)
+            pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
+        else
+            pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
+    end
+    
+    // Check if there is room
+    always @(usb_ram_ain, usb_ram_aout)
+    begin
+        if (reset)
+            have_space <= 1;
+        else if (usb_ram_ain == usb_ram_aout)
+            have_space <= ~isfull;   
+        else if (usb_ram_ain > usb_ram_aout)
+            have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
+        else
+            have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
+    end
+
+    /* RAM Write Address process */
+    always @(posedge clock_in)
+    begin
+        if( reset )
+            usb_ram_ain <= 0 ;
+        else
+            if( write_enable ) 
+              begin
+                usb_ram_ain <= usb_ram_ain + 1 ;
+                if (usb_ram_ain + 1 == usb_ram_aout)
+                   isfull <= 1;
+              end
+    end
+
+    /* RAM Writing process */
+    always @(posedge clock_in)
+    begin
+        if( write_enable ) 
+          begin
+            usb_ram[usb_ram_ain] <= ram_data_in ;
+          end
+    end
+
+    /* RAM Read Address process */
+    always @(posedge clock_out)
+    begin
+        if( reset ) 
+          begin
+            usb_ram_packet <= 0 ;
+            usb_ram_offset <= 0 ;
+            isfull <= 0;
+          end
+        else
+            if( skip_packet )
+              begin
+                usb_ram_packet <= usb_ram_packet + 1 ;
+                usb_ram_offset <= 0 ;
+              end
+            else if(read_enable)
+                if( usb_ram_offset == 8'b11111111 )
+                  begin
+                    usb_ram_offset <= 0 ;
+                    usb_ram_packet <= usb_ram_packet + 1 ;
+                  end
+                else
+                    usb_ram_offset <= usb_ram_offset + 1 ;
+            if (usb_ram_ain == usb_ram_aout)
+               isfull <= 0;                       
+    end
+
+    /* RAM Reading Process */
+    always @(posedge clock_out)
+    begin
+        ram_data_out <= usb_ram[usb_ram_aout] ;
+    end
+
+endmodule

fpga/usrp1/megacells/.gitignore

@@ -0,0 +1 @@
+/db

fpga/usrp1/megacells/accum32.bsf

@@ -0,0 +1,86 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+support information,  device programming or simulation file,  and any other
+associated  documentation or information  provided by  Altera  or a partner
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+other  use  of such  megafunction  design,  netlist,  support  information,
+device programming or simulation file,  or any other  related documentation
+or information  is prohibited  for  any  other purpose,  including, but not
+limited to  modification,  reverse engineering,  de-compiling, or use  with
+any other  silicon devices,  unless such use is  explicitly  licensed under
+a separate agreement with  Altera  or a megafunction partner.  Title to the
+intellectual property,  including patents,  copyrights,  trademarks,  trade
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+support  information,  device programming or simulation file,  or any other
+related documentation or information provided by  Altera  or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 240 120)
+	(text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 101 31 116)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 240 56)
+		(output)
+		(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8)))
+		(line (pt 240 56)(pt 224 56)(line_width 3))
+	)
+	(drawing
+		(text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8)))
+		(text "SIGNED" (rect 177 18 214 32)(font "Arial" ))
+		(line (pt 16 16)(pt 224 16)(line_width 1))
+		(line (pt 16 16)(pt 16 104)(line_width 1))
+		(line (pt 16 104)(pt 224 104)(line_width 1))
+		(line (pt 224 16)(pt 224 104)(line_width 1))
+		(line (pt 88 24)(pt 136 48)(line_width 1))
+		(line (pt 136 64)(pt 136 48)(line_width 1))
+		(line (pt 88 88)(pt 136 64)(line_width 1))
+		(line (pt 88 24)(pt 88 88)(line_width 1))
+		(line (pt 16 40)(pt 88 40)(line_width 1))
+		(line (pt 16 56)(pt 88 56)(line_width 1))
+		(line (pt 136 56)(pt 224 56)(line_width 1))
+		(line (pt 16 72)(pt 88 72)(line_width 1))
+		(line (pt 16 72)(pt 88 72)(line_width 1))
+		(line (pt 16 96)(pt 104 96)(line_width 1))
+		(line (pt 104 96)(pt 104 80)(line_width 1))
+	)
+)

fpga/usrp1/megacells/accum32.cmp

@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component accum32
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '0';
+		clken		: IN STD_LOGIC  := '1';
+		aclr		: IN STD_LOGIC  := '0';
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/accum32.inc

@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION accum32 
+(
+	data[31..0],
+	clock,
+	clken,
+	aclr
+)
+
+RETURNS (
+	result[31..0]
+);

fpga/usrp1/megacells/accum32.v

@@ -0,0 +1,765 @@
+// megafunction wizard: %ALTACCUMULATE%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altaccumulate 
+
+// ============================================================
+// File Name: accum32.v
+// Megafunction Name(s):
+// 			altaccumulate
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
+//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 32 
+module  accum32_accum_nta
+	( 
+	aclr,
+	clken,
+	clock,
+	data,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   aclr;
+	input   clken;
+	input   clock;
+	input   [31:0]  data;
+	output   [31:0]  result;
+
+	wire  [0:0]   wire_acc_cella_0cout;
+	wire  [0:0]   wire_acc_cella_1cout;
+	wire  [0:0]   wire_acc_cella_2cout;
+	wire  [0:0]   wire_acc_cella_3cout;
+	wire  [0:0]   wire_acc_cella_4cout;
+	wire  [0:0]   wire_acc_cella_5cout;
+	wire  [0:0]   wire_acc_cella_6cout;
+	wire  [0:0]   wire_acc_cella_7cout;
+	wire  [0:0]   wire_acc_cella_8cout;
+	wire  [0:0]   wire_acc_cella_9cout;
+	wire  [0:0]   wire_acc_cella_10cout;
+	wire  [0:0]   wire_acc_cella_11cout;
+	wire  [0:0]   wire_acc_cella_12cout;
+	wire  [0:0]   wire_acc_cella_13cout;
+	wire  [0:0]   wire_acc_cella_14cout;
+	wire  [0:0]   wire_acc_cella_15cout;
+	wire  [0:0]   wire_acc_cella_16cout;
+	wire  [0:0]   wire_acc_cella_17cout;
+	wire  [0:0]   wire_acc_cella_18cout;
+	wire  [0:0]   wire_acc_cella_19cout;
+	wire  [0:0]   wire_acc_cella_20cout;
+	wire  [0:0]   wire_acc_cella_21cout;
+	wire  [0:0]   wire_acc_cella_22cout;
+	wire  [0:0]   wire_acc_cella_23cout;
+	wire  [0:0]   wire_acc_cella_24cout;
+	wire  [0:0]   wire_acc_cella_25cout;
+	wire  [0:0]   wire_acc_cella_26cout;
+	wire  [0:0]   wire_acc_cella_27cout;
+	wire  [0:0]   wire_acc_cella_28cout;
+	wire  [0:0]   wire_acc_cella_29cout;
+	wire  [0:0]   wire_acc_cella_30cout;
+	wire  [31:0]   wire_acc_cella_dataa;
+	wire  [31:0]   wire_acc_cella_datab;
+	wire  [31:0]   wire_acc_cella_datac;
+	wire  [31:0]   wire_acc_cella_regout;
+	wire sload;
+
+	stratix_lcell   acc_cella_0
+	( 
+	.aclr(aclr),
+	.cin(1'b0),
+	.clk(clock),
+	.cout(wire_acc_cella_0cout[0:0]),
+	.dataa(wire_acc_cella_dataa[0:0]),
+	.datab(wire_acc_cella_datab[0:0]),
+	.datac(wire_acc_cella_datac[0:0]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[0:0]),
+	.sload(sload));
+	defparam
+		acc_cella_0.cin_used = "true",
+		acc_cella_0.lut_mask = "96e8",
+		acc_cella_0.operation_mode = "arithmetic",
+		acc_cella_0.sum_lutc_input = "cin",
+		acc_cella_0.synch_mode = "on",
+		acc_cella_0.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_1
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_0cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_1cout[0:0]),
+	.dataa(wire_acc_cella_dataa[1:1]),
+	.datab(wire_acc_cella_datab[1:1]),
+	.datac(wire_acc_cella_datac[1:1]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[1:1]),
+	.sload(sload));
+	defparam
+		acc_cella_1.cin_used = "true",
+		acc_cella_1.lut_mask = "96e8",
+		acc_cella_1.operation_mode = "arithmetic",
+		acc_cella_1.sum_lutc_input = "cin",
+		acc_cella_1.synch_mode = "on",
+		acc_cella_1.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_2
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_1cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_2cout[0:0]),
+	.dataa(wire_acc_cella_dataa[2:2]),
+	.datab(wire_acc_cella_datab[2:2]),
+	.datac(wire_acc_cella_datac[2:2]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[2:2]),
+	.sload(sload));
+	defparam
+		acc_cella_2.cin_used = "true",
+		acc_cella_2.lut_mask = "96e8",
+		acc_cella_2.operation_mode = "arithmetic",
+		acc_cella_2.sum_lutc_input = "cin",
+		acc_cella_2.synch_mode = "on",
+		acc_cella_2.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_3
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_2cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_3cout[0:0]),
+	.dataa(wire_acc_cella_dataa[3:3]),
+	.datab(wire_acc_cella_datab[3:3]),
+	.datac(wire_acc_cella_datac[3:3]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[3:3]),
+	.sload(sload));
+	defparam
+		acc_cella_3.cin_used = "true",
+		acc_cella_3.lut_mask = "96e8",
+		acc_cella_3.operation_mode = "arithmetic",
+		acc_cella_3.sum_lutc_input = "cin",
+		acc_cella_3.synch_mode = "on",
+		acc_cella_3.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_4
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_3cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_4cout[0:0]),
+	.dataa(wire_acc_cella_dataa[4:4]),
+	.datab(wire_acc_cella_datab[4:4]),
+	.datac(wire_acc_cella_datac[4:4]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[4:4]),
+	.sload(sload));
+	defparam
+		acc_cella_4.cin_used = "true",
+		acc_cella_4.lut_mask = "96e8",
+		acc_cella_4.operation_mode = "arithmetic",
+		acc_cella_4.sum_lutc_input = "cin",
+		acc_cella_4.synch_mode = "on",
+		acc_cella_4.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_5
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_4cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_5cout[0:0]),
+	.dataa(wire_acc_cella_dataa[5:5]),
+	.datab(wire_acc_cella_datab[5:5]),
+	.datac(wire_acc_cella_datac[5:5]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[5:5]),
+	.sload(sload));
+	defparam
+		acc_cella_5.cin_used = "true",
+		acc_cella_5.lut_mask = "96e8",
+		acc_cella_5.operation_mode = "arithmetic",
+		acc_cella_5.sum_lutc_input = "cin",
+		acc_cella_5.synch_mode = "on",
+		acc_cella_5.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_6
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_5cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_6cout[0:0]),
+	.dataa(wire_acc_cella_dataa[6:6]),
+	.datab(wire_acc_cella_datab[6:6]),
+	.datac(wire_acc_cella_datac[6:6]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[6:6]),
+	.sload(sload));
+	defparam
+		acc_cella_6.cin_used = "true",
+		acc_cella_6.lut_mask = "96e8",
+		acc_cella_6.operation_mode = "arithmetic",
+		acc_cella_6.sum_lutc_input = "cin",
+		acc_cella_6.synch_mode = "on",
+		acc_cella_6.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_7
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_6cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_7cout[0:0]),
+	.dataa(wire_acc_cella_dataa[7:7]),
+	.datab(wire_acc_cella_datab[7:7]),
+	.datac(wire_acc_cella_datac[7:7]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[7:7]),
+	.sload(sload));
+	defparam
+		acc_cella_7.cin_used = "true",
+		acc_cella_7.lut_mask = "96e8",
+		acc_cella_7.operation_mode = "arithmetic",
+		acc_cella_7.sum_lutc_input = "cin",
+		acc_cella_7.synch_mode = "on",
+		acc_cella_7.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_8
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_7cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_8cout[0:0]),
+	.dataa(wire_acc_cella_dataa[8:8]),
+	.datab(wire_acc_cella_datab[8:8]),
+	.datac(wire_acc_cella_datac[8:8]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[8:8]),
+	.sload(sload));
+	defparam
+		acc_cella_8.cin_used = "true",
+		acc_cella_8.lut_mask = "96e8",
+		acc_cella_8.operation_mode = "arithmetic",
+		acc_cella_8.sum_lutc_input = "cin",
+		acc_cella_8.synch_mode = "on",
+		acc_cella_8.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_9
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_8cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_9cout[0:0]),
+	.dataa(wire_acc_cella_dataa[9:9]),
+	.datab(wire_acc_cella_datab[9:9]),
+	.datac(wire_acc_cella_datac[9:9]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[9:9]),
+	.sload(sload));
+	defparam
+		acc_cella_9.cin_used = "true",
+		acc_cella_9.lut_mask = "96e8",
+		acc_cella_9.operation_mode = "arithmetic",
+		acc_cella_9.sum_lutc_input = "cin",
+		acc_cella_9.synch_mode = "on",
+		acc_cella_9.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_10
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_9cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_10cout[0:0]),
+	.dataa(wire_acc_cella_dataa[10:10]),
+	.datab(wire_acc_cella_datab[10:10]),
+	.datac(wire_acc_cella_datac[10:10]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[10:10]),
+	.sload(sload));
+	defparam
+		acc_cella_10.cin_used = "true",
+		acc_cella_10.lut_mask = "96e8",
+		acc_cella_10.operation_mode = "arithmetic",
+		acc_cella_10.sum_lutc_input = "cin",
+		acc_cella_10.synch_mode = "on",
+		acc_cella_10.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_11
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_10cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_11cout[0:0]),
+	.dataa(wire_acc_cella_dataa[11:11]),
+	.datab(wire_acc_cella_datab[11:11]),
+	.datac(wire_acc_cella_datac[11:11]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[11:11]),
+	.sload(sload));
+	defparam
+		acc_cella_11.cin_used = "true",
+		acc_cella_11.lut_mask = "96e8",
+		acc_cella_11.operation_mode = "arithmetic",
+		acc_cella_11.sum_lutc_input = "cin",
+		acc_cella_11.synch_mode = "on",
+		acc_cella_11.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_12
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_11cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_12cout[0:0]),
+	.dataa(wire_acc_cella_dataa[12:12]),
+	.datab(wire_acc_cella_datab[12:12]),
+	.datac(wire_acc_cella_datac[12:12]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[12:12]),
+	.sload(sload));
+	defparam
+		acc_cella_12.cin_used = "true",
+		acc_cella_12.lut_mask = "96e8",
+		acc_cella_12.operation_mode = "arithmetic",
+		acc_cella_12.sum_lutc_input = "cin",
+		acc_cella_12.synch_mode = "on",
+		acc_cella_12.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_13
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_12cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_13cout[0:0]),
+	.dataa(wire_acc_cella_dataa[13:13]),
+	.datab(wire_acc_cella_datab[13:13]),
+	.datac(wire_acc_cella_datac[13:13]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[13:13]),
+	.sload(sload));
+	defparam
+		acc_cella_13.cin_used = "true",
+		acc_cella_13.lut_mask = "96e8",
+		acc_cella_13.operation_mode = "arithmetic",
+		acc_cella_13.sum_lutc_input = "cin",
+		acc_cella_13.synch_mode = "on",
+		acc_cella_13.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_14
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_13cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_14cout[0:0]),
+	.dataa(wire_acc_cella_dataa[14:14]),
+	.datab(wire_acc_cella_datab[14:14]),
+	.datac(wire_acc_cella_datac[14:14]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[14:14]),
+	.sload(sload));
+	defparam
+		acc_cella_14.cin_used = "true",
+		acc_cella_14.lut_mask = "96e8",
+		acc_cella_14.operation_mode = "arithmetic",
+		acc_cella_14.sum_lutc_input = "cin",
+		acc_cella_14.synch_mode = "on",
+		acc_cella_14.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_15
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_14cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_15cout[0:0]),
+	.dataa(wire_acc_cella_dataa[15:15]),
+	.datab(wire_acc_cella_datab[15:15]),
+	.datac(wire_acc_cella_datac[15:15]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[15:15]),
+	.sload(sload));
+	defparam
+		acc_cella_15.cin_used = "true",
+		acc_cella_15.lut_mask = "96e8",
+		acc_cella_15.operation_mode = "arithmetic",
+		acc_cella_15.sum_lutc_input = "cin",
+		acc_cella_15.synch_mode = "on",
+		acc_cella_15.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_16
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_15cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_16cout[0:0]),
+	.dataa(wire_acc_cella_dataa[16:16]),
+	.datab(wire_acc_cella_datab[16:16]),
+	.datac(wire_acc_cella_datac[16:16]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[16:16]),
+	.sload(sload));
+	defparam
+		acc_cella_16.cin_used = "true",
+		acc_cella_16.lut_mask = "96e8",
+		acc_cella_16.operation_mode = "arithmetic",
+		acc_cella_16.sum_lutc_input = "cin",
+		acc_cella_16.synch_mode = "on",
+		acc_cella_16.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_17
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_16cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_17cout[0:0]),
+	.dataa(wire_acc_cella_dataa[17:17]),
+	.datab(wire_acc_cella_datab[17:17]),
+	.datac(wire_acc_cella_datac[17:17]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[17:17]),
+	.sload(sload));
+	defparam
+		acc_cella_17.cin_used = "true",
+		acc_cella_17.lut_mask = "96e8",
+		acc_cella_17.operation_mode = "arithmetic",
+		acc_cella_17.sum_lutc_input = "cin",
+		acc_cella_17.synch_mode = "on",
+		acc_cella_17.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_18
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_17cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_18cout[0:0]),
+	.dataa(wire_acc_cella_dataa[18:18]),
+	.datab(wire_acc_cella_datab[18:18]),
+	.datac(wire_acc_cella_datac[18:18]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[18:18]),
+	.sload(sload));
+	defparam
+		acc_cella_18.cin_used = "true",
+		acc_cella_18.lut_mask = "96e8",
+		acc_cella_18.operation_mode = "arithmetic",
+		acc_cella_18.sum_lutc_input = "cin",
+		acc_cella_18.synch_mode = "on",
+		acc_cella_18.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_19
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_18cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_19cout[0:0]),
+	.dataa(wire_acc_cella_dataa[19:19]),
+	.datab(wire_acc_cella_datab[19:19]),
+	.datac(wire_acc_cella_datac[19:19]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[19:19]),
+	.sload(sload));
+	defparam
+		acc_cella_19.cin_used = "true",
+		acc_cella_19.lut_mask = "96e8",
+		acc_cella_19.operation_mode = "arithmetic",
+		acc_cella_19.sum_lutc_input = "cin",
+		acc_cella_19.synch_mode = "on",
+		acc_cella_19.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_20
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_19cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_20cout[0:0]),
+	.dataa(wire_acc_cella_dataa[20:20]),
+	.datab(wire_acc_cella_datab[20:20]),
+	.datac(wire_acc_cella_datac[20:20]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[20:20]),
+	.sload(sload));
+	defparam
+		acc_cella_20.cin_used = "true",
+		acc_cella_20.lut_mask = "96e8",
+		acc_cella_20.operation_mode = "arithmetic",
+		acc_cella_20.sum_lutc_input = "cin",
+		acc_cella_20.synch_mode = "on",
+		acc_cella_20.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_21
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_20cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_21cout[0:0]),
+	.dataa(wire_acc_cella_dataa[21:21]),
+	.datab(wire_acc_cella_datab[21:21]),
+	.datac(wire_acc_cella_datac[21:21]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[21:21]),
+	.sload(sload));
+	defparam
+		acc_cella_21.cin_used = "true",
+		acc_cella_21.lut_mask = "96e8",
+		acc_cella_21.operation_mode = "arithmetic",
+		acc_cella_21.sum_lutc_input = "cin",
+		acc_cella_21.synch_mode = "on",
+		acc_cella_21.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_22
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_21cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_22cout[0:0]),
+	.dataa(wire_acc_cella_dataa[22:22]),
+	.datab(wire_acc_cella_datab[22:22]),
+	.datac(wire_acc_cella_datac[22:22]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[22:22]),
+	.sload(sload));
+	defparam
+		acc_cella_22.cin_used = "true",
+		acc_cella_22.lut_mask = "96e8",
+		acc_cella_22.operation_mode = "arithmetic",
+		acc_cella_22.sum_lutc_input = "cin",
+		acc_cella_22.synch_mode = "on",
+		acc_cella_22.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_23
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_22cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_23cout[0:0]),
+	.dataa(wire_acc_cella_dataa[23:23]),
+	.datab(wire_acc_cella_datab[23:23]),
+	.datac(wire_acc_cella_datac[23:23]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[23:23]),
+	.sload(sload));
+	defparam
+		acc_cella_23.cin_used = "true",
+		acc_cella_23.lut_mask = "96e8",
+		acc_cella_23.operation_mode = "arithmetic",
+		acc_cella_23.sum_lutc_input = "cin",
+		acc_cella_23.synch_mode = "on",
+		acc_cella_23.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_24
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_23cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_24cout[0:0]),
+	.dataa(wire_acc_cella_dataa[24:24]),
+	.datab(wire_acc_cella_datab[24:24]),
+	.datac(wire_acc_cella_datac[24:24]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[24:24]),
+	.sload(sload));
+	defparam
+		acc_cella_24.cin_used = "true",
+		acc_cella_24.lut_mask = "96e8",
+		acc_cella_24.operation_mode = "arithmetic",
+		acc_cella_24.sum_lutc_input = "cin",
+		acc_cella_24.synch_mode = "on",
+		acc_cella_24.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_25
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_24cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_25cout[0:0]),
+	.dataa(wire_acc_cella_dataa[25:25]),
+	.datab(wire_acc_cella_datab[25:25]),
+	.datac(wire_acc_cella_datac[25:25]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[25:25]),
+	.sload(sload));
+	defparam
+		acc_cella_25.cin_used = "true",
+		acc_cella_25.lut_mask = "96e8",
+		acc_cella_25.operation_mode = "arithmetic",
+		acc_cella_25.sum_lutc_input = "cin",
+		acc_cella_25.synch_mode = "on",
+		acc_cella_25.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_26
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_25cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_26cout[0:0]),
+	.dataa(wire_acc_cella_dataa[26:26]),
+	.datab(wire_acc_cella_datab[26:26]),
+	.datac(wire_acc_cella_datac[26:26]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[26:26]),
+	.sload(sload));
+	defparam
+		acc_cella_26.cin_used = "true",
+		acc_cella_26.lut_mask = "96e8",
+		acc_cella_26.operation_mode = "arithmetic",
+		acc_cella_26.sum_lutc_input = "cin",
+		acc_cella_26.synch_mode = "on",
+		acc_cella_26.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_27
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_26cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_27cout[0:0]),
+	.dataa(wire_acc_cella_dataa[27:27]),
+	.datab(wire_acc_cella_datab[27:27]),
+	.datac(wire_acc_cella_datac[27:27]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[27:27]),
+	.sload(sload));
+	defparam
+		acc_cella_27.cin_used = "true",
+		acc_cella_27.lut_mask = "96e8",
+		acc_cella_27.operation_mode = "arithmetic",
+		acc_cella_27.sum_lutc_input = "cin",
+		acc_cella_27.synch_mode = "on",
+		acc_cella_27.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_28
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_27cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_28cout[0:0]),
+	.dataa(wire_acc_cella_dataa[28:28]),
+	.datab(wire_acc_cella_datab[28:28]),
+	.datac(wire_acc_cella_datac[28:28]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[28:28]),
+	.sload(sload));
+	defparam
+		acc_cella_28.cin_used = "true",
+		acc_cella_28.lut_mask = "96e8",
+		acc_cella_28.operation_mode = "arithmetic",
+		acc_cella_28.sum_lutc_input = "cin",
+		acc_cella_28.synch_mode = "on",
+		acc_cella_28.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_29
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_28cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_29cout[0:0]),
+	.dataa(wire_acc_cella_dataa[29:29]),
+	.datab(wire_acc_cella_datab[29:29]),
+	.datac(wire_acc_cella_datac[29:29]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[29:29]),
+	.sload(sload));
+	defparam
+		acc_cella_29.cin_used = "true",
+		acc_cella_29.lut_mask = "96e8",
+		acc_cella_29.operation_mode = "arithmetic",
+		acc_cella_29.sum_lutc_input = "cin",
+		acc_cella_29.synch_mode = "on",
+		acc_cella_29.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_30
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_29cout[0:0]),
+	.clk(clock),
+	.cout(wire_acc_cella_30cout[0:0]),
+	.dataa(wire_acc_cella_dataa[30:30]),
+	.datab(wire_acc_cella_datab[30:30]),
+	.datac(wire_acc_cella_datac[30:30]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[30:30]),
+	.sload(sload));
+	defparam
+		acc_cella_30.cin_used = "true",
+		acc_cella_30.lut_mask = "96e8",
+		acc_cella_30.operation_mode = "arithmetic",
+		acc_cella_30.sum_lutc_input = "cin",
+		acc_cella_30.synch_mode = "on",
+		acc_cella_30.lpm_type = "stratix_lcell";
+	stratix_lcell   acc_cella_31
+	( 
+	.aclr(aclr),
+	.cin(wire_acc_cella_30cout[0:0]),
+	.clk(clock),
+	.dataa(wire_acc_cella_dataa[31:31]),
+	.datab(wire_acc_cella_datab[31:31]),
+	.datac(wire_acc_cella_datac[31:31]),
+	.ena(clken),
+	.regout(wire_acc_cella_regout[31:31]),
+	.sload(sload));
+	defparam
+		acc_cella_31.cin_used = "true",
+		acc_cella_31.lut_mask = "9696",
+		acc_cella_31.operation_mode = "normal",
+		acc_cella_31.sum_lutc_input = "cin",
+		acc_cella_31.synch_mode = "on",
+		acc_cella_31.lpm_type = "stratix_lcell";
+	assign
+		wire_acc_cella_dataa = data,
+		wire_acc_cella_datab = wire_acc_cella_regout,
+		wire_acc_cella_datac = data;
+	assign
+		result = wire_acc_cella_regout,
+		sload = 1'b0;
+endmodule //accum32_accum_nta
+//VALID FILE
+
+
+module accum32 (
+	data,
+	clock,
+	clken,
+	aclr,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[31:0]  data;
+	input	  clock;
+	input	  clken;
+	input	  aclr;
+	output	[31:0]  result;
+
+	wire [31:0] sub_wire0;
+	wire [31:0] result = sub_wire0[31:0];
+
+	accum32_accum_nta	accum32_accum_nta_component (
+				.clken (clken),
+				.aclr (aclr),
+				.clock (clock),
+				.data (data),
+				.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
+// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
+// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
+// Retrieval info: PRIVATE: CIN NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: ACLR NUMERIC "1"
+// Retrieval info: PRIVATE: COUT NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
+// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
+// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

fpga/usrp1/megacells/accum32_bb.v

@@ -0,0 +1,35 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module accum32 (
+	data,
+	clock,
+	clken,
+	aclr,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[31:0]  data;
+	input	  clock;
+	input	  clken;
+	input	  aclr;
+	output	[31:0]  result;
+
+endmodule
+

fpga/usrp1/megacells/accum32_inst.v

@@ -0,0 +1,7 @@
+accum32	accum32_inst (
+	.data ( data_sig ),
+	.clock ( clock_sig ),
+	.clken ( clken_sig ),
+	.aclr ( aclr_sig ),
+	.result ( result_sig )
+	);

fpga/usrp1/megacells/add32.bsf

@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+support information,  device programming or simulation file,  and any other
+associated  documentation or information  provided by  Altera  or a partner
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+other  use  of such  megafunction  design,  netlist,  support  information,
+device programming or simulation file,  or any other  related documentation
+or information  is prohibited  for  any  other purpose,  including, but not
+limited to  modification,  reverse engineering,  de-compiling, or use  with
+any other  silicon devices,  unless such use is  explicitly  licensed under
+a separate agreement with  Altera  or a megafunction partner.  Title to the
+intellectual property,  including patents,  copyrights,  trademarks,  trade
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+support  information,  device programming or simulation file,  or any other
+related documentation or information provided by  Altera  or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 96)
+	(text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 77 31 92)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+		(text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+		(text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 160 56)
+		(output)
+		(text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8)))
+		(line (pt 160 56)(pt 96 56)(line_width 3))
+	)
+	(drawing
+		(text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
+		(text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
+		(text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8)))
+		(line (pt 64 32)(pt 96 40)(line_width 1))
+		(line (pt 96 40)(pt 96 72)(line_width 1))
+		(line (pt 96 72)(pt 64 80)(line_width 1))
+		(line (pt 64 80)(pt 64 32)(line_width 1))
+	)
+)

fpga/usrp1/megacells/add32.cmp

@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component add32
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/add32.inc

@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION add32 
+(
+	dataa[7..0],
+	datab[7..0]
+)
+
+RETURNS (
+	result[7..0]
+);

fpga/usrp1/megacells/add32.v

@@ -0,0 +1,221 @@
+// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: add32.v
+// Megafunction Name(s):
+// 			lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 8 
+module  add32_add_sub_nq7
+	( 
+	dataa,
+	datab,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   [7:0]  dataa;
+	input   [7:0]  datab;
+	output   [7:0]  result;
+
+	wire  [7:0]   wire_add_sub_cella_combout;
+	wire  [0:0]   wire_add_sub_cella_0cout;
+	wire  [0:0]   wire_add_sub_cella_1cout;
+	wire  [0:0]   wire_add_sub_cella_2cout;
+	wire  [0:0]   wire_add_sub_cella_3cout;
+	wire  [0:0]   wire_add_sub_cella_4cout;
+	wire  [0:0]   wire_add_sub_cella_5cout;
+	wire  [0:0]   wire_add_sub_cella_6cout;
+	wire  [7:0]   wire_add_sub_cella_dataa;
+	wire  [7:0]   wire_add_sub_cella_datab;
+
+	stratix_lcell   add_sub_cella_0
+	( 
+	.cin(1'b0),
+	.combout(wire_add_sub_cella_combout[0:0]),
+	.cout(wire_add_sub_cella_0cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[0:0]),
+	.datab(wire_add_sub_cella_datab[0:0]));
+	defparam
+		add_sub_cella_0.cin_used = "true",
+		add_sub_cella_0.lut_mask = "96e8",
+		add_sub_cella_0.operation_mode = "arithmetic",
+		add_sub_cella_0.sum_lutc_input = "cin",
+		add_sub_cella_0.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_1
+	( 
+	.cin(wire_add_sub_cella_0cout[0:0]),
+	.combout(wire_add_sub_cella_combout[1:1]),
+	.cout(wire_add_sub_cella_1cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[1:1]),
+	.datab(wire_add_sub_cella_datab[1:1]));
+	defparam
+		add_sub_cella_1.cin_used = "true",
+		add_sub_cella_1.lut_mask = "96e8",
+		add_sub_cella_1.operation_mode = "arithmetic",
+		add_sub_cella_1.sum_lutc_input = "cin",
+		add_sub_cella_1.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_2
+	( 
+	.cin(wire_add_sub_cella_1cout[0:0]),
+	.combout(wire_add_sub_cella_combout[2:2]),
+	.cout(wire_add_sub_cella_2cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[2:2]),
+	.datab(wire_add_sub_cella_datab[2:2]));
+	defparam
+		add_sub_cella_2.cin_used = "true",
+		add_sub_cella_2.lut_mask = "96e8",
+		add_sub_cella_2.operation_mode = "arithmetic",
+		add_sub_cella_2.sum_lutc_input = "cin",
+		add_sub_cella_2.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_3
+	( 
+	.cin(wire_add_sub_cella_2cout[0:0]),
+	.combout(wire_add_sub_cella_combout[3:3]),
+	.cout(wire_add_sub_cella_3cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[3:3]),
+	.datab(wire_add_sub_cella_datab[3:3]));
+	defparam
+		add_sub_cella_3.cin_used = "true",
+		add_sub_cella_3.lut_mask = "96e8",
+		add_sub_cella_3.operation_mode = "arithmetic",
+		add_sub_cella_3.sum_lutc_input = "cin",
+		add_sub_cella_3.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_4
+	( 
+	.cin(wire_add_sub_cella_3cout[0:0]),
+	.combout(wire_add_sub_cella_combout[4:4]),
+	.cout(wire_add_sub_cella_4cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[4:4]),
+	.datab(wire_add_sub_cella_datab[4:4]));
+	defparam
+		add_sub_cella_4.cin_used = "true",
+		add_sub_cella_4.lut_mask = "96e8",
+		add_sub_cella_4.operation_mode = "arithmetic",
+		add_sub_cella_4.sum_lutc_input = "cin",
+		add_sub_cella_4.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_5
+	( 
+	.cin(wire_add_sub_cella_4cout[0:0]),
+	.combout(wire_add_sub_cella_combout[5:5]),
+	.cout(wire_add_sub_cella_5cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[5:5]),
+	.datab(wire_add_sub_cella_datab[5:5]));
+	defparam
+		add_sub_cella_5.cin_used = "true",
+		add_sub_cella_5.lut_mask = "96e8",
+		add_sub_cella_5.operation_mode = "arithmetic",
+		add_sub_cella_5.sum_lutc_input = "cin",
+		add_sub_cella_5.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_6
+	( 
+	.cin(wire_add_sub_cella_5cout[0:0]),
+	.combout(wire_add_sub_cella_combout[6:6]),
+	.cout(wire_add_sub_cella_6cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[6:6]),
+	.datab(wire_add_sub_cella_datab[6:6]));
+	defparam
+		add_sub_cella_6.cin_used = "true",
+		add_sub_cella_6.lut_mask = "96e8",
+		add_sub_cella_6.operation_mode = "arithmetic",
+		add_sub_cella_6.sum_lutc_input = "cin",
+		add_sub_cella_6.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_7
+	( 
+	.cin(wire_add_sub_cella_6cout[0:0]),
+	.combout(wire_add_sub_cella_combout[7:7]),
+	.dataa(wire_add_sub_cella_dataa[7:7]),
+	.datab(wire_add_sub_cella_datab[7:7]));
+	defparam
+		add_sub_cella_7.cin_used = "true",
+		add_sub_cella_7.lut_mask = "9696",
+		add_sub_cella_7.operation_mode = "normal",
+		add_sub_cella_7.sum_lutc_input = "cin",
+		add_sub_cella_7.lpm_type = "stratix_lcell";
+	assign
+		wire_add_sub_cella_dataa = dataa,
+		wire_add_sub_cella_datab = datab;
+	assign
+		result = wire_add_sub_cella_combout;
+endmodule //add32_add_sub_nq7
+//VALID FILE
+
+
+module add32 (
+	dataa,
+	datab,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[7:0]  dataa;
+	input	[7:0]  datab;
+	output	[7:0]  result;
+
+	wire [7:0] sub_wire0;
+	wire [7:0] result = sub_wire0[7:0];
+
+	add32_add_sub_nq7	add32_add_sub_nq7_component (
+				.dataa (dataa),
+				.datab (datab),
+				.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "8"
+// Retrieval info: PRIVATE: Function NUMERIC "0"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
+// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
+// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
+// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

fpga/usrp1/megacells/add32_bb.v

@@ -0,0 +1,31 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module add32 (
+	dataa,
+	datab,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[7:0]  dataa;
+	input	[7:0]  datab;
+	output	[7:0]  result;
+
+endmodule
+

fpga/usrp1/megacells/add32_inst.v

@@ -0,0 +1,5 @@
+add32	add32_inst (
+	.dataa ( dataa_sig ),
+	.datab ( datab_sig ),
+	.result ( result_sig )
+	);

fpga/usrp1/megacells/addsub16.bsf

@@ -0,0 +1,96 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+support information,  device programming or simulation file,  and any other
+associated  documentation or information  provided by  Altera  or a partner
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+other  use  of such  megafunction  design,  netlist,  support  information,
+device programming or simulation file,  or any other  related documentation
+or information  is prohibited  for  any  other purpose,  including, but not
+limited to  modification,  reverse engineering,  de-compiling, or use  with
+any other  silicon devices,  unless such use is  explicitly  licensed under
+a separate agreement with  Altera  or a megafunction partner.  Title to the
+intellectual property,  including patents,  copyrights,  trademarks,  trade
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+support  information,  device programming or simulation file,  or any other
+related documentation or information provided by  Altera  or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 144)
+	(text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 125 31 140)(font "Arial" ))
+	(port
+		(pt 0 56)
+		(input)
+		(text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 1))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8)))
+		(text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 80 32)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 74 112)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 85 128)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 96 72)(line_width 3))
+	)
+	(drawing
+		(text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
+		(text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
+		(text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
+		(line (pt 64 48)(pt 96 56)(line_width 1))
+		(line (pt 96 56)(pt 96 88)(line_width 1))
+		(line (pt 96 88)(pt 64 96)(line_width 1))
+		(line (pt 64 96)(pt 64 48)(line_width 1))
+		(line (pt 80 32)(pt 80 52)(line_width 1))
+		(line (pt 106 40)(pt 125 40)(line_width 1))
+		(line (pt 74 112)(pt 74 93)(line_width 1))
+		(line (pt 85 128)(pt 85 90)(line_width 1))
+		(line (pt 64 66)(pt 70 72)(line_width 1))
+		(line (pt 70 72)(pt 64 78)(line_width 1))
+	)
+)

fpga/usrp1/megacells/addsub16.cmp

@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component addsub16
+	PORT
+	(
+		add_sub		: IN STD_LOGIC ;
+		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		aclr		: IN STD_LOGIC ;
+		clken		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/addsub16.inc

@@ -0,0 +1,34 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION addsub16 
+(
+	add_sub,
+	dataa[15..0],
+	datab[15..0],
+	clock,
+	aclr,
+	clken
+)
+
+RETURNS (
+	result[15..0]
+);

fpga/usrp1/megacells/addsub16.v

@@ -0,0 +1,438 @@
+// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: addsub16.v
+// Megafunction Name(s):
+// 			lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 17 
+module  addsub16_add_sub_gp9
+	( 
+	aclr,
+	add_sub,
+	clken,
+	clock,
+	dataa,
+	datab,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   aclr;
+	input   add_sub;
+	input   clken;
+	input   clock;
+	input   [15:0]  dataa;
+	input   [15:0]  datab;
+	output   [15:0]  result;
+
+	wire  [0:0]   wire_add_sub_cella_0cout;
+	wire  [0:0]   wire_add_sub_cella_1cout;
+	wire  [0:0]   wire_add_sub_cella_2cout;
+	wire  [0:0]   wire_add_sub_cella_3cout;
+	wire  [0:0]   wire_add_sub_cella_4cout;
+	wire  [0:0]   wire_add_sub_cella_5cout;
+	wire  [0:0]   wire_add_sub_cella_6cout;
+	wire  [0:0]   wire_add_sub_cella_7cout;
+	wire  [0:0]   wire_add_sub_cella_8cout;
+	wire  [0:0]   wire_add_sub_cella_9cout;
+	wire  [0:0]   wire_add_sub_cella_10cout;
+	wire  [0:0]   wire_add_sub_cella_11cout;
+	wire  [0:0]   wire_add_sub_cella_12cout;
+	wire  [0:0]   wire_add_sub_cella_13cout;
+	wire  [0:0]   wire_add_sub_cella_14cout;
+	wire  [15:0]   wire_add_sub_cella_dataa;
+	wire  [15:0]   wire_add_sub_cella_datab;
+	wire  [15:0]   wire_add_sub_cella_regout;
+	wire  wire_strx_lcell1_cout;
+
+	stratix_lcell   add_sub_cella_0
+	( 
+	.aclr(aclr),
+	.cin(wire_strx_lcell1_cout),
+	.clk(clock),
+	.cout(wire_add_sub_cella_0cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[0:0]),
+	.datab(wire_add_sub_cella_datab[0:0]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[0:0]));
+	defparam
+		add_sub_cella_0.cin_used = "true",
+		add_sub_cella_0.lut_mask = "96e8",
+		add_sub_cella_0.operation_mode = "arithmetic",
+		add_sub_cella_0.sum_lutc_input = "cin",
+		add_sub_cella_0.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_1
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_0cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_1cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[1:1]),
+	.datab(wire_add_sub_cella_datab[1:1]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[1:1]));
+	defparam
+		add_sub_cella_1.cin_used = "true",
+		add_sub_cella_1.lut_mask = "96e8",
+		add_sub_cella_1.operation_mode = "arithmetic",
+		add_sub_cella_1.sum_lutc_input = "cin",
+		add_sub_cella_1.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_2
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_1cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_2cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[2:2]),
+	.datab(wire_add_sub_cella_datab[2:2]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[2:2]));
+	defparam
+		add_sub_cella_2.cin_used = "true",
+		add_sub_cella_2.lut_mask = "96e8",
+		add_sub_cella_2.operation_mode = "arithmetic",
+		add_sub_cella_2.sum_lutc_input = "cin",
+		add_sub_cella_2.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_3
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_2cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_3cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[3:3]),
+	.datab(wire_add_sub_cella_datab[3:3]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[3:3]));
+	defparam
+		add_sub_cella_3.cin_used = "true",
+		add_sub_cella_3.lut_mask = "96e8",
+		add_sub_cella_3.operation_mode = "arithmetic",
+		add_sub_cella_3.sum_lutc_input = "cin",
+		add_sub_cella_3.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_4
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_3cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_4cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[4:4]),
+	.datab(wire_add_sub_cella_datab[4:4]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[4:4]));
+	defparam
+		add_sub_cella_4.cin_used = "true",
+		add_sub_cella_4.lut_mask = "96e8",
+		add_sub_cella_4.operation_mode = "arithmetic",
+		add_sub_cella_4.sum_lutc_input = "cin",
+		add_sub_cella_4.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_5
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_4cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_5cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[5:5]),
+	.datab(wire_add_sub_cella_datab[5:5]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[5:5]));
+	defparam
+		add_sub_cella_5.cin_used = "true",
+		add_sub_cella_5.lut_mask = "96e8",
+		add_sub_cella_5.operation_mode = "arithmetic",
+		add_sub_cella_5.sum_lutc_input = "cin",
+		add_sub_cella_5.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_6
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_5cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_6cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[6:6]),
+	.datab(wire_add_sub_cella_datab[6:6]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[6:6]));
+	defparam
+		add_sub_cella_6.cin_used = "true",
+		add_sub_cella_6.lut_mask = "96e8",
+		add_sub_cella_6.operation_mode = "arithmetic",
+		add_sub_cella_6.sum_lutc_input = "cin",
+		add_sub_cella_6.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_7
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_6cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_7cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[7:7]),
+	.datab(wire_add_sub_cella_datab[7:7]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[7:7]));
+	defparam
+		add_sub_cella_7.cin_used = "true",
+		add_sub_cella_7.lut_mask = "96e8",
+		add_sub_cella_7.operation_mode = "arithmetic",
+		add_sub_cella_7.sum_lutc_input = "cin",
+		add_sub_cella_7.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_8
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_7cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_8cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[8:8]),
+	.datab(wire_add_sub_cella_datab[8:8]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[8:8]));
+	defparam
+		add_sub_cella_8.cin_used = "true",
+		add_sub_cella_8.lut_mask = "96e8",
+		add_sub_cella_8.operation_mode = "arithmetic",
+		add_sub_cella_8.sum_lutc_input = "cin",
+		add_sub_cella_8.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_9
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_8cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_9cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[9:9]),
+	.datab(wire_add_sub_cella_datab[9:9]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[9:9]));
+	defparam
+		add_sub_cella_9.cin_used = "true",
+		add_sub_cella_9.lut_mask = "96e8",
+		add_sub_cella_9.operation_mode = "arithmetic",
+		add_sub_cella_9.sum_lutc_input = "cin",
+		add_sub_cella_9.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_10
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_9cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_10cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[10:10]),
+	.datab(wire_add_sub_cella_datab[10:10]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[10:10]));
+	defparam
+		add_sub_cella_10.cin_used = "true",
+		add_sub_cella_10.lut_mask = "96e8",
+		add_sub_cella_10.operation_mode = "arithmetic",
+		add_sub_cella_10.sum_lutc_input = "cin",
+		add_sub_cella_10.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_11
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_10cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_11cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[11:11]),
+	.datab(wire_add_sub_cella_datab[11:11]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[11:11]));
+	defparam
+		add_sub_cella_11.cin_used = "true",
+		add_sub_cella_11.lut_mask = "96e8",
+		add_sub_cella_11.operation_mode = "arithmetic",
+		add_sub_cella_11.sum_lutc_input = "cin",
+		add_sub_cella_11.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_12
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_11cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_12cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[12:12]),
+	.datab(wire_add_sub_cella_datab[12:12]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[12:12]));
+	defparam
+		add_sub_cella_12.cin_used = "true",
+		add_sub_cella_12.lut_mask = "96e8",
+		add_sub_cella_12.operation_mode = "arithmetic",
+		add_sub_cella_12.sum_lutc_input = "cin",
+		add_sub_cella_12.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_13
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_12cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_13cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[13:13]),
+	.datab(wire_add_sub_cella_datab[13:13]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[13:13]));
+	defparam
+		add_sub_cella_13.cin_used = "true",
+		add_sub_cella_13.lut_mask = "96e8",
+		add_sub_cella_13.operation_mode = "arithmetic",
+		add_sub_cella_13.sum_lutc_input = "cin",
+		add_sub_cella_13.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_14
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_13cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_14cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[14:14]),
+	.datab(wire_add_sub_cella_datab[14:14]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[14:14]));
+	defparam
+		add_sub_cella_14.cin_used = "true",
+		add_sub_cella_14.lut_mask = "96e8",
+		add_sub_cella_14.operation_mode = "arithmetic",
+		add_sub_cella_14.sum_lutc_input = "cin",
+		add_sub_cella_14.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_15
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_14cout[0:0]),
+	.clk(clock),
+	.dataa(wire_add_sub_cella_dataa[15:15]),
+	.datab(wire_add_sub_cella_datab[15:15]),
+	.ena(clken),
+	.inverta((~ add_sub)),
+	.regout(wire_add_sub_cella_regout[15:15]));
+	defparam
+		add_sub_cella_15.cin_used = "true",
+		add_sub_cella_15.lut_mask = "9696",
+		add_sub_cella_15.operation_mode = "normal",
+		add_sub_cella_15.sum_lutc_input = "cin",
+		add_sub_cella_15.lpm_type = "stratix_lcell";
+	assign
+		wire_add_sub_cella_dataa = datab,
+		wire_add_sub_cella_datab = dataa;
+	stratix_lcell   strx_lcell1
+	( 
+	.cout(wire_strx_lcell1_cout),
+	.dataa(1'b0),
+	.datab((~ add_sub)),
+	.inverta((~ add_sub)));
+	defparam
+		strx_lcell1.cin_used = "false",
+		strx_lcell1.lut_mask = "00cc",
+		strx_lcell1.operation_mode = "arithmetic",
+		strx_lcell1.lpm_type = "stratix_lcell";
+	assign
+		result = wire_add_sub_cella_regout;
+endmodule //addsub16_add_sub_gp9
+//VALID FILE
+
+
+module addsub16 (
+	add_sub,
+	dataa,
+	datab,
+	clock,
+	aclr,
+	clken,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	  add_sub;
+	input	[15:0]  dataa;
+	input	[15:0]  datab;
+	input	  clock;
+	input	  aclr;
+	input	  clken;
+	output	[15:0]  result;
+
+	wire [15:0] sub_wire0;
+	wire [15:0] result = sub_wire0[15:0];
+
+	addsub16_add_sub_gp9	addsub16_add_sub_gp9_component (
+				.dataa (dataa),
+				.add_sub (add_sub),
+				.datab (datab),
+				.clken (clken),
+				.aclr (aclr),
+				.clock (clock),
+				.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "16"
+// Retrieval info: PRIVATE: Function NUMERIC "2"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: aclr NUMERIC "1"
+// Retrieval info: PRIVATE: clken NUMERIC "1"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
+// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
+// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
+// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
+// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

fpga/usrp1/megacells/addsub16_bb.v

@@ -0,0 +1,39 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module addsub16 (
+	add_sub,
+	dataa,
+	datab,
+	clock,
+	aclr,
+	clken,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	  add_sub;
+	input	[15:0]  dataa;
+	input	[15:0]  datab;
+	input	  clock;
+	input	  aclr;
+	input	  clken;
+	output	[15:0]  result;
+
+endmodule
+

fpga/usrp1/megacells/addsub16_inst.v

@@ -0,0 +1,9 @@
+addsub16	addsub16_inst (
+	.add_sub ( add_sub_sig ),
+	.dataa ( dataa_sig ),
+	.datab ( datab_sig ),
+	.clock ( clock_sig ),
+	.aclr ( aclr_sig ),
+	.clken ( clken_sig ),
+	.result ( result_sig )
+	);

fpga/usrp1/megacells/bustri.bsf

@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+support information,  device programming or simulation file,  and any other
+associated  documentation or information  provided by  Altera  or a partner
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+other  use  of such  megafunction  design,  netlist,  support  information,
+device programming or simulation file,  or any other  related documentation
+or information  is prohibited  for  any  other purpose,  including, but not
+limited to  modification,  reverse engineering,  de-compiling, or use  with
+any other  silicon devices,  unless such use is  explicitly  licensed under
+a separate agreement with  Altera  or a megafunction partner.  Title to the
+intellectual property,  including patents,  copyrights,  trademarks,  trade
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+support  information,  device programming or simulation file,  or any other
+related documentation or information provided by  Altera  or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "16" (rect 61 25 71 37)(font "Arial" ))
+		(text "16" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)

fpga/usrp1/megacells/bustri.cmp

@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component bustri
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/bustri.inc

@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION bustri 
+(
+	data[15..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[15..0]
+);

fpga/usrp1/megacells/bustri.v

@@ -0,0 +1,71 @@
+// megafunction wizard: %LPM_BUSTRI%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_bustri 
+
+// ============================================================
+// File Name: bustri.v
+// Megafunction Name(s):
+// 			lpm_bustri
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module bustri (
+	data,
+	enabledt,
+	tridata);
+
+	input	[15:0]  data;
+	input	  enabledt;
+	inout	[15:0]  tridata;
+
+
+	lpm_bustri	lpm_bustri_component (
+				.tridata (tridata),
+				.enabledt (enabledt),
+				.data (data));
+	defparam
+		lpm_bustri_component.lpm_width = 16,
+		lpm_bustri_component.lpm_type = "LPM_BUSTRI";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "16"
+// Retrieval info: PRIVATE: BiDir NUMERIC "0"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

fpga/usrp1/megacells/bustri_bb.v

@@ -0,0 +1,31 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module bustri (
+	data,
+	enabledt,
+	tridata);
+
+	input	[15:0]  data;
+	input	  enabledt;
+	inout	[15:0]  tridata;
+
+endmodule
+

fpga/usrp1/megacells/bustri_inst.v

@@ -0,0 +1,5 @@
+bustri	bustri_inst (
+	.data ( data_sig ),
+	.enabledt ( enabledt_sig ),
+	.tridata ( tridata_sig )
+	);

fpga/usrp1/megacells/clk_doubler.v

@@ -0,0 +1,198 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: clk_doubler.v
+// Megafunction Name(s):
+// 			altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.2 Build 156 11/29/2004 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module clk_doubler (
+	inclk0,
+	c0);
+
+	input	  inclk0;
+	output	  c0;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire4 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  sub_wire2 = inclk0;
+	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+	altpll	altpll_component (
+				.inclk (sub_wire3),
+				.clk (sub_wire0)
+				// synopsys translate_off
+				,
+				.activeclock (),
+				.areset (),
+				.clkbad (),
+				.clkena (),
+				.clkloss (),
+				.clkswitch (),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena (),
+				.fbin (),
+				.locked (),
+				.pfdena (),
+				.pllena (),
+				.scanaclr (),
+				.scanclk (),
+				.scandata (),
+				.scandataout (),
+				.scandone (),
+				.scanread (),
+				.scanwrite (),
+				.sclkout0 (),
+				.sclkout1 ()
+				// synopsys translate_on
+				);
+	defparam
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.lpm_type = "altpll",
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.inclk0_input_frequency = 15625,
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.pll_type = "AUTO",
+		altpll_component.intended_device_family = "Cyclone",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.clk0_phase_shift = "0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE

fpga/usrp1/megacells/clk_doubler_bb.v

@@ -0,0 +1,143 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: clk_doubler.v
+// Megafunction Name(s):
+// 			altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.2 Build 156 11/29/2004 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module clk_doubler (
+	inclk0,
+	c0);
+
+	input	  inclk0;
+	output	  c0;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE

fpga/usrp1/megacells/dspclkpll.v

@@ -0,0 +1,237 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: dspclkpll.v
+// Megafunction Name(s):
+// 			altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dspclkpll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0)
+				// synopsys translate_off
+,
+				.fbin (),
+				.pllena (),
+				.clkswitch (),
+				.areset (),
+				.pfdena (),
+				.clkena (),
+				.extclkena (),
+				.scanclk (),
+				.scanaclr (),
+				.scandata (),
+				.scanread (),
+				.scanwrite (),
+				.extclk (),
+				.clkbad (),
+				.activeclock (),
+				.locked (),
+				.clkloss (),
+				.scandataout (),
+				.scandone (),
+				.sclkout1 (),
+				.sclkout0 (),
+				.enable0 (),
+				.enable1 ()
+				// synopsys translate_on
+
+);
+	defparam
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.lpm_type = "altpll",
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.inclk0_input_frequency = 15625,
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.pll_type = "AUTO",
+		altpll_component.clk1_multiply_by = 2,
+		altpll_component.clk0_time_delay = "0",
+		altpll_component.intended_device_family = "Cyclone",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.clk1_time_delay = "0",
+		altpll_component.clk0_phase_shift = "0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE

fpga/usrp1/megacells/dspclkpll_bb.v

@@ -0,0 +1,31 @@
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module dspclkpll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+endmodule
+

fpga/usrp1/megacells/fifo_1kx16.bsf

@@ -0,0 +1,107 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 160)
+	(text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 144 25 156)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(port
+		(pt 160 56)
+		(output)
+		(text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
+		(line (pt 160 56)(pt 144 56)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 144 72)(line_width 1))
+	)
+	(port
+		(pt 160 88)
+		(output)
+		(text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8)))
+		(line (pt 160 88)(pt 144 88)(line_width 1))
+	)
+	(port
+		(pt 160 104)
+		(output)
+		(text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8)))
+		(text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8)))
+		(line (pt 160 104)(pt 144 104)(line_width 3))
+	)
+	(drawing
+		(text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" ))
+		(text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 144)(line_width 1))
+		(line (pt 144 144)(pt 16 144)(line_width 1))
+		(line (pt 16 144)(pt 16 16)(line_width 1))
+		(line (pt 16 116)(pt 144 116)(line_width 1))
+		(line (pt 16 90)(pt 22 96)(line_width 1))
+		(line (pt 22 96)(pt 16 102)(line_width 1))
+	)
+)

fpga/usrp1/megacells/fifo_1kx16.cmp

@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component fifo_1kx16
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		rdreq		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		almost_empty		: OUT STD_LOGIC ;
+		empty		: OUT STD_LOGIC ;
+		full		: OUT STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+		usedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/fifo_1kx16.inc

@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION fifo_1kx16 
+(
+	aclr,
+	clock,
+	data[15..0],
+	rdreq,
+	wrreq
+)
+
+RETURNS (
+	almost_empty,
+	empty,
+	full,
+	q[15..0],
+	usedw[9..0]
+);

fpga/usrp1/megacells/fifo_1kx16.v

@@ -0,0 +1,175 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: fifo_1kx16.v
+// Megafunction Name(s):
+// 			scfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_1kx16 (
+	aclr,
+	clock,
+	data,
+	rdreq,
+	wrreq,
+	almost_empty,
+	empty,
+	full,
+	q,
+	usedw);
+
+	input	  aclr;
+	input	  clock;
+	input	[15:0]  data;
+	input	  rdreq;
+	input	  wrreq;
+	output	  almost_empty;
+	output	  empty;
+	output	  full;
+	output	[15:0]  q;
+	output	[9:0]  usedw;
+
+	wire [9:0] sub_wire0;
+	wire  sub_wire1;
+	wire  sub_wire2;
+	wire [15:0] sub_wire3;
+	wire  sub_wire4;
+	wire [9:0] usedw = sub_wire0[9:0];
+	wire  empty = sub_wire1;
+	wire  almost_empty = sub_wire2;
+	wire [15:0] q = sub_wire3[15:0];
+	wire  full = sub_wire4;
+
+	scfifo	scfifo_component (
+				.rdreq (rdreq),
+				.aclr (aclr),
+				.clock (clock),
+				.wrreq (wrreq),
+				.data (data),
+				.usedw (sub_wire0),
+				.empty (sub_wire1),
+				.almost_empty (sub_wire2),
+				.q (sub_wire3),
+				.full (sub_wire4)
+				// synopsys translate_off
+				,
+				.sclr (),
+				.almost_full ()
+				// synopsys translate_on
+				);
+	defparam
+		scfifo_component.add_ram_output_register = "OFF",
+		scfifo_component.almost_empty_value = 504,
+		scfifo_component.intended_device_family = "Cyclone",
+		scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		scfifo_component.lpm_numwords = 1024,
+		scfifo_component.lpm_showahead = "OFF",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 16,
+		scfifo_component.lpm_widthu = 10,
+		scfifo_component.overflow_checking = "ON",
+		scfifo_component.underflow_checking = "ON",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE

fpga/usrp1/megacells/fifo_1kx16_bb.v

@@ -0,0 +1,127 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: fifo_1kx16.v
+// Megafunction Name(s):
+// 			scfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module fifo_1kx16 (
+	aclr,
+	clock,
+	data,
+	rdreq,
+	wrreq,
+	almost_empty,
+	empty,
+	full,
+	q,
+	usedw);
+
+	input	  aclr;
+	input	  clock;
+	input	[15:0]  data;
+	input	  rdreq;
+	input	  wrreq;
+	output	  almost_empty;
+	output	  empty;
+	output	  full;
+	output	[15:0]  q;
+	output	[9:0]  usedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE

fpga/usrp1/megacells/fifo_1kx16_inst.v

@@ -0,0 +1,12 @@
+fifo_1kx16	fifo_1kx16_inst (
+	.aclr ( aclr_sig ),
+	.clock ( clock_sig ),
+	.data ( data_sig ),
+	.rdreq ( rdreq_sig ),
+	.wrreq ( wrreq_sig ),
+	.almost_empty ( almost_empty_sig ),
+	.empty ( empty_sig ),
+	.full ( full_sig ),
+	.q ( q_sig ),
+	.usedw ( usedw_sig )
+	);

fpga/usrp1/megacells/fifo_2k_bb.v

@@ -0,0 +1,131 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_2k.v
+// Megafunction Name(s):
+// 			dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+module fifo_2k (
+	data,
+	wrreq,
+	rdreq,
+	rdclk,
+	wrclk,
+	aclr,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[15:0]  data;
+	input	  wrreq;
+	input	  rdreq;
+	input	  rdclk;
+	input	  wrclk;
+	input	  aclr;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[10:0]  rdusedw;
+	output	  wrfull;
+	output	[10:0]  wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "2048"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE

fpga/usrp1/megacells/fifo_4k_18.v

@@ -0,0 +1,186 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4k_18.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_4k_18 (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[17:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[17:0]  q;
+	output	  rdempty;
+	output	[11:0]  rdusedw;
+	output	  wrfull;
+	output	[11:0]  wrusedw;
+
+	wire  sub_wire0;
+	wire [11:0] sub_wire1;
+	wire  sub_wire2;
+	wire [17:0] sub_wire3;
+	wire [11:0] sub_wire4;
+	wire  rdempty = sub_wire0;
+	wire [11:0] wrusedw = sub_wire1[11:0];
+	wire  wrfull = sub_wire2;
+	wire [17:0] q = sub_wire3[17:0];
+	wire [11:0] rdusedw = sub_wire4[11:0];
+
+	dcfifo	dcfifo_component (
+				.wrclk (wrclk),
+				.rdreq (rdreq),
+				.aclr (aclr),
+				.rdclk (rdclk),
+				.wrreq (wrreq),
+				.data (data),
+				.rdempty (sub_wire0),
+				.wrusedw (sub_wire1),
+				.wrfull (sub_wire2),
+				.q (sub_wire3),
+				.rdusedw (sub_wire4)
+				// synopsys translate_off
+				,
+				.rdfull (),
+				.wrempty ()
+				// synopsys translate_on
+				);
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_numwords = 4096,
+		dcfifo_component.lpm_showahead = "ON",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 18,
+		dcfifo_component.lpm_widthu = 12,
+		dcfifo_component.overflow_checking = "OFF",
+		dcfifo_component.underflow_checking = "OFF",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "18"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "18"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
+// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
+// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf

fpga/usrp1/megacells/fifo_4k_bb.v

@@ -0,0 +1,131 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4k.v
+// Megafunction Name(s):
+// 			dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+module fifo_4k (
+	data,
+	wrreq,
+	rdreq,
+	rdclk,
+	wrclk,
+	aclr,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[15:0]  data;
+	input	  wrreq;
+	input	  rdreq;
+	input	  rdclk;
+	input	  wrclk;
+	input	  aclr;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[11:0]  rdusedw;
+	output	  wrfull;
+	output	[11:0]  wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE

fpga/usrp1/megacells/fifo_4kx16_dc.bsf

@@ -0,0 +1,117 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 184)
+	(text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 16 160)(line_width 1))
+	)
+	(port
+		(pt 160 40)
+		(output)
+		(text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+		(text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
+		(line (pt 160 40)(pt 144 40)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(port
+		(pt 160 120)
+		(output)
+		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+		(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
+		(line (pt 160 120)(pt 144 120)(line_width 1))
+	)
+	(port
+		(pt 160 136)
+		(output)
+		(text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
+		(text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8)))
+		(line (pt 160 136)(pt 144 136)(line_width 3))
+	)
+	(drawing
+		(text "(ack)" (rect 51 99 72 111)(font "Arial" ))
+		(text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 168)(line_width 1))
+		(line (pt 144 168)(pt 16 168)(line_width 1))
+		(line (pt 16 168)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 148)(pt 144 148)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)

fpga/usrp1/megacells/fifo_4kx16_dc.cmp

@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component fifo_4kx16_dc
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		rdusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+		wrfull		: OUT STD_LOGIC ;
+		wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/fifo_4kx16_dc.inc

@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION fifo_4kx16_dc 
+(
+	aclr,
+	data[15..0],
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq
+)
+
+RETURNS (
+	q[15..0],
+	rdempty,
+	rdusedw[11..0],
+	wrfull,
+	wrusedw[11..0]
+);

fpga/usrp1/megacells/fifo_4kx16_dc.v

@@ -0,0 +1,178 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4kx16_dc.v
+// Megafunction Name(s):
+// 			dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_4kx16_dc (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[11:0]  rdusedw;
+	output	  wrfull;
+	output	[11:0]  wrusedw;
+
+	wire  sub_wire0;
+	wire [11:0] sub_wire1;
+	wire  sub_wire2;
+	wire [15:0] sub_wire3;
+	wire [11:0] sub_wire4;
+	wire  rdempty = sub_wire0;
+	wire [11:0] wrusedw = sub_wire1[11:0];
+	wire  wrfull = sub_wire2;
+	wire [15:0] q = sub_wire3[15:0];
+	wire [11:0] rdusedw = sub_wire4[11:0];
+
+	dcfifo	dcfifo_component (
+				.wrclk (wrclk),
+				.rdreq (rdreq),
+				.aclr (aclr),
+				.rdclk (rdclk),
+				.wrreq (wrreq),
+				.data (data),
+				.rdempty (sub_wire0),
+				.wrusedw (sub_wire1),
+				.wrfull (sub_wire2),
+				.q (sub_wire3),
+				.rdusedw (sub_wire4)
+				// synopsys translate_off
+				,
+				.wrempty (),
+				.rdfull ()
+				// synopsys translate_on
+				);
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_numwords = 4096,
+		dcfifo_component.lpm_showahead = "ON",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 12,
+		dcfifo_component.overflow_checking = "OFF",
+		dcfifo_component.underflow_checking = "OFF",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE

fpga/usrp1/megacells/fifo_4kx16_dc_bb.v

@@ -0,0 +1,130 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4kx16_dc.v
+// Megafunction Name(s):
+// 			dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module fifo_4kx16_dc (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[11:0]  rdusedw;
+	output	  wrfull;
+	output	[11:0]  wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE

fpga/usrp1/megacells/fifo_4kx16_dc_inst.v

@@ -0,0 +1,13 @@
+fifo_4kx16_dc	fifo_4kx16_dc_inst (
+	.aclr ( aclr_sig ),
+	.data ( data_sig ),
+	.rdclk ( rdclk_sig ),
+	.rdreq ( rdreq_sig ),
+	.wrclk ( wrclk_sig ),
+	.wrreq ( wrreq_sig ),
+	.q ( q_sig ),
+	.rdempty ( rdempty_sig ),
+	.rdusedw ( rdusedw_sig ),
+	.wrfull ( wrfull_sig ),
+	.wrusedw ( wrusedw_sig )
+	);

fpga/usrp1/megacells/mylpm_addsub.bsf

@@ -0,0 +1,80 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+support information,  device programming or simulation file,  and any other
+associated  documentation or information  provided by  Altera  or a partner
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+other  use  of such  megafunction  design,  netlist,  support  information,
+device programming or simulation file,  or any other  related documentation
+or information  is prohibited  for  any  other purpose,  including, but not
+limited to  modification,  reverse engineering,  de-compiling, or use  with
+any other  silicon devices,  unless such use is  explicitly  licensed under
+a separate agreement with  Altera  or a megafunction partner.  Title to the
+intellectual property,  including patents,  copyrights,  trademarks,  trade
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+support  information,  device programming or simulation file,  or any other
+related documentation or information provided by  Altera  or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 112)
+	(text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 93 30 108)(font "Arial" ))
+	(port
+		(pt 0 56)
+		(input)
+		(text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+		(text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+		(text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 1))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 80 32)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 96 72)(line_width 3))
+	)
+	(drawing
+		(text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
+		(text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
+		(text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
+		(line (pt 64 48)(pt 96 56)(line_width 1))
+		(line (pt 96 56)(pt 96 88)(line_width 1))
+		(line (pt 96 88)(pt 64 96)(line_width 1))
+		(line (pt 64 96)(pt 64 48)(line_width 1))
+		(line (pt 80 32)(pt 80 52)(line_width 1))
+		(line (pt 106 40)(pt 125 40)(line_width 1))
+		(line (pt 64 66)(pt 70 72)(line_width 1))
+		(line (pt 70 72)(pt 64 78)(line_width 1))
+	)
+)

fpga/usrp1/megacells/mylpm_addsub.cmp

@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component mylpm_addsub
+	PORT
+	(
+		add_sub		: IN STD_LOGIC ;
+		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/mylpm_addsub.inc

@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION mylpm_addsub 
+(
+	add_sub,
+	dataa[15..0],
+	datab[15..0],
+	clock
+)
+
+RETURNS (
+	result[15..0]
+);

fpga/usrp1/megacells/mylpm_addsub.v

@@ -0,0 +1,102 @@
+// megafunction wizard: %LPM_ADD_SUB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: mylpm_addsub.v
+// Megafunction Name(s):
+// 			lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module mylpm_addsub (
+	add_sub,
+	dataa,
+	datab,
+	clock,
+	result);
+
+	input	  add_sub;
+	input	[15:0]  dataa;
+	input	[15:0]  datab;
+	input	  clock;
+	output	[15:0]  result;
+
+	wire [15:0] sub_wire0;
+	wire [15:0] result = sub_wire0[15:0];
+
+	lpm_add_sub	lpm_add_sub_component (
+				.dataa (dataa),
+				.add_sub (add_sub),
+				.datab (datab),
+				.clock (clock),
+				.result (sub_wire0));
+	defparam
+		lpm_add_sub_component.lpm_width = 16,
+		lpm_add_sub_component.lpm_direction = "UNUSED",
+		lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
+		lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
+		lpm_add_sub_component.lpm_pipeline = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "16"
+// Retrieval info: PRIVATE: Function NUMERIC "2"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
+// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
+// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
+// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

fpga/usrp1/megacells/mylpm_addsub_bb.v

@@ -0,0 +1,35 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module mylpm_addsub (
+	add_sub,
+	dataa,
+	datab,
+	clock,
+	result);
+
+	input	  add_sub;
+	input	[15:0]  dataa;
+	input	[15:0]  datab;
+	input	  clock;
+	output	[15:0]  result;
+
+endmodule
+

fpga/usrp1/megacells/mylpm_addsub_inst.v

@@ -0,0 +1,7 @@
+mylpm_addsub	mylpm_addsub_inst (
+	.add_sub ( add_sub_sig ),
+	.dataa ( dataa_sig ),
+	.datab ( datab_sig ),
+	.clock ( clock_sig ),
+	.result ( result_sig )
+	);

fpga/usrp1/megacells/pll.v

@@ -0,0 +1,207 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0);
+
+	input	  inclk0;
+	output	  c0;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire4 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  sub_wire2 = inclk0;
+	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+	altpll	altpll_component (
+				.inclk (sub_wire3),
+				.clk (sub_wire0)
+				// synopsys translate_off
+,
+				.fbin (),
+				.pllena (),
+				.clkswitch (),
+				.areset (),
+				.pfdena (),
+				.clkena (),
+				.extclkena (),
+				.scanclk (),
+				.scanaclr (),
+				.scandata (),
+				.scanread (),
+				.scanwrite (),
+				.extclk (),
+				.clkbad (),
+				.activeclock (),
+				.locked (),
+				.clkloss (),
+				.scandataout (),
+				.scandone (),
+				.sclkout1 (),
+				.sclkout0 (),
+				.enable0 (),
+				.enable1 ()
+				// synopsys translate_on
+
+);
+	defparam
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.lpm_type = "altpll",
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.inclk0_input_frequency = 20833,
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.pll_type = "AUTO",
+		altpll_component.clk0_time_delay = "0",
+		altpll_component.intended_device_family = "Cyclone",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.clk0_phase_shift = "-3000";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE

fpga/usrp1/megacells/pll_bb.v

@@ -0,0 +1,29 @@
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module pll (
+	inclk0,
+	c0);
+
+	input	  inclk0;
+	output	  c0;
+
+endmodule
+

fpga/usrp1/megacells/pll_inst.v

@@ -0,0 +1,4 @@
+pll	pll_inst (
+	.inclk0 ( inclk0_sig ),
+	.c0 ( c0_sig )
+	);

fpga/usrp1/megacells/sub32.bsf

@@ -0,0 +1,87 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+support information,  device programming or simulation file,  and any other
+associated  documentation or information  provided by  Altera  or a partner
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+other  use  of such  megafunction  design,  netlist,  support  information,
+device programming or simulation file,  or any other  related documentation
+or information  is prohibited  for  any  other purpose,  including, but not
+limited to  modification,  reverse engineering,  de-compiling, or use  with
+any other  silicon devices,  unless such use is  explicitly  licensed under
+a separate agreement with  Altera  or a megafunction partner.  Title to the
+intellectual property,  including patents,  copyrights,  trademarks,  trade
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+support  information,  device programming or simulation file,  or any other
+related documentation or information provided by  Altera  or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 128)
+	(text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 109 31 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 74 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 85 112)(line_width 1))
+	)
+	(port
+		(pt 160 56)
+		(output)
+		(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8)))
+		(line (pt 160 56)(pt 96 56)(line_width 3))
+	)
+	(drawing
+		(text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
+		(text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
+		(text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8)))
+		(line (pt 64 32)(pt 96 40)(line_width 1))
+		(line (pt 96 40)(pt 96 72)(line_width 1))
+		(line (pt 96 72)(pt 64 80)(line_width 1))
+		(line (pt 64 80)(pt 64 32)(line_width 1))
+		(line (pt 74 96)(pt 74 77)(line_width 1))
+		(line (pt 85 112)(pt 85 74)(line_width 1))
+		(line (pt 64 50)(pt 70 56)(line_width 1))
+		(line (pt 70 56)(pt 64 62)(line_width 1))
+	)
+)

fpga/usrp1/megacells/sub32.cmp

@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component sub32
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		aclr		: IN STD_LOGIC ;
+		clken		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;

fpga/usrp1/megacells/sub32.inc

@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION sub32 
+(
+	dataa[31..0],
+	datab[31..0],
+	clock,
+	aclr,
+	clken
+)
+
+RETURNS (
+	result[31..0]
+);

fpga/usrp1/megacells/sub32.v

@@ -0,0 +1,675 @@
+// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: sub32.v
+// Megafunction Name(s):
+// 			lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 32 
+module  sub32_add_sub_cqa
+	( 
+	aclr,
+	clken,
+	clock,
+	dataa,
+	datab,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   aclr;
+	input   clken;
+	input   clock;
+	input   [31:0]  dataa;
+	input   [31:0]  datab;
+	output   [31:0]  result;
+
+	wire  [0:0]   wire_add_sub_cella_0cout;
+	wire  [0:0]   wire_add_sub_cella_1cout;
+	wire  [0:0]   wire_add_sub_cella_2cout;
+	wire  [0:0]   wire_add_sub_cella_3cout;
+	wire  [0:0]   wire_add_sub_cella_4cout;
+	wire  [0:0]   wire_add_sub_cella_5cout;
+	wire  [0:0]   wire_add_sub_cella_6cout;
+	wire  [0:0]   wire_add_sub_cella_7cout;
+	wire  [0:0]   wire_add_sub_cella_8cout;
+	wire  [0:0]   wire_add_sub_cella_9cout;
+	wire  [0:0]   wire_add_sub_cella_10cout;
+	wire  [0:0]   wire_add_sub_cella_11cout;
+	wire  [0:0]   wire_add_sub_cella_12cout;
+	wire  [0:0]   wire_add_sub_cella_13cout;
+	wire  [0:0]   wire_add_sub_cella_14cout;
+	wire  [0:0]   wire_add_sub_cella_15cout;
+	wire  [0:0]   wire_add_sub_cella_16cout;
+	wire  [0:0]   wire_add_sub_cella_17cout;
+	wire  [0:0]   wire_add_sub_cella_18cout;
+	wire  [0:0]   wire_add_sub_cella_19cout;
+	wire  [0:0]   wire_add_sub_cella_20cout;
+	wire  [0:0]   wire_add_sub_cella_21cout;
+	wire  [0:0]   wire_add_sub_cella_22cout;
+	wire  [0:0]   wire_add_sub_cella_23cout;
+	wire  [0:0]   wire_add_sub_cella_24cout;
+	wire  [0:0]   wire_add_sub_cella_25cout;
+	wire  [0:0]   wire_add_sub_cella_26cout;
+	wire  [0:0]   wire_add_sub_cella_27cout;
+	wire  [0:0]   wire_add_sub_cella_28cout;
+	wire  [0:0]   wire_add_sub_cella_29cout;
+	wire  [0:0]   wire_add_sub_cella_30cout;
+	wire  [31:0]   wire_add_sub_cella_dataa;
+	wire  [31:0]   wire_add_sub_cella_datab;
+	wire  [31:0]   wire_add_sub_cella_regout;
+
+	stratix_lcell   add_sub_cella_0
+	( 
+	.aclr(aclr),
+	.cin(1'b1),
+	.clk(clock),
+	.cout(wire_add_sub_cella_0cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[0:0]),
+	.datab(wire_add_sub_cella_datab[0:0]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[0:0]));
+	defparam
+		add_sub_cella_0.cin_used = "true",
+		add_sub_cella_0.lut_mask = "69b2",
+		add_sub_cella_0.operation_mode = "arithmetic",
+		add_sub_cella_0.sum_lutc_input = "cin",
+		add_sub_cella_0.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_1
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_0cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_1cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[1:1]),
+	.datab(wire_add_sub_cella_datab[1:1]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[1:1]));
+	defparam
+		add_sub_cella_1.cin_used = "true",
+		add_sub_cella_1.lut_mask = "69b2",
+		add_sub_cella_1.operation_mode = "arithmetic",
+		add_sub_cella_1.sum_lutc_input = "cin",
+		add_sub_cella_1.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_2
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_1cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_2cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[2:2]),
+	.datab(wire_add_sub_cella_datab[2:2]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[2:2]));
+	defparam
+		add_sub_cella_2.cin_used = "true",
+		add_sub_cella_2.lut_mask = "69b2",
+		add_sub_cella_2.operation_mode = "arithmetic",
+		add_sub_cella_2.sum_lutc_input = "cin",
+		add_sub_cella_2.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_3
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_2cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_3cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[3:3]),
+	.datab(wire_add_sub_cella_datab[3:3]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[3:3]));
+	defparam
+		add_sub_cella_3.cin_used = "true",
+		add_sub_cella_3.lut_mask = "69b2",
+		add_sub_cella_3.operation_mode = "arithmetic",
+		add_sub_cella_3.sum_lutc_input = "cin",
+		add_sub_cella_3.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_4
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_3cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_4cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[4:4]),
+	.datab(wire_add_sub_cella_datab[4:4]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[4:4]));
+	defparam
+		add_sub_cella_4.cin_used = "true",
+		add_sub_cella_4.lut_mask = "69b2",
+		add_sub_cella_4.operation_mode = "arithmetic",
+		add_sub_cella_4.sum_lutc_input = "cin",
+		add_sub_cella_4.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_5
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_4cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_5cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[5:5]),
+	.datab(wire_add_sub_cella_datab[5:5]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[5:5]));
+	defparam
+		add_sub_cella_5.cin_used = "true",
+		add_sub_cella_5.lut_mask = "69b2",
+		add_sub_cella_5.operation_mode = "arithmetic",
+		add_sub_cella_5.sum_lutc_input = "cin",
+		add_sub_cella_5.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_6
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_5cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_6cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[6:6]),
+	.datab(wire_add_sub_cella_datab[6:6]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[6:6]));
+	defparam
+		add_sub_cella_6.cin_used = "true",
+		add_sub_cella_6.lut_mask = "69b2",
+		add_sub_cella_6.operation_mode = "arithmetic",
+		add_sub_cella_6.sum_lutc_input = "cin",
+		add_sub_cella_6.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_7
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_6cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_7cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[7:7]),
+	.datab(wire_add_sub_cella_datab[7:7]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[7:7]));
+	defparam
+		add_sub_cella_7.cin_used = "true",
+		add_sub_cella_7.lut_mask = "69b2",
+		add_sub_cella_7.operation_mode = "arithmetic",
+		add_sub_cella_7.sum_lutc_input = "cin",
+		add_sub_cella_7.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_8
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_7cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_8cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[8:8]),
+	.datab(wire_add_sub_cella_datab[8:8]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[8:8]));
+	defparam
+		add_sub_cella_8.cin_used = "true",
+		add_sub_cella_8.lut_mask = "69b2",
+		add_sub_cella_8.operation_mode = "arithmetic",
+		add_sub_cella_8.sum_lutc_input = "cin",
+		add_sub_cella_8.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_9
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_8cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_9cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[9:9]),
+	.datab(wire_add_sub_cella_datab[9:9]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[9:9]));
+	defparam
+		add_sub_cella_9.cin_used = "true",
+		add_sub_cella_9.lut_mask = "69b2",
+		add_sub_cella_9.operation_mode = "arithmetic",
+		add_sub_cella_9.sum_lutc_input = "cin",
+		add_sub_cella_9.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_10
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_9cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_10cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[10:10]),
+	.datab(wire_add_sub_cella_datab[10:10]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[10:10]));
+	defparam
+		add_sub_cella_10.cin_used = "true",
+		add_sub_cella_10.lut_mask = "69b2",
+		add_sub_cella_10.operation_mode = "arithmetic",
+		add_sub_cella_10.sum_lutc_input = "cin",
+		add_sub_cella_10.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_11
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_10cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_11cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[11:11]),
+	.datab(wire_add_sub_cella_datab[11:11]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[11:11]));
+	defparam
+		add_sub_cella_11.cin_used = "true",
+		add_sub_cella_11.lut_mask = "69b2",
+		add_sub_cella_11.operation_mode = "arithmetic",
+		add_sub_cella_11.sum_lutc_input = "cin",
+		add_sub_cella_11.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_12
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_11cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_12cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[12:12]),
+	.datab(wire_add_sub_cella_datab[12:12]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[12:12]));
+	defparam
+		add_sub_cella_12.cin_used = "true",
+		add_sub_cella_12.lut_mask = "69b2",
+		add_sub_cella_12.operation_mode = "arithmetic",
+		add_sub_cella_12.sum_lutc_input = "cin",
+		add_sub_cella_12.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_13
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_12cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_13cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[13:13]),
+	.datab(wire_add_sub_cella_datab[13:13]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[13:13]));
+	defparam
+		add_sub_cella_13.cin_used = "true",
+		add_sub_cella_13.lut_mask = "69b2",
+		add_sub_cella_13.operation_mode = "arithmetic",
+		add_sub_cella_13.sum_lutc_input = "cin",
+		add_sub_cella_13.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_14
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_13cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_14cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[14:14]),
+	.datab(wire_add_sub_cella_datab[14:14]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[14:14]));
+	defparam
+		add_sub_cella_14.cin_used = "true",
+		add_sub_cella_14.lut_mask = "69b2",
+		add_sub_cella_14.operation_mode = "arithmetic",
+		add_sub_cella_14.sum_lutc_input = "cin",
+		add_sub_cella_14.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_15
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_14cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_15cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[15:15]),
+	.datab(wire_add_sub_cella_datab[15:15]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[15:15]));
+	defparam
+		add_sub_cella_15.cin_used = "true",
+		add_sub_cella_15.lut_mask = "69b2",
+		add_sub_cella_15.operation_mode = "arithmetic",
+		add_sub_cella_15.sum_lutc_input = "cin",
+		add_sub_cella_15.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_16
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_15cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_16cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[16:16]),
+	.datab(wire_add_sub_cella_datab[16:16]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[16:16]));
+	defparam
+		add_sub_cella_16.cin_used = "true",
+		add_sub_cella_16.lut_mask = "69b2",
+		add_sub_cella_16.operation_mode = "arithmetic",
+		add_sub_cella_16.sum_lutc_input = "cin",
+		add_sub_cella_16.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_17
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_16cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_17cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[17:17]),
+	.datab(wire_add_sub_cella_datab[17:17]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[17:17]));
+	defparam
+		add_sub_cella_17.cin_used = "true",
+		add_sub_cella_17.lut_mask = "69b2",
+		add_sub_cella_17.operation_mode = "arithmetic",
+		add_sub_cella_17.sum_lutc_input = "cin",
+		add_sub_cella_17.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_18
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_17cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_18cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[18:18]),
+	.datab(wire_add_sub_cella_datab[18:18]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[18:18]));
+	defparam
+		add_sub_cella_18.cin_used = "true",
+		add_sub_cella_18.lut_mask = "69b2",
+		add_sub_cella_18.operation_mode = "arithmetic",
+		add_sub_cella_18.sum_lutc_input = "cin",
+		add_sub_cella_18.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_19
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_18cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_19cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[19:19]),
+	.datab(wire_add_sub_cella_datab[19:19]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[19:19]));
+	defparam
+		add_sub_cella_19.cin_used = "true",
+		add_sub_cella_19.lut_mask = "69b2",
+		add_sub_cella_19.operation_mode = "arithmetic",
+		add_sub_cella_19.sum_lutc_input = "cin",
+		add_sub_cella_19.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_20
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_19cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_20cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[20:20]),
+	.datab(wire_add_sub_cella_datab[20:20]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[20:20]));
+	defparam
+		add_sub_cella_20.cin_used = "true",
+		add_sub_cella_20.lut_mask = "69b2",
+		add_sub_cella_20.operation_mode = "arithmetic",
+		add_sub_cella_20.sum_lutc_input = "cin",
+		add_sub_cella_20.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_21
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_20cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_21cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[21:21]),
+	.datab(wire_add_sub_cella_datab[21:21]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[21:21]));
+	defparam
+		add_sub_cella_21.cin_used = "true",
+		add_sub_cella_21.lut_mask = "69b2",
+		add_sub_cella_21.operation_mode = "arithmetic",
+		add_sub_cella_21.sum_lutc_input = "cin",
+		add_sub_cella_21.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_22
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_21cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_22cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[22:22]),
+	.datab(wire_add_sub_cella_datab[22:22]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[22:22]));
+	defparam
+		add_sub_cella_22.cin_used = "true",
+		add_sub_cella_22.lut_mask = "69b2",
+		add_sub_cella_22.operation_mode = "arithmetic",
+		add_sub_cella_22.sum_lutc_input = "cin",
+		add_sub_cella_22.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_23
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_22cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_23cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[23:23]),
+	.datab(wire_add_sub_cella_datab[23:23]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[23:23]));
+	defparam
+		add_sub_cella_23.cin_used = "true",
+		add_sub_cella_23.lut_mask = "69b2",
+		add_sub_cella_23.operation_mode = "arithmetic",
+		add_sub_cella_23.sum_lutc_input = "cin",
+		add_sub_cella_23.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_24
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_23cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_24cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[24:24]),
+	.datab(wire_add_sub_cella_datab[24:24]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[24:24]));
+	defparam
+		add_sub_cella_24.cin_used = "true",
+		add_sub_cella_24.lut_mask = "69b2",
+		add_sub_cella_24.operation_mode = "arithmetic",
+		add_sub_cella_24.sum_lutc_input = "cin",
+		add_sub_cella_24.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_25
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_24cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_25cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[25:25]),
+	.datab(wire_add_sub_cella_datab[25:25]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[25:25]));
+	defparam
+		add_sub_cella_25.cin_used = "true",
+		add_sub_cella_25.lut_mask = "69b2",
+		add_sub_cella_25.operation_mode = "arithmetic",
+		add_sub_cella_25.sum_lutc_input = "cin",
+		add_sub_cella_25.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_26
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_25cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_26cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[26:26]),
+	.datab(wire_add_sub_cella_datab[26:26]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[26:26]));
+	defparam
+		add_sub_cella_26.cin_used = "true",
+		add_sub_cella_26.lut_mask = "69b2",
+		add_sub_cella_26.operation_mode = "arithmetic",
+		add_sub_cella_26.sum_lutc_input = "cin",
+		add_sub_cella_26.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_27
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_26cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_27cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[27:27]),
+	.datab(wire_add_sub_cella_datab[27:27]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[27:27]));
+	defparam
+		add_sub_cella_27.cin_used = "true",
+		add_sub_cella_27.lut_mask = "69b2",
+		add_sub_cella_27.operation_mode = "arithmetic",
+		add_sub_cella_27.sum_lutc_input = "cin",
+		add_sub_cella_27.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_28
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_27cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_28cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[28:28]),
+	.datab(wire_add_sub_cella_datab[28:28]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[28:28]));
+	defparam
+		add_sub_cella_28.cin_used = "true",
+		add_sub_cella_28.lut_mask = "69b2",
+		add_sub_cella_28.operation_mode = "arithmetic",
+		add_sub_cella_28.sum_lutc_input = "cin",
+		add_sub_cella_28.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_29
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_28cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_29cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[29:29]),
+	.datab(wire_add_sub_cella_datab[29:29]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[29:29]));
+	defparam
+		add_sub_cella_29.cin_used = "true",
+		add_sub_cella_29.lut_mask = "69b2",
+		add_sub_cella_29.operation_mode = "arithmetic",
+		add_sub_cella_29.sum_lutc_input = "cin",
+		add_sub_cella_29.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_30
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_29cout[0:0]),
+	.clk(clock),
+	.cout(wire_add_sub_cella_30cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[30:30]),
+	.datab(wire_add_sub_cella_datab[30:30]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[30:30]));
+	defparam
+		add_sub_cella_30.cin_used = "true",
+		add_sub_cella_30.lut_mask = "69b2",
+		add_sub_cella_30.operation_mode = "arithmetic",
+		add_sub_cella_30.sum_lutc_input = "cin",
+		add_sub_cella_30.lpm_type = "stratix_lcell";
+	stratix_lcell   add_sub_cella_31
+	( 
+	.aclr(aclr),
+	.cin(wire_add_sub_cella_30cout[0:0]),
+	.clk(clock),
+	.dataa(wire_add_sub_cella_dataa[31:31]),
+	.datab(wire_add_sub_cella_datab[31:31]),
+	.ena(clken),
+	.regout(wire_add_sub_cella_regout[31:31]));
+	defparam
+		add_sub_cella_31.cin_used = "true",
+		add_sub_cella_31.lut_mask = "6969",
+		add_sub_cella_31.operation_mode = "normal",
+		add_sub_cella_31.sum_lutc_input = "cin",
+		add_sub_cella_31.lpm_type = "stratix_lcell";
+	assign
+		wire_add_sub_cella_dataa = dataa,
+		wire_add_sub_cella_datab = datab;
+	assign
+		result = wire_add_sub_cella_regout;
+endmodule //sub32_add_sub_cqa
+//VALID FILE
+
+
+module sub32 (
+	dataa,
+	datab,
+	clock,
+	aclr,
+	clken,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[31:0]  dataa;
+	input	[31:0]  datab;
+	input	  clock;
+	input	  aclr;
+	input	  clken;
+	output	[31:0]  result;
+
+	wire [31:0] sub_wire0;
+	wire [31:0] result = sub_wire0[31:0];
+
+	sub32_add_sub_cqa	sub32_add_sub_cqa_component (
+				.dataa (dataa),
+				.datab (datab),
+				.clken (clken),
+				.aclr (aclr),
+				.clock (clock),
+				.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "32"
+// Retrieval info: PRIVATE: Function NUMERIC "1"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: aclr NUMERIC "1"
+// Retrieval info: PRIVATE: clken NUMERIC "1"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

fpga/usrp1/megacells/sub32_bb.v

@@ -0,0 +1,37 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module sub32 (
+	dataa,
+	datab,
+	clock,
+	aclr,
+	clken,
+	result)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[31:0]  dataa;
+	input	[31:0]  datab;
+	input	  clock;
+	input	  aclr;
+	input	  clken;
+	output	[31:0]  result;
+
+endmodule
+