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fpga: lib: disable clocks at startup for ddc_ms_tb

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This commit is contained in:
Max Köhler 2026-09-11 12:07:57 +02:00 committed by mkoop-ni
parent 50a47f75de
commit 3f46b68c6d
1 changed files with 26 additions and 3 deletions
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29
fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_ms/rfnoc_block_ddc_ms_tb.sv
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@ -85,9 +85,27 @@ module rfnoc_block_ddc_ms_tb #(
bit rfnoc_ctrl_clk;
bit ce_clk;
sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
sim_clock_gen #(CHDR_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
sim_clock_gen #(DDC_CLK_PER) ddc_clk_gen (.clk(ce_clk), .rst());
sim_clock_gen #(
.PERIOD(CHDR_CLK_PER),
.AUTOSTART(0)
) rfnoc_chdr_clk_gen (
.clk(rfnoc_chdr_clk),
.rst()
);
sim_clock_gen #(
.PERIOD(CHDR_CLK_PER),
.AUTOSTART(0)
) rfnoc_ctrl_clk_gen (
.clk(rfnoc_ctrl_clk),
.rst()
);
sim_clock_gen #(
.PERIOD(DDC_CLK_PER),
.AUTOSTART(0)
) ddc_clk_gen (
.clk(ce_clk),
.rst()
);
//---------------------------------------------------------------------------
@ -924,6 +942,11 @@ module rfnoc_block_ddc_ms_tb #(
test.start_tb($sformatf("rfnoc_block_ddc_tb with SPC=%0d, NUM_PORTS=%0d",
SPC, NUM_PORTS));
// Start the clocks
rfnoc_chdr_clk_gen.start();
rfnoc_ctrl_clk_gen.start();
ddc_clk_gen.start();
// Start the BFMs running
blk_ctrl.run();