mschill 0e3b241021 fpga: x440: add X1_200 bifile variant		2026-08-27 13:31:33 +01:00
..
export/x300/radio	fpga: removing deprecated FIFO IP cores	2026-08-20 01:46:19 +02:00
lib	doc: fpga: host: Updated Wideband DDC DUC related documentation	2026-08-23 02:03:43 +02:00
sim	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
tools	ci: Update fpga packaging configs	2026-08-27 08:41:16 +01:00
top	fpga: x440: add X1_200 bifile variant	2026-08-27 13:31:33 +01:00
.gitignore	Move ignore of build folders into top level	2025-07-18 11:19:52 +02:00
build.py	fpga: Replace references to python -> python3	2023-12-05 15:43:08 -06:00
LICENSE.md	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00