fpga: dsp: fix race condition in axi_tag_time_ms

Fixed an issue when multiple timed DDS commands were present, where
the first one was popped and then the second command immediately
got popped as well to the stale a lookahead signal.
The fix is to clear the lookahead signal and threshold signal on
every fifo pop command.

fpga/usrp3/lib/rfnoc/axi_tag_time_ms.sv

@@ -320,6 +320,12 @@ module axi_tag_time_ms
           lookahead           <= 1'b0;
         end
       end else fifo_time_threshold <= '1;
+      if (cmd_write_en) begin
+        // On a pop both signals still describe the outgoing command, so they
+        // must be invalidated before the next command becomes the FIFO head.
+        lookahead           <= 1'b0;
+        fifo_time_threshold <= '1;
+      end
     end
   end