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fpga: lib: fixup uart non-blocking assignments

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This commit is contained in:
Javier Valenzuela 2026-09-04 01:42:59 -05:00 committed by Frank Dietze
parent 7351887ab5
commit ef0a814a3d
1 changed files with 7 additions and 7 deletions
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14
fpga/usrp3/lib/control/ctrlport_to_wb_uart.v
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@ -112,19 +112,19 @@ module ctrlport_to_wb_uart #(
end
case (s_ctrlport_req_addr)
BASE_ADDRESS + SUART_CLKDIV * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_CLKDIV;
wb_adr_i <= SUART_CLKDIV;
end
BASE_ADDRESS + SUART_TXLEVEL * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_TXLEVEL;
wb_adr_i <= SUART_TXLEVEL;
end
BASE_ADDRESS + SUART_RXLEVEL * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_RXLEVEL;
wb_adr_i <= SUART_RXLEVEL;
end
BASE_ADDRESS + SUART_TXCHAR * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_TXCHAR;
wb_adr_i <= SUART_TXCHAR;
end
BASE_ADDRESS + SUART_RXCHAR * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_RXCHAR;
wb_adr_i <= SUART_RXCHAR;
end
endcase
@ -148,10 +148,10 @@ module ctrlport_to_wb_uart #(
wb_adr_i <= SUART_RXLEVEL;
end
BASE_ADDRESS + SUART_TXCHAR * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_TXCHAR;
wb_adr_i <= SUART_TXCHAR;
end
BASE_ADDRESS + SUART_RXCHAR * REG_STRIDE_SIZE: begin
wb_adr_i = SUART_RXCHAR;
wb_adr_i <= SUART_RXCHAR;
end
// Respond with 0
default: begin