From ef0a814a3d1a9f4761c9de9cc9f1b3acb5679da4 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Fri, 4 Sep 2026 01:42:59 -0500 Subject: [PATCH] fpga: lib: fixup uart non-blocking assignments --- fpga/usrp3/lib/control/ctrlport_to_wb_uart.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v b/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v index 32c5e7a06..e7d9d31af 100644 --- a/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v +++ b/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v @@ -112,19 +112,19 @@ module ctrlport_to_wb_uart #( end case (s_ctrlport_req_addr) BASE_ADDRESS + SUART_CLKDIV * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_CLKDIV; + wb_adr_i <= SUART_CLKDIV; end BASE_ADDRESS + SUART_TXLEVEL * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_TXLEVEL; + wb_adr_i <= SUART_TXLEVEL; end BASE_ADDRESS + SUART_RXLEVEL * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_RXLEVEL; + wb_adr_i <= SUART_RXLEVEL; end BASE_ADDRESS + SUART_TXCHAR * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_TXCHAR; + wb_adr_i <= SUART_TXCHAR; end BASE_ADDRESS + SUART_RXCHAR * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_RXCHAR; + wb_adr_i <= SUART_RXCHAR; end endcase @@ -148,10 +148,10 @@ module ctrlport_to_wb_uart #( wb_adr_i <= SUART_RXLEVEL; end BASE_ADDRESS + SUART_TXCHAR * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_TXCHAR; + wb_adr_i <= SUART_TXCHAR; end BASE_ADDRESS + SUART_RXCHAR * REG_STRIDE_SIZE: begin - wb_adr_i = SUART_RXCHAR; + wb_adr_i <= SUART_RXCHAR; end // Respond with 0 default: begin