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fpga: lib: Add DEVICE parameter to gpif2 and radio_legacy

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Wade Fife 2026-09-01 16:53:01 -05:00 committed by Frank Dietze
parent 6a8a56afb2
commit 85e163a0d9
4 changed files with 18 additions and 14 deletions
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5
fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v
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@ -9,7 +9,8 @@
module fifo64_to_gpif2
#(
parameter FIFO_SIZE = 9,
parameter MTU = 12
parameter MTU = 12,
parameter DEVICE = "SPARTAN6"
)
(
//input fifo interface
@ -42,7 +43,7 @@ module fifo64_to_gpif2
wire gate_tlast;
wire gate_tvalid, gate_tready;
axi_fifo_2clk #(.WIDTH(33), .SIZE(FIFO_SIZE)) cross_clock_fifo
axi_fifo_2clk #(.WIDTH(33), .SIZE(FIFO_SIZE), .DEVICE(DEVICE)) cross_clock_fifo
(
.reset(fifo_rst | gpif_rst),
.i_aclk(fifo_clk), .i_tdata({i32_tlast, i32_tdata}), .i_tvalid(i32_tvalid), .i_tready(i32_tready),

12
fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v
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@ -22,7 +22,9 @@ module gpif2_slave_fifo32
parameter ADDR_DATA_TX = 2'b00,
parameter ADDR_DATA_RX = 2'b01,
parameter ADDR_CTRL_TX = 2'b10,
parameter ADDR_CTRL_RX = 2'b11
parameter ADDR_CTRL_RX = 2'b11,
parameter DEVICE = "SPARTAN6"
)
(
// GPIF signals
@ -479,7 +481,7 @@ module gpif2_slave_fifo32
// TX Data Path
wire [31:0] debug_data_fifo;
gpif2_to_fifo64 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE)) gpif2_to_fifo64_tx(
gpif2_to_fifo64 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE), .DEVICE(DEVICE)) gpif2_to_fifo64_tx (
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.i_tdata(gpif_data_in), .i_tlast(data_ctrl_tx_tlast), .i_tvalid(data_tx_tvalid), .i_tready(data_tx_tready), // IJB. NOTE data_tx_tready currently unused.
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
@ -491,7 +493,7 @@ module gpif2_slave_fifo32
// ////////////////////////////////////////////
// RX Data Path
fifo64_to_gpif2 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo64_to_gpif2_rx(
fifo64_to_gpif2 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE), .DEVICE(DEVICE)) fifo64_to_gpif2_rx (
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.i_tdata(rx_tdata), .i_tlast(rx_tlast), .i_tvalid(rx_tvalid), .i_tready(rx_tready),
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
@ -502,7 +504,7 @@ module gpif2_slave_fifo32
// CTRL path
wire [31:0] debug_ctrl_fifo;
gpif2_to_fifo64 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE)) gpif2_to_fifo64_ctrl(
gpif2_to_fifo64 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE), .DEVICE(DEVICE)) gpif2_to_fifo64_ctrl (
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.i_tdata(gpif_data_in), .i_tlast(data_ctrl_tx_tlast), .i_tvalid(ctrl_tx_tvalid), .i_tready(ctrl_tx_tready), // IJB. NOTE data_tx_tready currently unused.
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
@ -514,7 +516,7 @@ module gpif2_slave_fifo32
// ////////////////////////////////////////////////////////////////////
// RESP path
fifo64_to_gpif2 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo64_to_gpif2_resp(
fifo64_to_gpif2 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE), .DEVICE(DEVICE)) fifo64_to_gpif2_resp (
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.i_tdata(resp_tdata), .i_tlast(resp_tlast), .i_tvalid(resp_tvalid), .i_tready(resp_tready),
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),

5
fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v
View File

@ -9,7 +9,8 @@
module gpif2_to_fifo64
#(
parameter FIFO_SIZE = 9,
parameter MTU = 12
parameter MTU = 12,
parameter DEVICE = "SPARTAN6"
)
(
//input interface
@ -77,7 +78,7 @@ module gpif2_to_fifo64
wire chk_tlast;
wire chk_tvalid, chk_tready;
axi_fifo_2clk #(.WIDTH(33), .SIZE(FIFO_SIZE)) cross_clock_fifo
axi_fifo_2clk #(.WIDTH(33), .SIZE(FIFO_SIZE), .DEVICE(DEVICE)) cross_clock_fifo
(
.reset(fifo_rst | gpif_rst),
.i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),

10
fpga/usrp3/lib/radio_200/radio_legacy.v
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@ -86,22 +86,22 @@ module radio_legacy
wire rx_tlast_int;
axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/), .DEVICE(DEVICE)) ctrl_fifo
(.reset(bus_rst),
.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE), .DEVICE(DEVICE)) tx_fifo
(.reset(bus_rst),
.i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) resp_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/), .DEVICE(DEVICE)) resp_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE), .DEVICE(DEVICE)) rx_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(rx_tvalid_r), .i_tready(rx_tready_r), .i_tdata({rx_tlast_r, rx_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int), .o_tdata({rx_tlast_int, rx_tdata_int}));
@ -238,7 +238,7 @@ endgenerate
wire [63:0] vita_time_b_int;
wire vita_time_b_valid;
axi_fifo_2clk #(.WIDTH(64), .SIZE(0)) vita_time_fifo
axi_fifo_2clk #(.WIDTH(64), .SIZE(0), .DEVICE(DEVICE)) vita_time_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(1'b1), .i_tready(), .i_tdata(vita_time),
.o_aclk(bus_clk), .o_tvalid(vita_time_b_valid), .o_tready(1'b1), .o_tdata(vita_time_b_int));