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fpga: b310: Use a resources file for RFNOC_OOT_SRCS

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Use a resources file to pass RFNoC OOT source files to Vivado TCL
scripts, avoiding ARG_MAX argument list limits.

This makes B310 consistent with other USRPs that were previously
updated in commit fa7c3604.
This commit is contained in:
Wade Fife 2026-09-09 18:17:19 -05:00
parent ddb7e6866b
commit 5ff8ca11f3
1 changed files with 7 additions and 4 deletions
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11
fpga/usrp3/top/b300/Makefile.b310.inc
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@ -80,7 +80,7 @@ $(IOPORT2_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) $(PACKET_PROC_SRCS) $(DSP_SRCS) \
$(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(LIB_IP_XCI_SRCS) $(PCI_K7_SRCS) \
$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
$(RFNOC_SRCS) \
$(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS) \
$(TOP_SRCS) \
@ -97,17 +97,20 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
$(OOT_SRCS_FILE):
@printf "%s\n" $(RFNOC_OOT_SRCS) > $@
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
bin: .prereqs $(OOT_SRCS_FILE)
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_b310.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
rtl: .prereqs
rtl: .prereqs $(OOT_SRCS_FILE)
$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
viv_ip: .prereqs $$(DESIGN_SRCS) ip
@echo "IP build for $(NAME) DONE . . ."
.PHONY: bin rtl viv_ip
.PHONY: bin rtl viv_ip $(OOT_SRCS_FILE)