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fpga: dsp: Reduce CIC comb bus width for cic_filter_interp
We can reduce the bus width of the comb filter stage in the CIC interpolation filter, as it is the first module in the CIC filter and only adds one bit per order stage. Therefore, we do not need to immediately go to the full accumulation bit width needed for the later integrator stages of the CIC interpolation filter, and can save some FPGA resources by only extending to the required width for each CIC stage. The same logic also applies to the interpolation stage, which only adds zeros into the bitstream and therefore does not change the bus width.
This commit is contained in:
Niels Garibaldi
mkoop-ni
parent
57df0ca685
commit
4904d06da2
@ -49,8 +49,10 @@
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// Finally, ORDER integrator stages accumulate partial sums across SPC
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// parallel sample lanes at the full output rate.
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//
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// Internally, all stages operate at ACCUM_W bits, which is automatically
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// computed to accommodate the full CIC bit growth of N*log2(R_max*D_max).
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// Comb and interpolator stages use COMB_W bits. COMB_W provides ORDER bits
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// of growth per I/Q component for the comb cascade. Integrator stages use
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// ACCUM_W bits, automatically computed to provide
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// ORDER*ceil(log2(MAX_INTERP*MAX_DELAY)) bits of growth per component.
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// Internal stages do not clip or round. The output is normalized back to
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// SAMP_W with signed round-to-nearest quantization.
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//
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@ -102,9 +104,14 @@ module cic_filter_interp #(
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//--------------------------------------------------------------------------
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localparam int MAX_DELAY = 1; // Maximum comb delay in samples
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// Accumulator width to accommodate max CIC growth without overflow:
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// Accumulator width for the maximum integrator growth without overflow.
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localparam int ACCUM_W = 2 * (SAMP_W/2 + $clog2(MAX_INTERP*MAX_DELAY)*ORDER);
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localparam int COMP_W = ACCUM_W/2; // Width of each I/Q component in the accumulator
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// A cascade of ORDER comb stages has coefficients whose absolute sum is
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// 2**ORDER, so each component needs ORDER bits of growth. The comb stages
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// precede the interpolator and can therefore use less width than the full
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// accumulation path.
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localparam int COMB_W = 2 * (SAMP_W/2 + ORDER);
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//---------------------------------------------------------------------------
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// Internal AXI-Stream buses
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@ -112,11 +119,16 @@ module cic_filter_interp #(
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// Comb chain: ORDER+1 buses connecting comb filter inputs/outputs.
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// comb_bus[0] is driven by the sign-extended input.
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// comb_bus[i] for i > 0 carries the output of comb stage i-1.
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AxiStreamIf #(SPC * ACCUM_W) comb_bus [ORDER+1] (.clk(clk), .rst(rst));
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AxiStreamIf #(SPC * COMB_W) comb_bus [ORDER+1] (.clk(clk), .rst(rst));
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// Integrator chain: ORDER+1 buses connecting integrator outputs.
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// integ_bus[0] is driven by the interpolator output.
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// integ_bus[i] for i > 0 carries the output of integrator stage i-1.
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// The interpolator operates at COMB_W bits. Its output is sign-extended to
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// ACCUM_W bits before entering the integrator chain.
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AxiStreamIf #(SPC * COMB_W) interp_bus (.clk(clk), .rst(rst));
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// Integrator path: two buses connecting the interpolator to the integrator
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// chain and carrying the chain output.
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// integ_bus[0] is driven by the interpolator.
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// integ_bus[1] carries the output of the ORDER-stage integrator chain.
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AxiStreamIf #(SPC * ACCUM_W) integ_bus [2] (.clk(clk), .rst(rst));
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//---------------------------------------------------------------------------
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@ -139,11 +151,11 @@ module cic_filter_interp #(
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//--------------------------------------------------------------------------
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// Sign extension to ACCUM_W bits for the input samples
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// Sign extension to COMB_W bits for the input samples
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//
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// Each sample in data_in is SAMP_W bits wide ({I, Q}). Sign-extend each I
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// and Q component independently from SAMP_W/2 to COMP_W bits, then pack into
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// comb_bus[0].tdata as ACCUM_W-wide samples.
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// and Q component independently from SAMP_W/2 to COMB_W/2 bits, then pack
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// into comb_bus[0].tdata as COMB_W-wide samples.
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//--------------------------------------------------------------------------
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assign comb_bus[0].tvalid = data_in.tvalid;
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@ -154,18 +166,18 @@ module cic_filter_interp #(
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// Q component (lower half of each sample)
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sign_extend #(
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.bits_in (SAMP_W/2),
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.bits_out(COMP_W)
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.bits_out(COMB_W/2)
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) sign_ext_q (
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.in (data_in.tdata[SAMP_W*samp_idx +: SAMP_W/2]),
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.out(comb_bus[0].tdata[ACCUM_W*samp_idx +: COMP_W])
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.out(comb_bus[0].tdata[COMB_W*samp_idx +: COMB_W/2])
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);
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// I component (upper half of each sample)
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sign_extend #(
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.bits_in (SAMP_W/2),
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.bits_out(COMP_W)
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.bits_out(COMB_W/2)
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) sign_ext_i (
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.in (data_in.tdata[SAMP_W*samp_idx + SAMP_W/2 +: SAMP_W/2]),
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.out(comb_bus[0].tdata[ACCUM_W*samp_idx + COMP_W +: COMP_W])
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.out(comb_bus[0].tdata[COMB_W*samp_idx + COMB_W/2 +: COMB_W/2])
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);
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end : gen_sign_ext
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@ -175,7 +187,7 @@ module cic_filter_interp #(
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//---------------------------------------------------------------------------
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for (genvar stage = 0; stage < ORDER; stage++) begin : gen_combs
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cic_comb_filter #(
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.ACCUM_W (ACCUM_W),
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.ACCUM_W (COMB_W),
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.SPC (SPC),
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.FIFO_SIZE((stage == ORDER-1)? 1 : 0)
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) cic_comb_filter_i (
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@ -192,18 +204,46 @@ module cic_filter_interp #(
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// Interpolator: increases sample rate by interp_factor
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//---------------------------------------------------------------------------
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cic_interpolator #(
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.SAMP_W (ACCUM_W),
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.SAMP_W (COMB_W),
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.SPC (SPC),
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.R_MAX (MAX_INTERP)
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) cic_interpolator_i (
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.clk (clk),
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.rst (rst || clear),
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.data_in (comb_bus[ORDER]),
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.data_out (integ_bus[0]),
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.data_out (interp_bus),
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.interp_factor (interp_factor_reg),
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.interp_changed(config_changed_reg)
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);
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//--------------------------------------------------------------------------
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// Sign extension from COMB_W to ACCUM_W bits.
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//
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// The interpolator does not increase the numeric width. The integrator
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// stages require ACCUM_W bits to accommodate their accumulated growth.
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//--------------------------------------------------------------------------
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assign integ_bus[0].tvalid = interp_bus.tvalid;
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assign integ_bus[0].tlast = interp_bus.tlast;
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assign interp_bus.tready = integ_bus[0].tready;
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for (genvar samp_idx = 0; samp_idx < SPC; samp_idx++) begin : gen_interp_ext
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sign_extend #(
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.bits_in (COMB_W/2),
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.bits_out(ACCUM_W/2)
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) sign_ext_q (
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.in (interp_bus.tdata[COMB_W*samp_idx +: COMB_W/2]),
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.out(integ_bus[0].tdata[ACCUM_W*samp_idx +: ACCUM_W/2])
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);
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sign_extend #(
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.bits_in (COMB_W/2),
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.bits_out(ACCUM_W/2)
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) sign_ext_i (
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.in (interp_bus.tdata[COMB_W*samp_idx + COMB_W/2 +: COMB_W/2]),
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.out(integ_bus[0].tdata[ACCUM_W*samp_idx + ACCUM_W/2 +: ACCUM_W/2])
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);
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end : gen_interp_ext
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//---------------------------------------------------------------------------
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// Integrator chain: ORDER stages at full output rate
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