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https://github.com/EttusResearch/uhd.git
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dsp: cic: Add FIFO in CIC decimation to allow tready bypass
Added a Fifo to bypass handshaking inside of the cic filter decim data pipeline.
This commit is contained in:
Niels Garibaldi
mkoop-ni
parent
5b1bcabcf8
commit
58ab7a88cc
@ -7,63 +7,89 @@
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//
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// Description:
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//
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// CIC decimation filter for multiple samples per clock cycle, implementing
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// the classic Hogenauer (CIC) decimation topology:
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// CIC decimation filter for SPC complex samples per clock cycle. The datapath
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// implements the classic Hogenauer topology and adds rate-dependent gain
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// normalization and an output FIFO:
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//
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// data_in
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// │
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// v
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// ┌───────────────────────────────┐
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// │ ┌────────────────────────┐ │
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// │ │ Integrator 0 │ │
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// │ └───────────┬────────────┘ │
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// │ │ │
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// │ ··· │ ORDER stages
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// │ │ │ (full input rate)
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// │ ┌────────────────────────┐ │
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// │ │ Integrator ORDER-1 │ │
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// │ └───────────┬────────────┘ │
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// └──────────────┼────────────────┘
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// │
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// ┌────────────────────────┐
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// decim_factor─┤ Decimator (÷R) │
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// └───────────┬────────────┘
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// │
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// ┌──────────────┼────────────────┐
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// │ ┌────────────────────────┐ │
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// │ │ Comb 0 │ │
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// │ └───────────┬────────────┘ │ ORDER stages
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// │ │ │ (decimated rate)
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// │ ... │
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// │ │ │
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// │ │ │
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// │ ┌────────────────────────┐ │
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// │ │ Comb ORDER-1 │ │
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// │ └───────────┬────────────┘ │
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// └──────────────┼────────────────┘
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// (SPC x SAMP_W)
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// │ tready
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// v<─────────────────────────────────┐
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// ┌───────────────────────────────┐ │
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// │ I/Q sign extension │ │
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// │ SAMP_W -> ACCUM_W │ │
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// └──────────────┬────────────────┘ │
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// │ │
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// ┌──────────────┼────────────────┐ │
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// │ ┌────────────────────────┐ │ │
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// │ │ Integrator 0 │ │ │
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// │ └───────────┬────────────┘ │ │
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// │ │ │ ORDER stages │
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// │ ... │ (full input rate)│
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// │ │ │ │
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// │ ┌────────────────────────┐ │ │
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// │ │ Integrator ORDER-1 │ │ │
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// │ └───────────┬────────────┘ │ │
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// └──────────────┼────────────────┘ │
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// │ │
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// ┌────────────────────────┐ │
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// decim_factor ─┤ Decimator (÷R) │ │
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// └───────────┬────────────┘ │
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// │ │
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// ┌──────────────┼────────────────┐ │
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// │ ┌────────────────────────┐ │ │
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// │ │ Comb 0 │ │ │
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// │ └───────────┬────────────┘ │ │
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// │ │ │ ORDER stages │
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// │ ... │ (decimated rate) │
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// │ │ │ │
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// │ ┌────────────────────────┐ │ │
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// │ │ Comb ORDER-1 │ │ │
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// │ └───────────┬────────────┘ │ │
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// └──────────────┼────────────────┘ │
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// │ │
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// ┌───────────────────────────────┐ │
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// │ Normalize and round │ │
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// │ ACCUM_W -> SAMP_W │ │
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// └──────────────┬────────────────┘ │
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// │ │
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// ┌───────────────────────────────┐ fifo_space │
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// │ Output FIFO │──────────────────┘
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// └──────────────┬────────────────┘
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// │
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// v
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// data_out
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// data_out
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// (SPC x SAMP_W)
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//
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// ORDER integrator stages run at the full input rate, accumulating partial
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// sums across SPC parallel sample lanes. The single decimator then selects
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// every R-th sample group (keeping SPC output samples per word). Finally,
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// ORDER comb stages (y[n] = x[n] - x[n-D]) operate at the decimated rate.
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// Each input word contains SPC packed complex samples. The module sign-extends
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// each I and Q component to ACCUM_W, which includes the maximum CIC bit growth.
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// The ORDER integrator stages process every input sample. For decimation factor
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// R, the decimator consumes R input words and constructs one SPC-sample output
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// word by selecting every R-th integrated sample. The ORDER comb stages then
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// apply y[n] = x[n] - x[n-1] at the decimated rate.
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//
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// All stages use the same SAMP_W, which must be pre-sized to accommodate
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// the full CIC bit growth of N*log2(R_max*D_max). Internal stages do not
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// clip or round; the final rate-dependent output conversion rounds before
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// reducing the result to SAMP_W.
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// The barrel shifter normalizes the CIC gain by right-shifting each accumulator
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// component by ceil(log2(R**ORDER)). It rounds each result to SAMP_W/2 bits
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// before packing the SPC output samples.
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//
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// NOTE: This module is expected to run within the context of the axi_rate_change
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// module, which ensures that the number of input words is always a multiple
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// of the decimation factor and that the output tlast signals are correctly
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// aligned.
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// Downstream backpressure stops at the output FIFO. A registered credit gate
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// admits input words only while the FIFO has room for every possible output
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// already in flight, using the worst-case R=1 rate. Once accepted, a word can
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// traverse the datapath without stalling on data_out.tready. If the reserved
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// capacity runs low, data_in.tready deasserts until FIFO space becomes available.
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//
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// The decimation factor is driven directly on decim_factor. It must be valid
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// before reset is released and remain stable while data is actively
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// processed.
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//
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// NOTE: This module is expected to run within axi_rate_change, which ensures
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// that each packet contains a multiple of R input words and that output tlast
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// signals are correctly aligned.
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//
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// Parameters:
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//
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// SPC : Number of samples per clock cycle (must be power of 2, >= 1).
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// SAMP_W : Bit width of each sample (I + Q packed, each SAMP_W/2 bits).
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// SPC : Number of samples per clock cycle (must be power of 2, >= 1).
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// SAMP_W : External sample width (I + Q packed, each SAMP_W/2 bits).
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// MAX_DECIM : Maximum decimation factor supported. Sizes internal registers.
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// ORDER : CIC filter order (number of integrator and comb stages).
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//
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@ -97,6 +123,22 @@ module cic_filter_decim #(
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localparam int ACCUM_W = 2 * (SAMP_W/2 + $clog2(MAX_DECIM*MAX_DELAY)*ORDER);
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localparam int COMP_W = ACCUM_W/2; // Width of each I/Q component in the accumulator
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import cic_utils_pkg::*;
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// Reserve for the worst-case R=1 path, where every input word produces an
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// output word, plus one cycle each for the registered FIFO-space decision
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// and input_blocked state.
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localparam int DATAPATH_LATENCY = integrator_latency(SPC, ORDER)
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+ decimator_latency()
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+ comb_filter_latency(ORDER)
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+ barrel_shift_latency(ACCUM_W, SAMP_W)
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+ 2; // Additional cycles for fifo_ready and input_blocked
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// Set the output FIFO size to twice the datapath latency to allow continuous
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// downstream traffic.
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localparam int OUTPUT_FIFO_SIZE = $clog2(2 * DATAPATH_LATENCY);
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localparam int OUTPUT_FIFO_DEPTH = 1 << OUTPUT_FIFO_SIZE;
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//---------------------------------------------------------------------------
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// Internal AXI-Stream buses
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//---------------------------------------------------------------------------
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@ -109,6 +151,10 @@ module cic_filter_decim #(
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// comb_bus[i] for i > 0 carries the output of comb stage i-1.
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AxiStreamIf #(SPC * ACCUM_W) comb_bus [ORDER+1] (.clk(clk), .rst(rst));
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// The output of the barrel shift stage after the bus width is reduced back
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// to SAMP_W bits from ACCUM_W bits.
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AxiStreamIf #(SPC * SAMP_W) barrel_shift_out (.clk(clk), .rst(rst));
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//--------------------------------------------------------------------------
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// Sign extension to ACCUM_W bits for the input samples
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@ -118,9 +164,27 @@ module cic_filter_decim #(
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// bits, then pack into integ_bus[0].tdata as ACCUM_W-wide samples.
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//--------------------------------------------------------------------------
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assign integ_bus[0].tvalid = data_in.tvalid;
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assign integ_bus[0].tlast = data_in.tlast;
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assign data_in.tready = integ_bus[0].tready;
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logic fifo_ready;
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logic input_blocked;
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// Hold the input blocked until FIFO credit is restored.
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always_ff @(posedge clk) begin
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if (rst || clear) begin
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input_blocked <= 1'b0;
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end else begin
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if (fifo_ready) begin
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input_blocked <= 1'b0;
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end else if (integ_bus[0].tvalid && integ_bus[0].tready) begin
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input_blocked <= 1'b1;
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end
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end
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end
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always_comb begin
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integ_bus[0].tvalid = data_in.tvalid & ~input_blocked;
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integ_bus[0].tlast = data_in.tlast;
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data_in.tready = integ_bus[0].tready & ~input_blocked;
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end
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for (genvar samp_idx = 0; samp_idx < SPC; samp_idx++) begin : gen_sign_ext
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// Q component (lower half of each sample)
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@ -200,9 +264,55 @@ module cic_filter_decim #(
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.clear (clear),
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.rate_factor (decim_factor),
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.data_in (comb_bus[ORDER]),
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.data_out (data_out)
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.data_out (barrel_shift_out)
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);
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// Downstream backpressure terminates at the output FIFO. The credit gate at
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// data_in reserves enough room for every word already in the datapath.
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assign barrel_shift_out.tready = 1'b1;
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localparam FIFO_WIDTH = data_out.DATA_WIDTH + 1;
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logic [15:0] fifo_space;
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logic output_fifo_i_tready;
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logic [FIFO_WIDTH-1:0] fifo_data_in;
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logic [FIFO_WIDTH-1:0] fifo_data_out;
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assign fifo_data_in = {barrel_shift_out.tlast, barrel_shift_out.tdata};
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assign {data_out.tlast, data_out.tdata} = fifo_data_out;
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always_ff @(posedge clk) begin
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if (rst || clear) begin
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fifo_ready <= 1'b0;
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end else begin
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fifo_ready <= (fifo_space > DATAPATH_LATENCY);
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end
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end
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axi_fifo #(
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.WIDTH(FIFO_WIDTH),
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.SIZE (OUTPUT_FIFO_SIZE)
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) output_fifo (
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.clk (clk),
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.reset (rst),
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.clear (clear),
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.i_tdata (fifo_data_in),
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.i_tvalid (barrel_shift_out.tvalid),
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.i_tready (output_fifo_i_tready),
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.o_tdata (fifo_data_out),
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.o_tvalid (data_out.tvalid),
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.o_tready (data_out.tready),
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.space (fifo_space),
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.occupied ()
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);
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// synthesis translate_off
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assert property (
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@(posedge clk) disable iff (rst || clear)
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barrel_shift_out.tvalid |-> output_fifo_i_tready
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) else
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$error("cic_filter_decim: output FIFO not ready for valid data");
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// synthesis translate_on
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endmodule : cic_filter_decim
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`default_nettype wire
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@ -155,6 +155,27 @@ module cic_filter_decim_tb #(
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.data_out (o_data)
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);
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// Monitor output packet activity during drain phase of backpressure test.
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bit monitor_output_tvalid;
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bit output_packet_active;
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always_ff @(posedge clk) begin : track_output_packet
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if (rst || clr) begin
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output_packet_active <= 1'b0;
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end else if (o_data.tvalid && o_data.tready) begin
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output_packet_active <= !o_data.tlast;
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end
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end
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always @(negedge o_data.tvalid) begin : assert_output_tvalid
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if (monitor_output_tvalid && output_packet_active) begin
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`ASSERT_ERROR(0, "Output tvalid deasserted before packet end")
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end
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end
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// Saturation threshold for the output FIFO, used in backpressure tests.
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localparam int SATURATION_WORDS = (2 ** (dut.OUTPUT_FIFO_SIZE + 1)) ;
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//---------------------------------------------------------------------------
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// Reference Model
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//---------------------------------------------------------------------------
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@ -292,6 +313,70 @@ module cic_filter_decim_tb #(
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@(negedge rst);
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endtask : test_cic_decim
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//--------------------------------------------------------------------------
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// Fill the output FIFO, observe input backpressure, then drain all data.
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//--------------------------------------------------------------------------
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task automatic test_output_fifo_backpressure();
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axis_pkt_t input_pkt;
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axis_pkt_t rx_pkt;
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sample_queue_t input_samples;
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sample_queue_t expected_samples;
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sample_queue_t actual_samples;
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model_sample_queue_t model_in;
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model_sample_queue_t model_out;
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set_decim_factor(1);
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input_pkt = test_utils_c::generate_random_packet(SATURATION_WORDS);
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input_samples = test_utils_c::pkt_to_samples(input_pkt.copy());
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model_in = {};
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foreach (input_samples[i]) begin
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model_in.push_back(sign_extend_sample(input_samples[i]));
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end
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model.process(model_in, 1, model_out);
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expected_samples = {};
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foreach (model_out[i]) begin
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expected_samples.push_back(shift_sample(model_out[i], 1));
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end
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bfm.set_master_stall_prob(0);
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bfm.set_slave_stall_prob(100);
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bfm.put(input_pkt);
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// Ignore the initial credit startup delay, then wait for the FIFO credits
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// to be exhausted while input data remains pending.
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do begin
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@(posedge clk);
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end while (!i_data.tvalid || !i_data.tready);
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@(negedge i_data.tready);
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`ASSERT_ERROR(i_data.tvalid, "Input packet ended before backpressure was observed")
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// Allow all admitted words to reach the output FIFO while it remains
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// blocked. No new input should be accepted until output space is released.
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clk_gen.clk_wait_r(SATURATION_WORDS);
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`ASSERT_ERROR(!i_data.tready, "Input credits reopened while output remained blocked")
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monitor_output_tvalid = 1;
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bfm.set_slave_stall_prob(0);
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bfm.get(rx_pkt);
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monitor_output_tvalid = 0;
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actual_samples = test_utils_c::pkt_to_samples(rx_pkt.copy());
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`ASSERT_ERROR(actual_samples.size() == expected_samples.size(),
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$sformatf("Expected %0d output samples, received %0d",
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expected_samples.size(), actual_samples.size()))
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foreach (expected_samples[i]) begin
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`ASSERT_ERROR(actual_samples[i] === expected_samples[i],
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$sformatf("Backpressure sample %0d: expected 0x%0h, got 0x%0h",
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i, expected_samples[i], actual_samples[i]))
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end
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bfm.set_master_stall_prob(STALL_PROB_DEFAULT);
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bfm.set_slave_stall_prob(STALL_PROB_DEFAULT);
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clk_gen.reset();
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@(negedge rst);
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endtask : test_output_fifo_backpressure
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//---------------------------------------------------------------------------
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// Main Test Process
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//---------------------------------------------------------------------------
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@ -325,6 +410,13 @@ module cic_filter_decim_tb #(
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end
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test.end_test();
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//-------------------------------------------------------------------------
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// Test: output FIFO saturation and recovery
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//-------------------------------------------------------------------------
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test.start_test("CIC decim output FIFO backpressure", 1ms);
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test_output_fifo_backpressure();
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test.end_test();
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//-------------------------------------------------------------------------
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// Test: ramp input (I=Q=1,2,3,...) with random decimation factor
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//-------------------------------------------------------------------------
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@ -34,6 +34,17 @@ package cic_utils_pkg;
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return integrator_dsp_latency(spc, order) + 1;
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endfunction
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// The decimator has a registered compute_output stage and a 1-cycle
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// output FIFO.
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function automatic int decimator_latency();
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return 2;
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endfunction
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// Each comb stage contains one registered output FIFO stage.
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function automatic int comb_filter_latency(input int order);
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return order;
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endfunction
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class cic_utils #(
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parameter int SPC = 8, // Number of samples processed per clock cycle
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parameter int SAMP_W = 48 // Input/output data width
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