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fpga: lib: adjust ctrlport_to_wb_uart signal width

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Javier Valenzuela 2026-09-28 20:02:43 -05:00 committed by Wade Fife
parent 1907032f7b
commit 5709e8b546
1 changed files with 1 additions and 1 deletions
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fpga/usrp3/lib/control/ctrlport_to_wb_uart.v
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@ -56,7 +56,7 @@ module ctrlport_to_wb_uart #(
reg wb_cyc_i; // Active bus cycle
reg wb_we_i = 1'b0; // Write access
reg [ 4:0] wb_adr_i = 3'b0;
reg [ 2:0] wb_adr_i = 3'b0;
reg [31:0] wb_dat_i = 32'b0;
wire wb_ack_o;
wire [31:0] wb_dat_o;