From 5709e8b54679a970898590b46276db019c47ba77 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Mon, 28 Sep 2026 20:02:43 -0500 Subject: [PATCH] fpga: lib: adjust ctrlport_to_wb_uart signal width --- fpga/usrp3/lib/control/ctrlport_to_wb_uart.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v b/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v index e7d9d31af..6c107f212 100644 --- a/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v +++ b/fpga/usrp3/lib/control/ctrlport_to_wb_uart.v @@ -56,7 +56,7 @@ module ctrlport_to_wb_uart #( reg wb_cyc_i; // Active bus cycle reg wb_we_i = 1'b0; // Write access - reg [ 4:0] wb_adr_i = 3'b0; + reg [ 2:0] wb_adr_i = 3'b0; reg [31:0] wb_dat_i = 32'b0; wire wb_ack_o; wire [31:0] wb_dat_o;