Added a state machine to fix a bug in the temporal decimation code
of the decimating halfband filter module.
Additionally added a testcase to the testbench for the issue this
change is fixing.
Reversing the order of the barrel shifter module used by the CIC
filter implementations, in order to reduce the possible bits
selectable from the last stage going into the rounding module.
This should make routing easier.
We can reduce the bus width of the comb filter stage in the CIC
interpolation filter, as it is the first module in the CIC filter and
only adds one bit per order stage. Therefore, we do not need to
immediately go to the full accumulation bit width needed for the later
integrator stages of the CIC interpolation filter, and can save some
FPGA resources by only extending to the required width for each CIC
stage.
The same logic also applies to the interpolation stage, which only adds
zeros into the bitstream and therefore does not change the bus width.
Adding a FIFO size module parameter to the comb filter module, in
order to selectively set only the last of N-order filter stages to
use a 2-stage FIFO.
Without this change, kernel 6.12 generates the following warning:
nixge 40000000.ethernet (unnamed net_device) (uninitialized): fixed link full duplex 1000Mbps not recognised
With the change, the link is correctly detected as 1G:
nixge 40000000.ethernet sfp0: configuring for fixed/gmii link mode
Fixed an issue when multiple timed DDS commands were present, where
the first one was popped and then the second command immediately
got popped as well to the stale a lookahead signal.
The fix is to clear the lookahead signal and threshold signal on
every fifo pop command.
Enable clock watch circuit for images with 200 and 400MHz bandwidth
as well. With this we also move from watch the rfdc_clk to watch the
radio_clk. This makes is easier to calculate the max clock rate for
all flavours of images.
Updated the references to DDC and DUC RFNoC blocks to reflect the
new split between legacy(singlesample) and wideband(multisample)
implementations.
Updated the related manual references as well as the C++ block
controller API comments that are pulled in by doxygen.
Also fixed a minor outdated comment in the FPGA source code.
Adding the RFNoC DDC and DUC blocks to our shipping bitfiles.
The new wideband DxC implementation allow processing input/output
rates up to a maximum of 2000MSps.
This commit adds the DDC/DUC blocks to some of our shipping
bitfiles for all channels.
Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com>
Co-authored-by: André Zoch <andre.zoch@emerson.com>
Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
Adds a direct MMCM output for the quarter rfdc_clk.
Additionally, all other consumers of the rfdc_clk and rfdc_clk_2x
receive their clock from the MMCM output directly instead of
the clock buffers. Thus, making the clock buffers obsolete and
removing them from the design.
For the multisample version of the DUC block, in order
to align with the singlesample behavior this changes the packet
generation in axi_rate_change_ms to only include the timestamp in
the first packet of each burst.
Add a parameter to the axi_rate_change_ms module called
EN_TIME_ALL_PKTS.
Set to 1, the module will calculate timestamps
for all packets of the output burst.
Set to 0, the module will only insert a timestamp in the first
pkt of each generated output burst.
