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fpga: lib: rfnoc: Merge payload and async FIFO
Merge the payload and async FIFOs in the axis_data_to_chdr and chdr_to_axis_data conversion conversion modules.
This commit is contained in:
Max Köhler
mkoop-ni
parent
2ff1a639eb
commit
a9ddd67fb9
@ -324,20 +324,22 @@ module axis_data_to_chdr #(
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// Transfer packet payload between clock domains:
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// in_pyld_* (axis_data_clk) to out_pyld_* (axis_chdr_clk)
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if (NIPC != CHDR_W/ITEM_W) begin : gen_axis_width_conv
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wire [CHDR_W-1:0] pyld_resize_tdata;
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wire pyld_resize_tlast;
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wire pyld_resize_tvalid;
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wire pyld_resize_tready;
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// Do the width conversion and clock crossing in the axis_width_conv
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// module to ensure that the resize happens on the correct side of the
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// clock crossing.
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// PAYLOAD_FIFO_SIZE is specified in log2 of the number of CHDR words. The axis_width_conv
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// module expects the FIFO size in log2 of WORD_W. Add the output ratio to
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// the logarithmic FIFO size to get the correct FIFO size in log2 of WORD_W.
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localparam integer PAYLOAD_FIFO_SIZE_WORD = PAYLOAD_FIFO_SIZE + $clog2(CHDR_W/ITEM_W);
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axis_width_conv #(
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.WORD_W (ITEM_W),
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.IN_WORDS (NIPC),
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.OUT_WORDS (CHDR_W/ITEM_W),
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.SYNC_CLKS (SYNC_CLKS),
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.PIPELINE ("IN")
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.PIPELINE ("IN"),
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.FIFO_SIZE (PAYLOAD_FIFO_SIZE_WORD)
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) payload_width_conv_i (
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.s_axis_aclk (axis_data_clk),
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.s_axis_rst (axis_data_rst),
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@ -348,28 +350,11 @@ module axis_data_to_chdr #(
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.s_axis_tready (in_pyld_tready),
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.m_axis_aclk (axis_chdr_clk),
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.m_axis_rst (axis_chdr_rst),
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.m_axis_tdata (pyld_resize_tdata),
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.m_axis_tdata (out_pyld_tdata),
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.m_axis_tkeep (),
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.m_axis_tlast (pyld_resize_tlast),
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.m_axis_tvalid (pyld_resize_tvalid),
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.m_axis_tready (pyld_resize_tready)
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);
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axi_fifo #(
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.WIDTH (CHDR_W+1),
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.SIZE (PAYLOAD_FIFO_SIZE)
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) pyld_fifo (
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.clk (axis_chdr_clk),
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.reset (axis_chdr_rst),
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.clear (1'b0),
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.i_tdata ({pyld_resize_tlast, pyld_resize_tdata}),
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.i_tvalid (pyld_resize_tvalid),
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.i_tready (pyld_resize_tready),
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.o_tdata ({out_pyld_tlast, out_pyld_tdata}),
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.o_tvalid (out_pyld_tvalid),
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.o_tready (out_pyld_tready),
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.space (),
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.occupied ()
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.m_axis_tlast (out_pyld_tlast),
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.m_axis_tvalid (out_pyld_tvalid),
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.m_axis_tready (out_pyld_tready)
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);
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end else begin : no_gen_axis_width_conv
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if (SYNC_CLKS) begin : gen_sync_pyld_fifo
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@ -7,12 +7,12 @@
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//
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// Description:
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//
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// A deframer module for CHDR data packets. It accepts an input CHDR stream
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// and produces an output data stream that includes the payload of the
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// packet, as well as timestamp and packet flags presented as sideband
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// A deframer module for CHDR data packets. It accepts an input CHDR stream
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// and produces an output data stream that includes the payload of the
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// packet, as well as timestamp and packet flags presented as sideband
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// information.
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//
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// This module also performs an optional clock crossing and data width
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// This module also performs an optional clock crossing and data width
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// conversion from CHDR_W to a user requested width for the payload data bus.
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//
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// Parameters:
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@ -243,23 +243,23 @@ module chdr_to_axis_data #(
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assign in_pyld_tvalid = in_chdr_tvalid && (state == ST_BODY);
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always @(*) begin
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// Packet timestamp and flags go into the info FIFO, but only if it's a
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// Packet timestamp and flags go into the info FIFO, but only if it's a
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// data packet since non-data packets will be discarded.
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if (CHDR_W > 64) begin
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// When CHDR_W > 64, all info will be in the first word of the CHDR packet
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in_info_tdata = { in_chdr_tdata[127:64],
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in_info_tdata = { in_chdr_tdata[127:64],
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chdr_get_has_time(in_chdr_tdata),
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chdr_calc_payload_length(CHDR_W, in_chdr_tdata),
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chdr_get_eob(in_chdr_tdata),
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chdr_get_eov(in_chdr_tdata) };
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in_info_tvalid = in_chdr_tvalid && (state == ST_HDR &&
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in_info_tvalid = in_chdr_tvalid && (state == ST_HDR &&
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(in_pkt_type == CHDR_PKT_TYPE_DATA || in_pkt_type == CHDR_PKT_TYPE_DATA_TS));
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end else begin
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// When CHDR_W == 64, the flags will be in the first word of the packet,
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// When CHDR_W == 64, the flags will be in the first word of the packet,
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// but the timestamp will be in the second word, if there is a timestamp.
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if (state == ST_HDR && in_pkt_type == CHDR_PKT_TYPE_DATA) begin
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// No timestamp in this case
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in_info_tdata = { in_chdr_tdata[63:0], 1'b0,
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in_info_tdata = { in_chdr_tdata[63:0], 1'b0,
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chdr_calc_payload_length(CHDR_W, in_chdr_tdata),
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chdr_get_eob(in_chdr_tdata), chdr_get_eov(in_chdr_tdata) };
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in_info_tvalid = in_chdr_tvalid;
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@ -284,10 +284,6 @@ module chdr_to_axis_data #(
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// ---------------------------------------------------
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// Payload and Sideband Data FIFOs
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// ---------------------------------------------------
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wire [CHDR_W-1:0] out_pyld_tdata;
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wire [CHDR_KEEP_W-1:0] out_pyld_tkeep;
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wire out_pyld_tlast, out_pyld_tvalid, out_pyld_tready;
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wire [INFO_W-1:0] out_info_tdata;
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wire out_info_tvalid, out_info_tready;
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@ -318,29 +314,25 @@ module chdr_to_axis_data #(
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.o_tvalid(out_info_tvalid), .o_tready(out_info_tready)
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);
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end
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// Payload FIFOs
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if (CHDR_W != ITEM_W*NIPC) begin : gen_axis_width_conv
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axi_fifo #(.WIDTH(CHDR_W+CHDR_KEEP_W+1), .SIZE(PYLD_FIFO_SIZE)) pyld_fifo_i (
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.clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
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.i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
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.i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
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.o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
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.o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready),
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.space(), .occupied()
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);
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// Do the width conversion and clock crossing in the axis_width_conv
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// module to ensure that the resize happens on the correct side of the
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// clock crossing.
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// PYLD_FIFO_SIZE is specified in log2 of the number of CHDR words. The axis_width_conv
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// module expects the FIFO size in log2 of WORD_W. Add the input ratio to
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// the logarithmic FIFO size to get the correct FIFO size in log2 of WORD_W.
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localparam integer PYLD_FIFO_SIZE_WORD = PYLD_FIFO_SIZE + $clog2(CHDR_W/ITEM_W);
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axis_width_conv #(
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.WORD_W(ITEM_W), .IN_WORDS(CHDR_W/ITEM_W), .OUT_WORDS(NIPC),
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.SYNC_CLKS(SYNC_CLKS), .PIPELINE("NONE")
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.SYNC_CLKS(SYNC_CLKS), .PIPELINE("NONE"), .FIFO_SIZE(PYLD_FIFO_SIZE_WORD)
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) payload_width_conv_i (
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.s_axis_aclk(axis_chdr_clk), .s_axis_rst(axis_chdr_rst),
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.s_axis_tdata(out_pyld_tdata), .s_axis_tkeep(out_pyld_tkeep),
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.s_axis_tlast(out_pyld_tlast), .s_axis_tvalid(out_pyld_tvalid),
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.s_axis_tready(out_pyld_tready),
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.s_axis_tdata(in_pyld_tdata), .s_axis_tkeep(in_pyld_tkeep),
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.s_axis_tlast(in_pyld_tlast), .s_axis_tvalid(in_pyld_tvalid),
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.s_axis_tready(in_pyld_tready),
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.m_axis_aclk(axis_data_clk), .m_axis_rst(axis_data_rst),
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.m_axis_tdata(conv_pyld_tdata), .m_axis_tkeep(conv_pyld_tkeep),
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.m_axis_tlast(conv_pyld_tlast), .m_axis_tvalid(conv_pyld_tvalid),
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@ -352,8 +344,8 @@ module chdr_to_axis_data #(
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.clk(axis_chdr_clk), .reset(axis_chdr_rst), .clear(1'b0),
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.i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
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.i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
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.o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
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.o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready),
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.o_tdata({conv_pyld_tlast, conv_pyld_tkeep, conv_pyld_tdata}),
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.o_tvalid(conv_pyld_tvalid), .o_tready(conv_pyld_tready),
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.space(), .occupied()
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);
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end else begin : gen_async_pyld_fifo
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@ -363,17 +355,10 @@ module chdr_to_axis_data #(
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.i_tdata({in_pyld_tlast, in_pyld_tkeep, in_pyld_tdata}),
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.i_tvalid(in_pyld_tvalid), .i_tready(in_pyld_tready),
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.o_aclk(axis_data_clk),
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.o_tdata({out_pyld_tlast, out_pyld_tkeep, out_pyld_tdata}),
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.o_tvalid(out_pyld_tvalid), .o_tready(out_pyld_tready)
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.o_tdata({conv_pyld_tlast, conv_pyld_tkeep, conv_pyld_tdata}),
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.o_tvalid(conv_pyld_tvalid), .o_tready(conv_pyld_tready)
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);
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end
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// No width conversion needed
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assign conv_pyld_tdata = out_pyld_tdata;
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assign conv_pyld_tkeep = out_pyld_tkeep;
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assign conv_pyld_tlast = out_pyld_tlast;
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assign conv_pyld_tvalid = out_pyld_tvalid;
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assign out_pyld_tready = conv_pyld_tready;
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end
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endgenerate
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@ -428,7 +413,7 @@ module chdr_to_axis_data #(
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.s_axis_tlast(flush_tlast),
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.s_axis_tvalid(flush_tvalid),
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.s_axis_tready(flush_tready),
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.m_axis_tdata({m_axis_ttimestamp, m_axis_thas_time, m_axis_tlength,
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.m_axis_tdata({m_axis_ttimestamp, m_axis_thas_time, m_axis_tlength,
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m_axis_teob, m_axis_teov, m_axis_tkeep, m_axis_tdata}),
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.m_axis_tlast(m_axis_tlast),
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.m_axis_tvalid(m_axis_tvalid),
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