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fpga: b310: update jtag prescalar

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Javier Valenzuela 2026-08-12 23:04:34 -05:00 committed by Wade Fife
parent 8745af720e
commit c17c6a4c3a
1 changed files with 1 additions and 1 deletions
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fpga/usrp3/top/b300/core/b310_core.sv
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@ -829,7 +829,7 @@ module b310_core # (
ctrlport_to_jtag #(
.BASE_ADDRESS (CPLD_JTAG_WINDOW),
.DEFAULT_PRESCALAR (32)
.DEFAULT_PRESCALAR (12)
) cpld_jtag_ctrl (
.ctrlport_clk (bus_clk),
.ctrlport_rst (bus_rst),