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Niels Garibaldi 9365ae9b6a fpga: dsp: reverse order of cic barrel shifter 
Reversing the order of the barrel shifter module used by the CIC
filter implementations, in order to reduce the possible bits
selectable from the last stage going into the rounding module.
This should make routing easier.
2026-09-15 23:47:05 +01:00
..
.ci ci: apply target name for X420 FPGA compiles 2026-08-28 16:06:17 +01:00
usrp1 Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
usrp2 fpga: Fix check_timing.py break indent 2026-09-02 09:40:20 +02:00
usrp3 fpga: dsp: reverse order of cic barrel shifter 2026-09-15 23:47:05 +01:00
.clang-format fpga: Clear clang-format settings for FPGA code 2023-08-17 10:51:55 -05:00
.gitignore fpga: Add more spurious files to gitignore 2023-12-13 17:28:09 -06:00
CODING.md fpga: Update recommended HDL header guideline 2021-06-10 11:56:58 -05:00
CONTRIBUTING.md Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
README.md docs: Fix FPGA readme (Doxygen link) 2026-05-11 15:26:30 +02:00

README.md

Ettus Research USRP FPGA HDL Source

Welcome to the USRP FPGA HDL source code tree! This repository contains free & open-source FPGA HDL for the Universal Software Radio Peripheral (USRP™) SDR platform, created and sold by Ettus Research. A large percentage of the source code is written in Verilog.

Product Generations

This repository contains the FPGA source for the following generations of USRP devices.

Generation 1

  • Directory: usrp1
  • Devices: USRP Classic Only
  • Tools: Quartus from Altera
  • Build Instructions

Generation 2

Generation 3

  • Directory: usrp3
  • Devices: USRP B2X0, USRP X Series, USRP E3X0, USRP N3xx
  • Tools: Vivado from Xilinx, ISE from Xilinx, GNU make
  • Build Instructions
  • Simulation

Pre-built FPGA Images

Pre-built FPGA and Firmware images are not hosted here. Please visit the FPGA and Firmware manual page for instructions on downloading and using pre-built images. In most cases, running the following command will do the right thing.

$ uhd_images_downloader

Building This Manual

This FPGA manual is now fully integrated into the UHD manual and is built as part of the UHD build process.