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fpga: add wideband ddc and duc blocks to default fpga images(Part2)
Adding the RFNoC DDC and DUC blocks to our shipping bitfiles. The new wideband DxC implementation allow processing input/output rates up to a maximum of 2000MSps. This commit adds the DDC/DUC blocks to some of our shipping bitfiles for all channels. Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com> Co-authored-by: André Zoch <andre.zoch@emerson.com> Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Max Köhler <max.koehler@emerson.com>
This commit is contained in:
Niels Garibaldi
mkoop-ni
parent
c0be7431c0
commit
6ab55e0cf4
@ -72,6 +72,26 @@ noc_blocks:
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EN_FIFO_OUT_REG: 1
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CTRL_FIFO_SIZE: 1024
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CTRL_OUT_FIFO_SIZE: 1024
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duc0:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 1
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NIPC: 4
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duc1:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 1
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NIPC: 4
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 1
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NIPC: 4
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ddc1:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 1
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NIPC: 4
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replay0:
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block_desc: 'replay.yml'
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parameters:
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@ -94,13 +114,17 @@ noc_blocks:
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# - dstport = Port on the destination block to connect
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connections:
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# RF A:0 TX
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- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
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- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A:0 RX
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- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF B:0 TX
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- { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 }
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- { srcblk: ep1, srcport: out0, dstblk: duc1, dstport: in_0 }
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- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
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# RF B:0 RX
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- { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 }
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- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
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- { srcblk: ddc1, srcport: out_0, dstblk: ep1, dstport: in0 }
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# Replay Connections
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- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
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@ -123,6 +147,10 @@ connections:
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
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- { srcblk: _device_, srcport: fast_ce, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: fast_ce, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: fast_ce, dstblk: duc1, dstport: ce }
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- { srcblk: _device_, srcport: fast_ce, dstblk: ddc1, dstport: ce }
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
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# Other clock domains are inherited from YAML include files
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128
fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml
Normal file
128
fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml
Normal file
@ -0,0 +1,128 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2026 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 512 # Bit width of the CHDR bus for this image
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device: 'x420' # USRP type
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image_core_name: 'usrp_x420_fpga_CG_1000' # Name to use for the generated output files
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default_target: 'X420' # Default make target
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inherit:
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- 'yaml_include/x440_radio_base.yml'
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- 'yaml_include/x4xx_cg_base.yml'
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parameters:
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ENABLE_DRAM: True
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NUM_DRAM_BANKS: 2
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NUM_DRAM_CHANS: 2
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DRAM_WIDTH: 512
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 2097152 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 2097152
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 131072
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 131072
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# A table of which crossbar routes to include
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# -------------------------------------------
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# Rows correspond to input ports and columns correspond to output ports.
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# Entering a 1 includes and a 0 removes that route from the crossbar.
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crossbar_routes:
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# eth0 dma ep1 ep3
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# eth1 ep0 ep2
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- [ 1, 0, 0, 1, 1, 1, 1 ] # eth0 (QSFP Port 0)
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- [ 0, 1, 0, 1, 1, 1, 1 ] # eth1 (QSFP Port 1)
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- [ 0, 0, 1, 1, 1, 1, 1 ] # dma
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- [ 1, 1, 1, 0, 0, 1, 1 ] # ep0 (radio0.0)
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- [ 1, 1, 1, 0, 0, 1, 1 ] # ep1 (radio1.0)
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- [ 1, 1, 1, 1, 1, 0, 0 ] # ep2 (replay0.0)
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- [ 1, 1, 1, 1, 1, 0, 0 ] # ep3 (replay1.0)
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 1
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EN_FIFO_OUT_REG: 1
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CTRL_FIFO_SIZE: 1024
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CTRL_OUT_FIFO_SIZE: 1024
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 1
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EN_FIFO_OUT_REG: 1
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CTRL_FIFO_SIZE: 1024
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CTRL_OUT_FIFO_SIZE: 1024
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 1
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MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above
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MEM_ADDR_W: 32
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replay1:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 1
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MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above
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MEM_ADDR_W: 32
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A:0 TX
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- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
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# RF A:0 RX
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- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF B:0 TX
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- { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 }
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# RF B:0 RX
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- { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 }
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# Replay Connections
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- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
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- { srcblk: ep3, srcport: out0, dstblk: replay1, dstport: in_0 }
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- { srcblk: replay1, srcport: out_0, dstblk: ep3, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
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- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
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# Front-Panel GPIO
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- { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio0 }
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- { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio1 }
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# Other BSP connections are inherited from YAML include files
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
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# Other clock domains are inherited from YAML include files
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@ -18,3 +18,19 @@ inherit:
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parameters:
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RF_BW: 400
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noc_blocks:
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duc0:
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parameters:
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NIPC: 2
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duc1:
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parameters:
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NIPC: 2
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ddc0:
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parameters:
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NIPC: 2
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ddc1:
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parameters:
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NIPC: 2
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20
fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml
Normal file
20
fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml
Normal file
@ -0,0 +1,20 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2026 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 512 # Bit width of the CHDR bus for this image
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device: 'x420' # USRP type
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image_core_name: 'usrp_x420_fpga_CG_400' # Name to use for the generated output files
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default_target: 'X420' # Default make target
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# This image is identical to the 1000 MHz image, except for the RF bandwidth,
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# which is achieved by adding resamplers with fixed factor of 3 in the RF data
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# path
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inherit:
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- 'x420_CG_1000_woDDC_rfnoc_image_core.yml'
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parameters:
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RF_BW: 400
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