diff --git a/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml index d49faa3ab..e927f02cd 100644 --- a/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml @@ -72,6 +72,26 @@ noc_blocks: EN_FIFO_OUT_REG: 1 CTRL_FIFO_SIZE: 1024 CTRL_OUT_FIFO_SIZE: 1024 + duc0: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 replay0: block_desc: 'replay.yml' parameters: @@ -94,13 +114,17 @@ noc_blocks: # - dstport = Port on the destination block to connect connections: # RF A:0 TX - - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } # RF A:0 RX - - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } # RF B:0 TX - - { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 } + - { srcblk: ep1, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } # RF B:0 RX - - { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 } + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep1, dstport: in0 } # Replay Connections - { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 } - { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 } @@ -123,6 +147,10 @@ connections: # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect clk_domains: - - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } - - { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem } + - { srcblk: _device_, srcport: fast_ce, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: fast_ce, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: fast_ce, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: fast_ce, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem } # Other clock domains are inherited from YAML include files diff --git a/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml new file mode 100644 index 000000000..d49faa3ab --- /dev/null +++ b/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml @@ -0,0 +1,128 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2026 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 512 # Bit width of the CHDR bus for this image +device: 'x420' # USRP type +image_core_name: 'usrp_x420_fpga_CG_1000' # Name to use for the generated output files +default_target: 'X420' # Default make target +inherit: + - 'yaml_include/x440_radio_base.yml' + - 'yaml_include/x4xx_cg_base.yml' + +parameters: + ENABLE_DRAM: True + NUM_DRAM_BANKS: 2 + NUM_DRAM_CHANS: 2 + DRAM_WIDTH: 512 + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size_bytes: 2097152 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 2097152 + ep2: + ctrl: False + data: True + buff_size_bytes: 131072 + ep3: + ctrl: False + data: True + buff_size_bytes: 131072 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 dma ep1 ep3 + # eth1 ep0 ep2 + - [ 1, 0, 0, 1, 1, 1, 1 ] # eth0 (QSFP Port 0) + - [ 0, 1, 0, 1, 1, 1, 1 ] # eth1 (QSFP Port 1) + - [ 0, 0, 1, 1, 1, 1, 1 ] # dma + - [ 1, 1, 1, 0, 0, 1, 1 ] # ep0 (radio0.0) + - [ 1, 1, 1, 0, 0, 1, 1 ] # ep1 (radio1.0) + - [ 1, 1, 1, 1, 1, 0, 0 ] # ep2 (replay0.0) + - [ 1, 1, 1, 1, 1, 0, 0 ] # ep3 (replay1.0) + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + EN_FIFO_OUT_REG: 1 + CTRL_FIFO_SIZE: 1024 + CTRL_OUT_FIFO_SIZE: 1024 + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + EN_FIFO_OUT_REG: 1 + CTRL_FIFO_SIZE: 1024 + CTRL_OUT_FIFO_SIZE: 1024 + replay0: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 1 + MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above + MEM_ADDR_W: 32 + replay1: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 1 + MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above + MEM_ADDR_W: 32 + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF A:0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF B:0 TX + - { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 } + # Replay Connections + - { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 } + - { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 } + - { srcblk: ep3, srcport: out0, dstblk: replay1, dstport: in_0 } + - { srcblk: replay1, srcport: out_0, dstblk: ep3, dstport: in0 } + # + # BSP Connections + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 } + - { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 } + # Front-Panel GPIO + - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio0 } + - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio1 } + # Other BSP connections are inherited from YAML include files + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem } + # Other clock domains are inherited from YAML include files diff --git a/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml index 07ffb6137..f93cfb5c4 100644 --- a/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml @@ -18,3 +18,19 @@ inherit: parameters: RF_BW: 400 + +noc_blocks: + duc0: + parameters: + NIPC: 2 + duc1: + parameters: + NIPC: 2 + ddc0: + parameters: + NIPC: 2 + ddc1: + parameters: + NIPC: 2 + + diff --git a/fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml new file mode 100644 index 000000000..4f1ef7934 --- /dev/null +++ b/fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml @@ -0,0 +1,20 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2026 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 512 # Bit width of the CHDR bus for this image +device: 'x420' # USRP type +image_core_name: 'usrp_x420_fpga_CG_400' # Name to use for the generated output files +default_target: 'X420' # Default make target +# This image is identical to the 1000 MHz image, except for the RF bandwidth, +# which is achieved by adding resamplers with fixed factor of 3 in the RF data +# path +inherit: + - 'x420_CG_1000_woDDC_rfnoc_image_core.yml' + +parameters: + RF_BW: 400