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fpga: b310: removed unused revision reg

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This commit is contained in:
Javier Valenzuela 2026-08-06 10:08:19 -05:00 committed by Wade Fife
parent 984bc86793
commit 9849f85918
3 changed files with 18 additions and 160 deletions
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15
fpga/usrp3/top/b300/core/basic_regs.sv
View File

@ -144,7 +144,6 @@ endmodule
// please refer to the register map documentation accordingly:
// <li> Current version: @.BASIC_REGS_REGMAP..CORE_REVISION
// <li> Oldest compatible version: @.BASIC_REGS_REGMAP..CORE_OLDEST_REVISION
// <li> Version last modified: @.BASIC_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="BOARD_ID_VALUE" integer="0xB310"/>
// <value name="FPGA_CURRENT_VERSION_MAJOR" integer="2"/>
@ -153,7 +152,6 @@ endmodule
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="2"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x26061611"/>
// </enumeratedtype>
//
// <register name="CORE_SIGNATURE" size="32" offset="0x00" attributes="Readable">
@ -210,19 +208,6 @@ endmodule
// </bitfield>
// </register>
//
// <register name="VERSION_LAST_MODIFIED" size="32" offset="0x0C" attributes="Readable">
// <info>
// This register contains the date/time when the version was last modified.
// The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
// </info>
// <bitfield name="YY" range="31..24">
// <info>This is the year number after 2000 (e.g. 2019 = 0x19).</info>
// </bitfield>
// <bitfield name="MM" range="23..16"/>
// <bitfield name="DD" range="15..8"/>
// <bitfield name="HH" range="7..0"/>
// </register>
//
// <register name="CORE_SCRATCH" size="32" offset="0x10" attributes="Readable|Writable">
// <info>
// Read/write scratch register

132
fpga/usrp3/top/b300/doc/B310_FPGA.htm
View File

@ -535,11 +535,6 @@ p.offset_info, td.offset_info {
</p>
<p>
<a class="register" href="#BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
</p>
<p>
<a class="register" href="#BASIC_REGS_REGMAP|CORE_SCRATCH">CORE_SCRATCH</a>
</p>
@ -1400,7 +1395,6 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
please refer to the register map documentation accordingly:
<li> Current version: <a href="#BASIC_REGS_REGMAP|CORE_REVISION">CORE_REVISION</a>
<li> Oldest compatible version: <a href="#BASIC_REGS_REGMAP|CORE_OLDEST_REVISION">CORE_OLDEST_REVISION</a>
<li> Version last modified: <a href="#BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
@ -1415,7 +1409,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">0</td>
<td class="l">0x00000000</td>
<td class="l">0x0000</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_BUILD"></a>
@ -1428,7 +1422,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">0</td>
<td class="l">0x00000000</td>
<td class="l">0x0000</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR"></a>
@ -1441,7 +1435,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">0</td>
<td class="l">0x00000000</td>
<td class="l">0x0000</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD"></a>
@ -1454,7 +1448,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">1</td>
<td class="l">0x00000001</td>
<td class="l">0x0001</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR"></a>
@ -1467,7 +1461,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">2</td>
<td class="l">0x00000002</td>
<td class="l">0x0002</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MAJOR"></a>
@ -1480,7 +1474,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">2</td>
<td class="l">0x00000002</td>
<td class="l">0x0002</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR"></a>
@ -1493,7 +1487,7 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<td class="value">45840</td>
<td class="l">0x0000B310</td>
<td class="l">0xB310</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|BOARD_ID_VALUE"></a>
@ -1502,19 +1496,6 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
</td>
</tr>
<tr valign="top">
<td class="value">637933073</td>
<td class="l">0x26061611</td>
<td class="l" style="text-align: left;">
<p class="name">
<a name="BASIC_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME"></a>
FPGA_VERSION_LAST_MODIFIED_TIME
</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file basic_regs.sv.
@ -1774,98 +1755,6 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
<section class="register">
<a name="BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED"></a>
<h3 class="register">
Offset 0x000C: VERSION_LAST_MODIFIED
Register
(R)
<a href="#BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED">&#x1F517;</a>
</h3>
<div class="sh">
<span class="opener sh-addrs">(<span class="sh-hidden">show</span><span class="sh-shown">hide</span> extended info)</span>
<div class="sh-content">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#B310_BAR0_REGMAP|BASIC_REGS_WINDOW">B310_BAR0_REGMAP|BASIC_REGS_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">VERSION_LAST_MODIFIED</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr>
<td class="offset_info">Total Offset =</td>
<td class="offset_info">0x00000C</td>
</tr>
</table>
</td>
</tr>
</table>
<p class="reg_info">
Initial Value not specified
</p>
<p class="reg_info">
This register is defined in HDL source file basic_regs.sv.
</p>
</div>
</div>
<div class="info">
This register contains the date/time when the version was last modified.
The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr class="" valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED|YY"></a>YY</span><span class="attr">&nbsp;&nbsp;&nbsp;</span></p>
<p>This is the year number after 2000 (e.g. 2019 = 0x19).</p>
</td>
</tr>
<tr class="byte" valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED|MM"></a>MM</span><span class="attr">&nbsp;&nbsp;&nbsp;</span></p>
<p></p>
</td>
</tr>
<tr class="byte" valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED|DD"></a>DD</span><span class="attr">&nbsp;&nbsp;&nbsp;</span></p>
<p></p>
</td>
</tr>
<tr class="byte" valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="BASIC_REGS_REGMAP|VERSION_LAST_MODIFIED|HH"></a>HH</span><span class="attr">&nbsp;&nbsp;&nbsp;</span></p>
<p></p>
</td>
</tr>
</table>
</section>
<section class="register">
<a name="BASIC_REGS_REGMAP|CORE_SCRATCH"></a>
@ -2905,7 +2794,8 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
</div>
</div>
<div class="info">
Holds the lower 32 bits of the current radio time. Read the LOW register followed by the HIGH register to get a coherent 64-bit value.
Holds the lower 32 bits of the current radio time. Read the LOW
register followed by the HIGH register to get a coherent 64-bit value.
</div>
</section>
@ -2960,7 +2850,9 @@ For information on NI trademark guidelines, please see <a href="http://www.ni.co
</div>
</div>
<div class="info">
Holds the upper 32 bits of the radio time from when the LOW register was read. Read the LOW register followed by the HIGH register to get a coherent 64-bit value.
Holds the upper 32 bits of the radio time from when the LOW register
was read. Read the LOW register followed by the HIGH register to get a
coherent 64-bit value.
</div>
</section>

31
fpga/usrp3/top/b300/regmap/basic_regs_regmap_utils.vh
View File

@ -14,12 +14,11 @@
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// CORE_SIGNATURE : 0x0 (basic_regs.sv)
// CORE_REVISION : 0x4 (basic_regs.sv)
// CORE_OLDEST_REVISION : 0x8 (basic_regs.sv)
// VERSION_LAST_MODIFIED : 0xC (basic_regs.sv)
// CORE_SCRATCH : 0x10 (basic_regs.sv)
// GIT_HASH_REGISTER : 0x14 (basic_regs.sv)
// CORE_SIGNATURE : 0x0 (basic_regs.sv)
// CORE_REVISION : 0x4 (basic_regs.sv)
// CORE_OLDEST_REVISION : 0x8 (basic_regs.sv)
// CORE_SCRATCH : 0x10 (basic_regs.sv)
// GIT_HASH_REGISTER : 0x14 (basic_regs.sv)
//===============================================================================
// RegTypes
@ -30,7 +29,7 @@
//===============================================================================
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 8;
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
@ -38,7 +37,6 @@
localparam FPGA_CURRENT_VERSION_MAJOR = 'h2; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h2; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam BOARD_ID_VALUE = 'hB310; // FPGA_VERSION:BOARD_ID_VALUE
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h26061611; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// CORE_SIGNATURE Register (from basic_regs.sv)
localparam CORE_SIGNATURE = 'h0; // Register Offset
@ -76,23 +74,6 @@
localparam OLDEST_REVISION_MAJOR_MSB = 31; //CORE_OLDEST_REVISION:OLDEST_REVISION_MAJOR
localparam OLDEST_REVISION_MAJOR = 24; //CORE_OLDEST_REVISION:OLDEST_REVISION_MAJOR
// VERSION_LAST_MODIFIED Register (from basic_regs.sv)
localparam VERSION_LAST_MODIFIED = 'hC; // Register Offset
localparam VERSION_LAST_MODIFIED_SIZE = 32; // register width in bits
localparam VERSION_LAST_MODIFIED_MASK = 32'hFFFFFFFF;
localparam HH_SIZE = 8; //VERSION_LAST_MODIFIED:HH
localparam HH_MSB = 7; //VERSION_LAST_MODIFIED:HH
localparam HH = 0; //VERSION_LAST_MODIFIED:HH
localparam DD_SIZE = 8; //VERSION_LAST_MODIFIED:DD
localparam DD_MSB = 15; //VERSION_LAST_MODIFIED:DD
localparam DD = 8; //VERSION_LAST_MODIFIED:DD
localparam MM_SIZE = 8; //VERSION_LAST_MODIFIED:MM
localparam MM_MSB = 23; //VERSION_LAST_MODIFIED:MM
localparam MM = 16; //VERSION_LAST_MODIFIED:MM
localparam YY_SIZE = 8; //VERSION_LAST_MODIFIED:YY
localparam YY_MSB = 31; //VERSION_LAST_MODIFIED:YY
localparam YY = 24; //VERSION_LAST_MODIFIED:YY
// CORE_SCRATCH Register (from basic_regs.sv)
localparam CORE_SCRATCH = 'h10; // Register Offset
localparam CORE_SCRATCH_SIZE = 32; // register width in bits