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fpga: lib: move ctrlport_to_jtag to lib sirectory

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This commit is contained in:
Javier Valenzuela 2026-08-06 09:53:43 -05:00 committed by Wade Fife
parent c17c6a4c3a
commit a9aed26306
6 changed files with 27 additions and 9 deletions
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28
.ci/hwtools/X410/vsmakesettings.py
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@ -7,11 +7,13 @@
from hwtools.api import vapi
def do_options():
vapi.set_project_name(name="X410_FPGA", pretty_name="USRP X410 FPGA")
vapi.set_top_sim_entity("x4xx")
vapi.set_top_synth_entity("x4xx")
def do_files():
# x400 related files
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400", tree=False)
@ -23,17 +25,28 @@ def do_files():
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/rf/100m")
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/rf/200m")
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/rf/400m")
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap")
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap")
vapi.find_files_and_add_to_fileset(
base="repo", path="fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap"
)
vapi.find_files_and_add_to_fileset(
base="repo", path="fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap"
)
# library
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/lib/rfnoc")
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/lib/control")
# regmap files
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/regmap", tree=False)
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/regmap/x410", tree=False)
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/cpld/regmap", tree=False)
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/cpld/regmap/x410", tree=False)
vapi.find_files_and_add_to_fileset(
base="repo", path="fpga/usrp3/top/x400/regmap/x410", tree=False
)
vapi.find_files_and_add_to_fileset(
base="repo", path="fpga/usrp3/top/x400/cpld/regmap", tree=False
)
vapi.find_files_and_add_to_fileset(
base="repo", path="fpga/usrp3/top/x400/cpld/regmap/x410", tree=False
)
# simulation files
vapi.find_files_and_add_to_fileset(base="repo", path="fpga/usrp3/top/x400/rf/sim")
@ -44,17 +57,22 @@ def do_files():
vapi.remove_from_fileset(".*lib/rfnoc/.*_tb")
vapi.remove_from_fileset("pll-v")
def do_preparse():
pass
def do_precompile():
pass
def do_presynth():
pass
def do_finish():
vapi.run_user_function(function="update_xmlparse_files", base="self", path="../common.py")
def vhook_warn_filter(msgstr):
return False

1
fpga/usrp3/lib/control/Makefile.srcs
View File

@ -75,6 +75,7 @@ ctrlport_to_regport.v \
ctrlport_to_wb_i2c.v \
ctrlport_to_wb_uart.v \
ctrlport_to_simple_spi.sv \
ctrlport_to_jtag.v \
glitch_free_mux.v \
regport_if.sv \
))

4
fpga/usrp3/top/x400/cpld/x410/ctrlport_to_jtag.v → fpga/usrp3/lib/control/ctrlport_to_jtag.v
View File

@ -49,8 +49,8 @@ module ctrlport_to_jtag #(
output wire tms
);
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "../regmap/jtag_regmap_utils.vh"
`include "../rfnoc/core/ctrlport.vh"
`include "jtag_regmap_utils.vh"
//---------------------------------------------------------------------------
// Local Registers

0
fpga/usrp3/top/x400/cpld/regmap/jtag_regmap_utils.vh → fpga/usrp3/lib/control/jtag_regmap_utils.vh
View File

1
fpga/usrp3/top/b300/Makefile.b310.inc
View File

@ -68,7 +68,6 @@ b310_xadc_wrapper.sv \
constraints/b310.xdc \
constraints/timing.xdc \
constraints/b310_dram.xdc \
../x400/cpld/x410/ctrlport_to_jtag.v \
../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd \

2
fpga/usrp3/top/x400/cpld/x410/quartus/mb_cpld.qsf
View File

@ -401,7 +401,7 @@ set_global_assignment -name SDC_FILE ../common/common.sdc
set_global_assignment -name SDC_FILE ../x410/db_spi_shared_constants.sdc
set_global_assignment -name SDC_FILE ../x410/mb_cpld.sdc
set_global_assignment -name VERILOG_FILE ../x410/mb_cpld.v -new_extractor
set_global_assignment -name VERILOG_FILE ../x410/ctrlport_to_jtag.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/ctrlport_to_jtag.v
set_global_assignment -name VERILOG_FILE ../common/reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../common/ctrlport_to_spi.v
set_global_assignment -name VERILOG_FILE ../common/pl_cpld_regs.v