For the multisample version of the DUC block, in order
to align with the singlesample behavior this changes the packet
generation in axi_rate_change_ms to only include the timestamp in
the first packet of each burst.
Add a parameter to the axi_rate_change_ms module called
EN_TIME_ALL_PKTS.
Set to 1, the module will calculate timestamps
for all packets of the output burst.
Set to 0, the module will only insert a timestamp in the first
pkt of each generated output burst.
Adding the RFNoC DDC and DUC blocks to our shipping bitfiles.
The new wideband DxC implementation allow processing input/output
rates up to a maximum of 2000MSps.
This commit adds the DDC/DUC blocks to some of our shipping
bitfiles for all channels.
Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com>
Co-authored-by: André Zoch <andre.zoch@emerson.com>
Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
Added variants for the DDC/DUC blocks that can process multiple
samples per cycle and can be used for bandwidths higher than
200Mhz.
This new feature is integrated into the existing RFNoC DDC/DUC
blocks. Depending on the Radio bandwidth specified for the USRP
variant, the DxC blocks will instantiate the existing singlesample
implementation(for FPGA image variants <= 200MHz) or instantiate
the multisample implementation(for FPGA image variants > 200MHz).
Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com>
Co-authored-by: André Zoch <andre.zoch@emerson.com>
Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
Previously it would round up the requested size to the nearest power of
two. Now it will attempt to match the size of the buffer to the
requested size, allowing more control over how many FPGA RAM resources
get consumed.
The axi_fifo_2clk module uses a generic FIFO macro from Xilinx. This allows
custom widths and depths to be specified. It removes the need for combinatorial
logic to connect multiple smaller IP blocks to form a wider data path FIFO.
Fix an issue in which the most-significant word could be overwritten
with cached data when ctrlport_reg_rw is used in coherent mode. Also
fix per-word byte-enable handling for wide registers.
Fix the coherent-read cache width in ctrlport_reg_ro to match the
padded register width.
Thanks to GitHub user NobleBrutus for pointing out the coherency bug
and suggesting a fix.
The following IP blocks are removed:
- lib/ip/complex_multiplier: This was only used in rfnoc-gain (but not
anymore).
- lib/ip/dds: This had been designed out a while ago.
- x300/ip/input_sample_fifo: This was also unused.
Unused IP is a drag on builds and Vivado upgrades.
Added two different behaviours for AXIS BFM when reset is asserted:
- TRUNCATE_PACKET: ignores the TREADY from the DUT and progresses
through the rest of the data in the current packet.
This was and still is the default behaviour.
- DISCARD_PACKET : discards the rest of the packet in-flight and
moves to the next one. This prevents partial
packets from the master persisting after a reset.
Replacing the synth target of the FPGA Makefiles with the normal "bin" flow
which ends after synthesis if desired. This aligns the build flows in case ILAs
want to be added.
Some testbenches were overwriting DESIGN_SRCS, but this gets
initialized in viv_sim_preamble.mak and overwriting it causes some
necessary files to be removed from the file list.
This adds support for block write, block read, and poll operations in
the AXIS-Ctrl endpoint.
A burst mode is also now supported, in which the READ or WRITE opcode
with NumData > 1 allows repeated reads or writes to the same address,
unlike block write/read, which auto-increments the address.
This change also removes the requirement for dummy data words to be
present in read request packets as well as write and sleep response
packets. This improves efficiency of the control interface, especially
for block and burst operations.
