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fpga: x4xx: add placement constraints

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Max Köhler 2026-06-03 14:04:54 +02:00 committed by Martin Braun
parent 4bf834a9a8
commit 16c3a3acc2
2 changed files with 30 additions and 1 deletions
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3
fpga/usrp3/top/x400/Makefile.x4xx.inc
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@ -161,7 +161,8 @@ constraints/pins/common.xdc \
constraints/timing/shared_constants.sdc \
constraints/timing/common.xdc \
constraints/pins/dram.xdc \
constraints/timing/dram.xdc
constraints/timing/dram.xdc \
constraints/placement/common.xdc
ifdef X410
MB_XDC += \

28
fpga/usrp3/top/x400/constraints/placement/common.xdc Normal file
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@ -0,0 +1,28 @@
#
# Copyright 2026 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Placement constraints for X4xx based devices.
#
# Restricting the placement of the RF modules per DB ensures a better compile
# success rate through the reduced routing congestion. The naming here matches
# RFNoC block names used within UHD's default FPGA yml files.
#
# move RF core 0, radio 0, ddc 0, duc0 to lower part of the FPGA die
create_pblock rf_path_0
add_cells_to_pblock rf_path_0 [get_cells [list {gen_rf_cores[0]*}]]
add_cells_to_pblock rf_path_0 [get_cells [list x4xx_core_i/rfnoc_image_core_i/*ddc0*]]
add_cells_to_pblock rf_path_0 [get_cells [list x4xx_core_i/rfnoc_image_core_i/*duc0*]]
add_cells_to_pblock rf_path_0 [get_cells [list x4xx_core_i/rfnoc_image_core_i/*radio0*]]
resize_pblock rf_path_0 -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y3}
# move RF core 1, radio 1, ddc 1, duc1 to upper part of the FPGA die
create_pblock rf_path_1
add_cells_to_pblock rf_path_1 [get_cells [list {gen_rf_cores[1]*}]]
add_cells_to_pblock rf_path_1 [get_cells [list x4xx_core_i/rfnoc_image_core_i/*ddc1*]]
add_cells_to_pblock rf_path_1 [get_cells [list x4xx_core_i/rfnoc_image_core_i/*duc1*]]
add_cells_to_pblock rf_path_1 [get_cells [list x4xx_core_i/rfnoc_image_core_i/*radio1*]]
resize_pblock rf_path_1 -add {CLOCKREGION_X0Y4:CLOCKREGION_X5Y7}