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mpm: x440: add fabric resampling to clock policy
Adjusting the MPM code to enable the correct generation of data_clk and data_clk_2x based on the fabric resampler rate. Further increasing the rfdc_clocks to match the desired higher sampling rates of the RFDC.
This commit is contained in:
Max Köhler
Martin Braun
parent
94dd1084f8
commit
4bf834a9a8
@ -464,7 +464,7 @@ class X440ClockPolicy(X4xxClockPolicy):
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def _read_converter_rates(self):
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"""Gets the converter rate.
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Gets the converter rate from the argument string, if it is given there,
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Gets the converter rate from the argument string, if it is given there,
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None otherwise.
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"""
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self.conv_rates = self.args.get("converter_rate")
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@ -545,14 +545,14 @@ class X440ClockPolicy(X4xxClockPolicy):
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# Calculate desired converter rate: If a converter rate was passed, check if
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# we can decimate from converter rate to master clock rate and if this converter rate
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# is within the valid range. If this is impossible, pick the converter rate automatically.
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div = desired_conv_rate / desired_mcr
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coerced_mcr = desired_mcr
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coerced_mcr = desired_mcr * self._extra_resampling
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div = desired_conv_rate / coerced_mcr
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if (
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div not in X4xxRfdcCtrl.RFDC_RESAMPLER
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or not X4xxRfdcCtrl.CONV_RATE_MIN <= desired_conv_rate <= X4xxRfdcCtrl.CONV_RATE_MAX
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or desired_mcr not in MCR_LMK_VCO
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or coerced_mcr not in MCR_LMK_VCO
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):
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coerced_mcr = min(sorted(MCR_LMK_VCO), key=lambda x: abs(x - desired_mcr))
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coerced_mcr = min(sorted(MCR_LMK_VCO), key=lambda x: abs(x - coerced_mcr))
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for div in sorted(X4xxRfdcCtrl.RFDC_RESAMPLER, reverse=True):
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if coerced_mcr * div <= X4xxRfdcCtrl.CONV_RATE_MAX:
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break
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@ -682,6 +682,14 @@ class X440ClockPolicy(X4xxClockPolicy):
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if len(master_clock_rates) < self.get_num_rates():
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master_clock_rates = [master_clock_rates[0]] * self.get_num_rates()
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# In case resamplers are present there is only 1 MCR allowed
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if len(master_clock_rates) > 1 and self._extra_resampling > 1:
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if master_clock_rates[0] != master_clock_rates[1]:
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raise ValueError(
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"X440 with resamplers only supports identical "
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"master clock rates on both DBs."
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)
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# Check if MCR meets BW
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for mcr in master_clock_rates:
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if not self._get_min_mcr() <= mcr <= self._get_max_mcr():
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@ -695,6 +703,8 @@ class X440ClockPolicy(X4xxClockPolicy):
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conv_rates = []
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for idx, mcr in enumerate(master_clock_rates):
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conv_rate = 0 if self.conv_rates is None else self.conv_rates[idx]
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# If extra_resampling is >1, then from this place on, mcr will be
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# the MCR multiplied by the extra resampling factor in the PL.
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mcr, cvr = self._match_mcrs(mcr, conv_rate)
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mcrs.append(mcr)
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conv_rates.append(cvr)
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@ -707,7 +717,7 @@ class X440ClockPolicy(X4xxClockPolicy):
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conv_rates[1] = conv_rates[0]
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# With these values check if we can do this in MMCM
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rfdc_rate = list(map(lambda x: int(x / (self._spc * self._extra_resampling)), mcrs))
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rfdc_rate = [int(x / self._spc) for x in mcrs]
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min_mmcm_vco_rate = lcm(rfdc_rate[0], rfdc_rate[1])
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# Inform user if we don't have an exact match
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if min_mmcm_vco_rate > X4xxRfdcCtrl.MMCM_VCO_MAX:
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@ -715,10 +725,11 @@ class X440ClockPolicy(X4xxClockPolicy):
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# Ensure we're falling back to converter rate 0, too
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conv_rates[1] = conv_rates[0]
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if mcrs != master_clock_rates:
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if mcrs != [mcr * self._extra_resampling for mcr in master_clock_rates]:
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self.log.warning(
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f"Unable to use desired master clock rate(s), using "
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f"{mcrs[0]/1e6} MHz for DB0 and {mcrs[1]/1e6} MHz for DB1."
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f"{mcrs[0]/self._extra_resampling/1e6} MHz for DB0 and "
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f"{mcrs[1]/self._extra_resampling/1e6} MHz for DB1."
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)
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if self.conv_rates is not None and self.conv_rates != conv_rates:
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self.log.warning(
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@ -726,16 +737,18 @@ class X440ClockPolicy(X4xxClockPolicy):
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f"{conv_rates[0]/1e6} MSps for DB0 "
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f"and {conv_rates[1]/1e6} MSps for DB1. Converter rate needs "
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f"to be a {X4xxRfdcCtrl.RFDC_RESAMPLER} multiple of the master "
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f"clock rates {mcrs[0]/1e6} MHz and {mcrs[1]/1e6} MHz "
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f"clock rates {mcrs[0]/self._extra_resampling/1e6} MHz and "
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f"{mcrs[1]/self._extra_resampling/1e6} MHz multiplied by the "
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f"extra resampling factor {self._extra_resampling}, "
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f"but additional clock constraints may limit this."
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)
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self.conv_rates = conv_rates
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return mcrs
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return [mcr / self._extra_resampling for mcr in mcrs]
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def get_config(self, ref_clock_freq, master_clock_rates):
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"""Returns a valid configuration based on the master clock rate.
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It uses the configuration where the RFDC_CLOCK/SPC is the closest to the MCR
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It uses the configuration where the RFDC_CLOCK/SPC is the closest to the MCR.
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This method is called after coerce_mcr() has run and - if necessary -
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rounded the MCR values, so will skip the checks here to save some time.
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"""
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@ -747,6 +760,8 @@ class X440ClockPolicy(X4xxClockPolicy):
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conv_rates = []
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for idx, mcr in enumerate(master_clock_rates):
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conv_rate = 0 if self.conv_rates is None else self.conv_rates[idx]
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# If extra_resampling is >1, then from this place on, mcr will be
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# the MCR multiplied by the extra resampling factor in the PL.
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mcr, cvr = self._match_mcrs(mcr, conv_rate)
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mcrs.append(mcr)
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conv_rates.append(cvr)
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@ -790,7 +805,7 @@ class X440ClockPolicy(X4xxClockPolicy):
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conv_rate % sysref_config["SYSREF_FREQ"] == 0.0 for conv_rate in conv_rates
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), "Converter Rate is not a multiple of the SysRef freq"
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rfdc_rate = list(map(lambda x: int(x / (self._spc * self._extra_resampling)), mcrs))
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rfdc_rate = list(map(lambda x: int(x / self._spc), mcrs))
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mmcm_input, mmcm_vco_rate = self._get_mmcm_rates(
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rfdc_rate, lmk_vco, sysref_config["SYSREF_FREQ"]
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)
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@ -799,7 +814,8 @@ class X440ClockPolicy(X4xxClockPolicy):
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if not mmcm_input or mmcm_input > lmk_vco:
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error_msg = (
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f"Unable to find a valid MMCM configuration for Master Clock Rate(s) "
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f"{mcrs[0]/1e6} MHz and {mcrs[1]/1e6} MHz. Please choose different "
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f"{mcrs[0]/self._extra_resampling/1e6} MHz and "
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f"{mcrs[1]/self._extra_resampling/1e6} MHz. Please choose different "
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f"Master Clock Rate(s)."
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)
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self.log.error(error_msg)
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@ -857,6 +873,8 @@ class X440ClockPolicy(X4xxClockPolicy):
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"r0_clk_2x": r0_clk2x,
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"r1_clk_2x": r1_clk2x,
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"prc": prc_out_div,
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"data_clk": r0_clk * self._extra_resampling,
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"data_clk_2x": r0_clk2x * self._extra_resampling,
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},
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"rfdc_configs": [RfdcConfig(**rfdc_cfg0), RfdcConfig(**rfdc_cfg1)],
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"spll_config": SpllConfig(**spll_cfg),
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