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fpga: rfnoc: Fix chdr_traffic_source in Questa

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Wade Fife 2026-06-23 19:38:13 -05:00 committed by Jörg Hofrichter
parent fdc57ca407
commit 831f2940d5
1 changed files with 9 additions and 2 deletions
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11
fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv
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@ -130,6 +130,13 @@ module chdr_traffic_source_sim #(
end
end
logic [WIDTH:0] fifo_idata;
logic [WIDTH:0] fifo_odata;
assign fifo_idata = {m_chdr.axis.tlast, m_chdr.axis.tdata};
assign post_fifo.tlast = fifo_odata[WIDTH];
assign post_fifo.tdata = fifo_odata[WIDTH-1:0];
// Capture packets in a really short FIFO (for backpressure)
axi_fifo #(
.WIDTH(WIDTH+1), .SIZE(MTU + 1)
@ -137,10 +144,10 @@ module chdr_traffic_source_sim #(
.clk (clk),
.reset (rst),
.clear (1'b0),
.i_tdata ({m_chdr.axis.tlast, m_chdr.axis.tdata}),
.i_tdata (fifo_idata),
.i_tvalid (m_chdr.axis.tvalid),
.i_tready (m_chdr.axis.tready),
.o_tdata ({post_fifo.tlast, post_fifo.tdata}),
.o_tdata (fifo_odata),
.o_tvalid (post_fifo.tvalid),
.o_tready (post_fifo.tready),
.space (),