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fpga: x400 add faster ce_clk variant

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Add a new faster ce clock called fast_ce to x4xx that runs at
333.33MHz.

Co-authored-by: Max Köhler <max.koehler@emerson.com>
This commit is contained in:
Niels Garibaldi 2026-07-29 13:58:52 +02:00 committed by mkoop-ni
parent e466f427fd
commit 66769905bb
5 changed files with 61 additions and 0 deletions
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53
fpga/usrp3/top/x400/x4xx.sv
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@ -558,6 +558,58 @@ module x4xx (
.I(ce_gen_clkout0)
);
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__333.33333______0.000______50.0_______88.896_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________200____________0.010
wire fast_ce_gen_clkfbout;
wire fast_ce_gen_clkout0;
wire fast_ce_clk;
PLLE4_ADV #(
.COMPENSATION ("AUTO" ),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1 ),
.CLKFBOUT_MULT (5 ),
.CLKFBOUT_PHASE (0.000 ),
.CLKOUT0_DIVIDE (3 ),
.CLKOUT0_PHASE (0.000 ),
.CLKOUT0_DUTY_CYCLE(0.500 ),
.CLKIN_PERIOD (5.000 )
) fast_ce_clk_gen_i (
.CLKFBOUT (fast_ce_gen_clkfbout),
.CLKOUT0 (fast_ce_gen_clkout0 ),
.CLKOUT0B ( ),
.CLKOUT1 ( ),
.CLKOUT1B ( ),
.CLKFBIN (fast_ce_gen_clkfbout),
.CLKIN (clk200 ),
.DADDR (7'h0 ),
.DCLK (1'b0 ),
.DEN (1'b0 ),
.DI (16'h0 ),
.DO ( ),
.DRDY ( ),
.DWE (1'b0 ),
.CLKOUTPHYEN(1'b0 ),
.CLKOUTPHY ( ),
.LOCKED ( ),
.PWRDWN (1'b0 ),
.RST (areset )
);
BUFG bufg_fast_ce_i (
.O(fast_ce_clk ),
.I(fast_ce_gen_clkout0)
);
//---------------------------------------------------------------------------
// PPS Handling
@ -3344,6 +3396,7 @@ module x4xx (
.rfnoc_ctrl_clk (clk40),
.rfnoc_ctrl_rst (clk40_rst),
.ce_clk (ce_clk),
.fast_ce_clk (fast_ce_clk),
.dram0_sys_clk_p (DRAM0_REFCLK_P),
.dram0_sys_clk_n (DRAM0_REFCLK_N),
.dram0_ck_t (DRAM0_CLK_P),

2
fpga/usrp3/top/x400/x4xx_core.v
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@ -53,6 +53,7 @@ module x4xx_core #(
input wire rfnoc_ctrl_rst,
input wire ce_clk,
input wire fast_ce_clk,
// DRAM Bank 0
input wire dram0_sys_clk_p,
@ -840,6 +841,7 @@ module x4xx_core #(
`endif
.dram_clk (dram_clk),
.ce_clk (ce_clk),
.fast_ce_clk (fast_ce_clk),
.device_id (device_id),
.dna (device_dna),
.m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]),

2
host/include/uhd/rfnoc/core/x410_bsp.yml
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@ -87,6 +87,8 @@ clocks:
index: 2
- name: ce
index: 3
- name: fast_ce
index: 9
- name: radio
index: 4
- name: radio_2x

2
host/include/uhd/rfnoc/core/x420_bsp.yml
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@ -83,6 +83,8 @@ clocks:
index: 2
- name: ce
index: 3
- name: fast_ce
index: 9
- name: radio0
index: 4
- name: radio1

2
host/include/uhd/rfnoc/core/x440_bsp.yml
View File

@ -99,6 +99,8 @@ clocks:
index: 2
- name: ce
index: 3
- name: fast_ce
index: 9
- name: radio0
index: 4
- name: radio1