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fpga: Add support for USRP B310
Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Tony Liecthy <tony.liechty@ni.com> Co-authored-by: Grant Meyerhoff <grant.meyerhoff@emerson.com> Co-authored-by: Christopher Oeltjen <christopher.oeltjen@emerson.com>
This commit is contained in:
Javier Valenzuela
Marian Koop
parent
2cde73ab6f
commit
b6286bab13
@ -88,15 +88,16 @@ module axi_fifo_2clk #(
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wire o_ext_tvalid;
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wire o_ext_tready;
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// Derive constants based on device.
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// The XPM based FIFO cannot be used for X300/X310 based devices due to the
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// timing constraints. Deriving a local parameter to use for later checks.
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// Derive constants based on device. The XPM-based FIFO is not yet supported
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// on some devices. Deriving a local parameter to use for later checks.
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`ifdef X300
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localparam DEVICE_X3XX = 1;
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localparam USE_LEGACY_FIFO = 1;
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`elsif X310
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localparam DEVICE_X3XX = 1;
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localparam USE_LEGACY_FIFO = 1;
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`elsif B310
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localparam USE_LEGACY_FIFO = 1;
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`else
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localparam DEVICE_X3XX = 0;
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localparam USE_LEGACY_FIFO = 0;
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`endif
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// First triple of values is for Intel's MAX10 FPGAs. The FIFO generator for
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@ -121,8 +122,8 @@ module axi_fifo_2clk #(
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assign rd_en = o_ext_tready & o_ext_tvalid;
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generate
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// XPM based FIFO for Xilinx FPGAs except for the X300/X310 based devices.
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if (DEVICE != "MAX10" && !DEVICE_X3XX) begin: xpm_fifo_section
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// XPM-based FIFO for Xilinx FPGAs, except for the certain devices.
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if (DEVICE != "MAX10" && !USE_LEGACY_FIFO) begin: xpm_fifo_section
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localparam XPM_SIZE = (SIZE < SRL_THRESHOLD) ? SRL_THRESHOLD : SIZE;
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fifo_xpm_2clk #(.WIDTH(WIDTH), .DEPTH(1 << XPM_SIZE)) impl_xpm_i (
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@ -4,9 +4,8 @@
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Container for the list of image package targets, and the information about them
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"""
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"""Container for the list of image package targets, and the information about them."""
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PACKAGE_MAPPING = {
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"e310_sg1": {
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"type": "e3xx",
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@ -348,6 +347,16 @@ PACKAGE_MAPPING = {
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"package_name": "usrp2_usrp2_fw_default-g{}.zip",
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"files": ["usrp2_fw.bin"],
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},
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"b310": {
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"type": "b3xx",
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"package_name": "b3xx_b310_fpga_default-g{}.zip",
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"files": [
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"usrp_b310_fpga_replay.bit",
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"usrp_b310_fpga_replay.rpt",
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"usrp_b310_fpga_fifo.bit",
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"usrp_b310_fpga_fifo.rpt",
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],
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},
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"b200": {
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"type": "b2xx",
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"package_name": "b2xx_b200_fpga_default-g{}.zip",
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@ -23,3 +23,4 @@ top/x400/rf/sim
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top/x300/dboards/obx/cpld/sim/obx_register_endpoints
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top/x300/dboards/obx/cpld/sim/obx_spi_passthrough
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lib/sim/fifo/axi_fifo
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lib/sim/control/ctrlport_spi_adrv_tb
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8
fpga/usrp3/top/b300/.gitignore
vendored
Normal file
8
fpga/usrp3/top/b300/.gitignore
vendored
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@ -0,0 +1,8 @@
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isim*
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fuse*
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tmp*
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*impact*
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objects
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modelsim
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# Ignore Python bytecode cache files
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__pycache__/
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139
fpga/usrp3/top/b300/Makefile
Normal file
139
fpga/usrp3/top/b300/Makefile
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@ -0,0 +1,139 @@
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#
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# Copyright 2025 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP B310 FPGA Help
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##-------------------
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##Usage:
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## rfnoc_image_builder -y <image core file> [-t <target>]
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##
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## NOTE: For building B310 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bin: Configuration bitstream without header
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Base output directory for all builds.
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BUILD_BASE_DIR ?= .
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# Base directory for the build outputs.
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BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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BASE_DEFS= $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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# Set build option (check RTL, run synthesis, or do a full build)
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ifndef TARGET
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ifeq ($(CHECK), 1)
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TARGET = rtl
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else ifeq ($(SYNTH), 1)
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TARGET = synth
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else ifeq ($(IP_ONLY), 1)
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TARGET = viv_ip
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else
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TARGET = bin
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endif
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endif
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TOP ?= b310
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.b310.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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vivado_ip = make -f Makefile.b310.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream files..."; \
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cp $(BUILD_DIR)/b310.bin $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bin; \
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cp $(BUILD_DIR)/b310.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Supported Targets
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##-----------------
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##
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml> [-t <target>]
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##
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##The default <image core file.yml> is one of:
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##
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##- b310_rfnoc_image_core.yml
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##
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##Of course, a custom YAML file may be used.
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##
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##For all other targets, choose a suitable target image core YAML file depending
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##on the device type (b310_*.yml) and provide the '--target' option
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##to override the default from the YAML file.
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##
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##Example:
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## $ rfnoc_image_builder -y b310_rfnoc_image_core.yml -t B310
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##will build the B310 target.
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##
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##B310:
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B310: check-variables B310_IP
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$(call vivado_build,B310,$(BASE_DEFS) B310=1)
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$(call post_build,B310)
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##
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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##B310_IP: Build IP for B310 only. Use the -j option to build multiple IP blocks simultaneously.
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B310_IP:
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+$(call vivado_ip,B310,$(BASE_DEFS) B310=1)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-B3*_* $(BUILD_BASE_DIR)/build-b3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-B3*_* $(BUILD_BASE_DIR)/build-b3* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##GUI=1 Launch the build in the Vivado GUI.
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##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##IP_ONLY=1 Launch the build but stop after IP generation.
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##SYNTH=1 Launch the build but stop after synthesis.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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117
fpga/usrp3/top/b300/Makefile.b310.inc
Normal file
117
fpga/usrp3/top/b300/Makefile.b310.inc
Normal file
@ -0,0 +1,117 @@
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#
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# Copyright 2025 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include ../x300/coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/wishbone/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/io_port2/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/io_cap_gen/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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b310.sv \
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netlists/b310_jesd204b.vhd \
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netlists/b310_jesd204b.edf \
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netlists/cpld_interface_wrapper.vhd \
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netlists/cpld_interface_wrapper.edf \
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netlists/b310_g2x4_host_interface.vhd \
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netlists/b310_g2x4_host_interface.edf \
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b310_pcie_int.sv \
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core/core_regs.sv \
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core/basic_regs.sv \
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core/radio_control_regs.sv \
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core/b310_core.sv \
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b3xx_pps_sync.sv \
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b310_xadc_wrapper.sv \
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constraints/b310.xdc \
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constraints/timing.xdc \
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constraints/b310_dram.xdc \
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../x400/cpld/x410/ctrlport_to_jtag.v \
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../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd \
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DESIGN_SRCS = $(abspath $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(EXTRAM_SRCS) \
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$(WISHBONE_SRCS) \
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$(IOPORT2_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) $(PACKET_PROC_SRCS) $(DSP_SRCS) \
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$(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(LIB_IP_XCI_SRCS) $(PCI_K7_SRCS) \
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$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS) \
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$(TOP_SRCS) \
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)
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_b310.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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viv_ip: .prereqs $$(DESIGN_SRCS) ip
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@echo "IP build for $(NAME) DONE . . ."
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.PHONY: bin synth rtl viv_ip
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1239
fpga/usrp3/top/b300/b310.sv
Normal file
1239
fpga/usrp3/top/b300/b310.sv
Normal file
File diff suppressed because it is too large
Load Diff
79
fpga/usrp3/top/b300/b310_fifo_rfnoc_image_core.yml
Normal file
79
fpga/usrp3/top/b300/b310_fifo_rfnoc_image_core.yml
Normal file
@ -0,0 +1,79 @@
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#
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# Copyright 2026 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2026 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 128 # Bit width of the CHDR bus for this image
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device: 'b310'
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image_core_name: 'usrp_b310_fpga_fifo' # This is used for the bitfile, DTS, and report
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default_target: 'B310'
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inherit:
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- 'yaml_include/b310_radio_base.yml'
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parameters:
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NUM_PORTS_PER_RADIO: 2
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ENABLE_DRAM: True
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PCIE_LINK_WIDTH: 4
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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fifo0:
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block_desc: 'axi_ram_fifo.yml'
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parameters:
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# These parameters match the memory interface on the B310
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NUM_PORTS: 2
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MEM_DATA_W: 64
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MEM_ADDR_W: 30
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MEM_CLK_RATE: "200e6"
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# Increase the output buffer size
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OUT_FIFO_SIZE: 14
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# Create two non-overlapping 512 MiB buffers by default
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FIFO_ADDR_BASE: "{30'h20000000, 30'h00000000}"
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FIFO_ADDR_MASK: "{30'h1FFFFFFF, 30'h1FFFFFFF}"
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A TX with DRAM FIFO
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- { srcblk: ep0, srcport: out0, dstblk: fifo0, dstport: in_0 }
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- { srcblk: fifo0, srcport: out_0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A RX
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
|
||||
#
|
||||
# RF B TX with DRAM FIFO
|
||||
- { srcblk: ep1, srcport: out0, dstblk: fifo0, dstport: in_1 }
|
||||
- { srcblk: fifo0, srcport: out_1, dstblk: duc0, dstport: in_1 }
|
||||
- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
|
||||
# RF B RX
|
||||
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
|
||||
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem }
|
||||
528
fpga/usrp3/top/b300/b310_pcie_int.sv
Normal file
528
fpga/usrp3/top/b300/b310_pcie_int.sv
Normal file
@ -0,0 +1,528 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: b310
|
||||
//
|
||||
// Description:
|
||||
// This module implements the PCIe interface for the B310. It is responsible
|
||||
// for merging the DMA channels connected to the Host IP into a two streams
|
||||
// (1 for TX and 1 for RX) that are connected to the crossbar.
|
||||
//
|
||||
// Parameters:
|
||||
// - DMA_STREAM_WIDTH: Width of the data bus. Currently 128 bits expected.
|
||||
// - NUM_TX_STREAMS: Number of TX FIFOs.
|
||||
// - NUM_RX_STREAMS: Number of RX FIFOs. Note: Despite having two different
|
||||
// parameters, NUM_TX_STREAMS and NUM_RX_STREAMS need to be
|
||||
// identical.
|
||||
|
||||
module b310_pcie_int #(
|
||||
int DMA_STREAM_WIDTH = 128,
|
||||
int NUM_TX_STREAMS = 5,
|
||||
int NUM_RX_STREAMS = 5,
|
||||
int BUS_CLK_RATE = 166_666_666
|
||||
) (
|
||||
//---------------------------------------------------------
|
||||
// Clocks and Resets
|
||||
//---------------------------------------------------------
|
||||
input wire reg_clk,
|
||||
input wire dma_clk,
|
||||
input wire bus_clk,
|
||||
input wire bus_rst,
|
||||
|
||||
//---------------------------------------------------------
|
||||
// DMA streams to/from InchWorm (Domain: dma_clk)
|
||||
//---------------------------------------------------------
|
||||
input wire [NUM_TX_STREAMS-1:0] [DMA_STREAM_WIDTH-1:0] host_dma_tx_tdata,
|
||||
input wire [NUM_TX_STREAMS-1:0] host_dma_tx_tvalid,
|
||||
output wire [NUM_TX_STREAMS-1:0] host_dma_tx_tready,
|
||||
|
||||
output wire [NUM_RX_STREAMS-1:0] [DMA_STREAM_WIDTH-1:0] host_dma_rx_tdata,
|
||||
output wire [NUM_RX_STREAMS-1:0] host_dma_rx_tvalid,
|
||||
input wire [NUM_RX_STREAMS-1:0] host_dma_rx_tready,
|
||||
|
||||
//---------------------------------------------------------
|
||||
// DMA stream to/from crossbar (Domain: bus_clk)
|
||||
//---------------------------------------------------------
|
||||
output wire [DMA_STREAM_WIDTH-1:0] dma_tx_tdata,
|
||||
output wire [2:0] dma_tx_tuser,
|
||||
output wire dma_tx_tvalid,
|
||||
output wire dma_tx_tlast,
|
||||
input wire dma_tx_tready,
|
||||
|
||||
input wire [DMA_STREAM_WIDTH-1:0] dma_rx_tdata,
|
||||
input wire [2:0] dma_rx_tuser,
|
||||
input wire dma_rx_tvalid,
|
||||
input wire dma_rx_tlast,
|
||||
output wire dma_rx_tready,
|
||||
|
||||
//---------------------------------------------------------
|
||||
// CtrlPort register interface (Domain: reg_clk)
|
||||
//---------------------------------------------------------
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
output wire s_ctrlport_resp_ack,
|
||||
output wire [1:0] s_ctrlport_resp_status,
|
||||
output wire [31:0] s_ctrlport_resp_data,
|
||||
|
||||
//---------------------------------------------------------
|
||||
// Misc
|
||||
//---------------------------------------------------------
|
||||
input wire [15:0] misc_status,
|
||||
output wire [127:0] debug
|
||||
);
|
||||
|
||||
localparam DMA_CLK_XING_FIFO_SIZE = 5; //Will synthesize fifo_short_2clk
|
||||
localparam DMA_PKT_GATE_FIFO_SIZE = 11; //Room for 2 8k packets
|
||||
localparam DMA_FRAME_SIZE_WIDTH = 16;
|
||||
localparam DMA_RX_DEST_WIDTH = $clog2(NUM_RX_STREAMS);
|
||||
|
||||
|
||||
wire [NUM_TX_STREAMS-1:0] dma_tx_clear, dma_tx_enabled;
|
||||
wire [NUM_TX_STREAMS-1:0] dma_tx_samp_stb, dma_tx_pkt_stb;
|
||||
wire [NUM_TX_STREAMS-1:0] dma_tx_busy, dma_tx_error;
|
||||
wire [NUM_TX_STREAMS-1:0] [DMA_FRAME_SIZE_WIDTH-1:0] dma_tx_frame_size;
|
||||
|
||||
wire [NUM_RX_STREAMS-1:0] dma_rx_clear, dma_rx_enabled;
|
||||
wire [NUM_RX_STREAMS-1:0] dma_rx_samp_stb, dma_rx_pkt_stb;
|
||||
wire [NUM_RX_STREAMS-1:0] dma_rx_busy, dma_rx_error;
|
||||
wire [NUM_RX_STREAMS-1:0] [DMA_FRAME_SIZE_WIDTH-1:0] dma_rx_frame_size;
|
||||
wire [DMA_STREAM_WIDTH-1:0] dma_rx_header;
|
||||
|
||||
//*******************************************************************************
|
||||
// CtrlPort interface conversion + crossing + decode
|
||||
//
|
||||
// Address map (0x200-address windows):
|
||||
// Slave 0 (basic_regs): 0x00000 - 0x001FF
|
||||
// Slave 1 (tx_dma_ctrl): 0x00200 - 0x003FF
|
||||
// Slave 2 (rx_dma_ctrl): 0x00400 - 0x005FF
|
||||
//
|
||||
typedef enum int {
|
||||
BASIC_REGS,
|
||||
TX_DMA,
|
||||
RX_DMA
|
||||
} ctrlport_ep_t;
|
||||
localparam int NUM_EP = 3;
|
||||
|
||||
localparam int EP_PORT_BASE [NUM_EP] = '{
|
||||
'h00000, // BASIC_REGS
|
||||
'h00200, // TX_DMA
|
||||
'h00400 // RX_DMA
|
||||
};
|
||||
localparam int EP_PORT_SIZE [NUM_EP] = '{
|
||||
'h00200, // BASIC_REGS
|
||||
'h00200, // TX_DMA
|
||||
'h00200 // RX_DMA
|
||||
};
|
||||
|
||||
ctrlport_if reg_ctrlport_if (.clk(reg_clk), .rst(bus_rst));
|
||||
ctrlport_if bclk_ctrlport_if (.clk(bus_clk), .rst(bus_rst));
|
||||
ctrlport_if ep_ctrlport_if [NUM_EP] (
|
||||
.clk(bus_clk),
|
||||
.rst(bus_rst)
|
||||
);
|
||||
|
||||
assign reg_ctrlport_if.req.wr = s_ctrlport_req_wr;
|
||||
assign reg_ctrlport_if.req.rd = s_ctrlport_req_rd;
|
||||
assign reg_ctrlport_if.req.addr = s_ctrlport_req_addr;
|
||||
assign reg_ctrlport_if.req.port_id = '0;
|
||||
assign reg_ctrlport_if.req.remote_epid = '0;
|
||||
assign reg_ctrlport_if.req.remote_portid = '0;
|
||||
assign reg_ctrlport_if.req.data = s_ctrlport_req_data;
|
||||
assign reg_ctrlport_if.req.byte_en = '1;
|
||||
assign reg_ctrlport_if.req.has_time = 1'b0;
|
||||
assign reg_ctrlport_if.req.timestamp = '0;
|
||||
|
||||
assign s_ctrlport_resp_ack = reg_ctrlport_if.resp.ack;
|
||||
assign s_ctrlport_resp_status = reg_ctrlport_if.resp.status;
|
||||
assign s_ctrlport_resp_data = reg_ctrlport_if.resp.data;
|
||||
|
||||
|
||||
//CtrlPort clock crossing: reg_clk -> bus_clk
|
||||
ctrlport_if_clk_cross reg_to_bus_clk_cross (
|
||||
.s_ctrlport(reg_ctrlport_if),
|
||||
.m_ctrlport(bclk_ctrlport_if)
|
||||
);
|
||||
|
||||
ctrlport_if_decoder #(
|
||||
.NUM_SLAVES(NUM_EP),
|
||||
.PORT_BASE (EP_PORT_BASE),
|
||||
.PORT_SIZE (EP_PORT_SIZE)
|
||||
) ctrlport_decoder (
|
||||
.s_ctrlport(bclk_ctrlport_if),
|
||||
.m_ctrlport(ep_ctrlport_if)
|
||||
);
|
||||
|
||||
wire [63:0] basic_regi_tdata, dma_tx_regi_tdata, dma_rx_regi_tdata;
|
||||
wire basic_regi_tvalid, dma_tx_regi_tvalid, dma_rx_regi_tvalid;
|
||||
wire basic_regi_tready, dma_tx_regi_tready, dma_rx_regi_tready;
|
||||
wire [63:0] basic_rego_tdata, dma_tx_rego_tdata, dma_rx_rego_tdata;
|
||||
wire basic_rego_tvalid, dma_tx_rego_tvalid, dma_rx_rego_tvalid;
|
||||
wire basic_rego_tready, dma_tx_rego_tready, dma_rx_rego_tready;
|
||||
|
||||
// Slave 0: pcie_basic_regs
|
||||
ctrlport_to_ioport2_stream basic_regs_bridge (
|
||||
.s_ctrlport (ep_ctrlport_if[BASIC_REGS]),
|
||||
.regi_tdata (basic_regi_tdata),
|
||||
.regi_tvalid (basic_regi_tvalid),
|
||||
.regi_tready (basic_regi_tready),
|
||||
.rego_tdata (basic_rego_tdata),
|
||||
.rego_tvalid (basic_rego_tvalid),
|
||||
.rego_tready (basic_rego_tready)
|
||||
);
|
||||
|
||||
// Slave 1: tx_dma_ctrl
|
||||
ctrlport_to_ioport2_stream tx_dma_bridge (
|
||||
.s_ctrlport (ep_ctrlport_if[TX_DMA]),
|
||||
.regi_tdata (dma_tx_regi_tdata),
|
||||
.regi_tvalid (dma_tx_regi_tvalid),
|
||||
.regi_tready (dma_tx_regi_tready),
|
||||
.rego_tdata (dma_tx_rego_tdata),
|
||||
.rego_tvalid (dma_tx_rego_tvalid),
|
||||
.rego_tready (dma_tx_rego_tready)
|
||||
);
|
||||
|
||||
// Slave 2: rx_dma_ctrl
|
||||
ctrlport_to_ioport2_stream rx_dma_bridge (
|
||||
.s_ctrlport (ep_ctrlport_if[RX_DMA]),
|
||||
.regi_tdata (dma_rx_regi_tdata),
|
||||
.regi_tvalid (dma_rx_regi_tvalid),
|
||||
.regi_tready (dma_rx_regi_tready),
|
||||
.rego_tdata (dma_rx_rego_tdata),
|
||||
.rego_tvalid (dma_rx_rego_tvalid),
|
||||
.rego_tready (dma_rx_rego_tready)
|
||||
);
|
||||
|
||||
wire [15:0] fpga_status;
|
||||
assign fpga_status[7:0] = {|(dma_tx_error), 1'b0, dma_tx_enabled};
|
||||
assign fpga_status[15:8] = {|(dma_rx_error), 1'b0, dma_rx_enabled};
|
||||
|
||||
pcie_basic_regs #(
|
||||
.SIGNATURE (32'h42333130 /*ASCII:"B310"*/),
|
||||
.CLK_FREQ (BUS_CLK_RATE)
|
||||
) basic_regs (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.regi_tdata (basic_regi_tdata),
|
||||
.regi_tvalid (basic_regi_tvalid),
|
||||
.regi_tready (basic_regi_tready),
|
||||
.rego_tdata (basic_rego_tdata),
|
||||
.rego_tvalid (basic_rego_tvalid),
|
||||
.rego_tready (basic_rego_tready),
|
||||
.misc_status ({fpga_status, misc_status})
|
||||
);
|
||||
|
||||
pcie_dma_ctrl #(
|
||||
.NUM_STREAMS (NUM_TX_STREAMS),
|
||||
.FRAME_SIZE_W (DMA_FRAME_SIZE_WIDTH),
|
||||
.REG_BASE_ADDR (20'h00000), // offset 0x200 extracted by the ctrlport_if_decoder
|
||||
.ENABLE_ROUTER (0)
|
||||
) tx_dma_ctrl_regs (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.regi_tdata (dma_tx_regi_tdata),
|
||||
.regi_tvalid (dma_tx_regi_tvalid),
|
||||
.regi_tready (dma_tx_regi_tready),
|
||||
.rego_tdata (dma_tx_rego_tdata),
|
||||
.rego_tvalid (dma_tx_rego_tvalid),
|
||||
.rego_tready (dma_tx_rego_tready),
|
||||
.set_enabled (dma_tx_enabled),
|
||||
.set_clear (dma_tx_clear),
|
||||
.set_frame_size (dma_tx_frame_size),
|
||||
.sample_stb (dma_tx_samp_stb),
|
||||
.packet_stb (dma_tx_pkt_stb),
|
||||
.stream_busy (dma_tx_busy),
|
||||
.stream_err (dma_tx_error),
|
||||
.rtr_sid (8'h00),
|
||||
.rtr_dst ()
|
||||
);
|
||||
|
||||
pcie_dma_ctrl #(
|
||||
.NUM_STREAMS (NUM_RX_STREAMS),
|
||||
.FRAME_SIZE_W (DMA_FRAME_SIZE_WIDTH),
|
||||
.REG_BASE_ADDR (20'h00000), // offset 0x400 extracted by the ctrlport_if_decoder
|
||||
.ENABLE_ROUTER (0)
|
||||
) rx_dma_ctrl_regs (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.regi_tdata (dma_rx_regi_tdata),
|
||||
.regi_tvalid (dma_rx_regi_tvalid),
|
||||
.regi_tready (dma_rx_regi_tready),
|
||||
.rego_tdata (dma_rx_rego_tdata),
|
||||
.rego_tvalid (dma_rx_rego_tvalid),
|
||||
.rego_tready (dma_rx_rego_tready),
|
||||
.set_enabled (dma_rx_enabled),
|
||||
.set_clear (dma_rx_clear),
|
||||
.set_frame_size (dma_rx_frame_size),
|
||||
.sample_stb (dma_rx_samp_stb),
|
||||
.packet_stb (dma_rx_pkt_stb),
|
||||
.stream_busy (dma_rx_busy),
|
||||
.stream_err (dma_rx_error),
|
||||
.rtr_sid (8'h00),
|
||||
.rtr_dst ()
|
||||
);
|
||||
//
|
||||
//*******************************************************************************
|
||||
|
||||
//*******************************************************************************
|
||||
// TX DMA Datapath
|
||||
//
|
||||
wire [NUM_TX_STREAMS-1:0][DMA_STREAM_WIDTH-1:0] dma_tx_tdata_bclk, dma_tx_tdata_in,
|
||||
dma_tx_tdata_trun, dma_tx_tdata_gt;
|
||||
wire [NUM_TX_STREAMS-1:0] dma_tx_tvalid_bclk, dma_tx_tvalid_in,
|
||||
dma_tx_tvalid_trun, dma_tx_tvalid_gt;
|
||||
wire [NUM_TX_STREAMS-1:0] dma_tx_tready_bclk, dma_tx_tready_in,
|
||||
dma_tx_tready_trun, dma_tx_tready_gt;
|
||||
wire [NUM_TX_STREAMS-1:0] dma_tx_tlast_trun, dma_tx_tlast_gt;
|
||||
// Output of the axi_mux8
|
||||
wire [DMA_STREAM_WIDTH-1:0] dma_tx_tdata_mux;
|
||||
wire [DMA_RX_DEST_WIDTH-1:0] dma_tx_tuser_mux;
|
||||
wire dma_tx_tvalid_mux, dma_tx_tlast_mux,
|
||||
dma_tx_tready_mux;
|
||||
|
||||
genvar tx_i;
|
||||
generate
|
||||
for (tx_i=0; tx_i<NUM_TX_STREAMS; tx_i=tx_i+1) begin: gen_tx_dma_path
|
||||
axi_fifo_2clk #(
|
||||
.WIDTH (DMA_STREAM_WIDTH),
|
||||
.SIZE (DMA_CLK_XING_FIFO_SIZE)
|
||||
) tx_dma_clock_crossing_fifo (
|
||||
.reset (bus_rst),
|
||||
.i_aclk (dma_clk),
|
||||
.i_tdata (host_dma_tx_tdata[tx_i]),
|
||||
.i_tvalid (host_dma_tx_tvalid[tx_i]),
|
||||
.i_tready (host_dma_tx_tready[tx_i]),
|
||||
.o_aclk (bus_clk),
|
||||
.o_tdata (dma_tx_tdata_bclk[tx_i]),
|
||||
.o_tvalid (dma_tx_tvalid_bclk[tx_i]),
|
||||
.o_tready (dma_tx_tready_bclk[tx_i])
|
||||
);
|
||||
|
||||
pcie_lossy_samp_gate #(
|
||||
.DATA_WIDTH(DMA_STREAM_WIDTH)
|
||||
) tx_samp_gate (
|
||||
.i_tdata (dma_tx_tdata_bclk[tx_i]),
|
||||
.i_tvalid (dma_tx_tvalid_bclk[tx_i]),
|
||||
.i_tready (dma_tx_tready_bclk[tx_i]),
|
||||
.o_tdata (dma_tx_tdata_in[tx_i]),
|
||||
.o_tvalid (dma_tx_tvalid_in[tx_i]),
|
||||
.o_tready (dma_tx_tready_in[tx_i]),
|
||||
.drop (~dma_tx_enabled[tx_i]),
|
||||
.dropping (dma_tx_busy[tx_i])
|
||||
);
|
||||
|
||||
chdr_dechunker #(
|
||||
.DATA_WIDTH (DMA_STREAM_WIDTH),
|
||||
.PAD_VALUE ({DMA_STREAM_WIDTH{1'b1}})
|
||||
) tx_dma_dechunker (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.clear (dma_tx_clear[tx_i]),
|
||||
.frame_size (dma_tx_frame_size[tx_i]),
|
||||
.i_tdata (dma_tx_tdata_in[tx_i]),
|
||||
.i_tvalid (dma_tx_tvalid_in[tx_i]),
|
||||
.i_tready (dma_tx_tready_in[tx_i]),
|
||||
.o_tdata (dma_tx_tdata_trun[tx_i]),
|
||||
.o_tlast (dma_tx_tlast_trun[tx_i]),
|
||||
.o_tvalid (dma_tx_tvalid_trun[tx_i]),
|
||||
.o_tready (dma_tx_tready_trun[tx_i]),
|
||||
.error (dma_tx_error[tx_i])
|
||||
);
|
||||
|
||||
assign dma_tx_samp_stb[tx_i] = dma_tx_tvalid_trun[tx_i] & dma_tx_tready_trun[tx_i];
|
||||
assign dma_tx_pkt_stb[tx_i] = dma_tx_samp_stb[tx_i] & dma_tx_tlast_trun[tx_i];
|
||||
|
||||
axi_packet_gate #(
|
||||
.WIDTH (DMA_STREAM_WIDTH),
|
||||
.SIZE (DMA_PKT_GATE_FIFO_SIZE)
|
||||
) vita_chdr_gate (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.clear (dma_tx_clear[tx_i]),
|
||||
.i_tdata (dma_tx_tdata_trun[tx_i]),
|
||||
.i_tlast (dma_tx_tlast_trun[tx_i]),
|
||||
.i_tvalid (dma_tx_tvalid_trun[tx_i]),
|
||||
.i_tready (dma_tx_tready_trun[tx_i]),
|
||||
.i_terror (dma_tx_error[tx_i]),
|
||||
.o_tdata (dma_tx_tdata_gt[tx_i]),
|
||||
.o_tlast (dma_tx_tlast_gt[tx_i]),
|
||||
.o_tvalid (dma_tx_tvalid_gt[tx_i]),
|
||||
.o_tready (dma_tx_tready_gt[tx_i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// [DrB] The following transport adapter requires a tuser input with the DMA
|
||||
// channel. Neither axi_mux8 nor axi_fifo_flop2 support tuser at the time of
|
||||
// this modification, and to reduce the risk we will simply widen tdata and
|
||||
// include the tuser value in there.
|
||||
axi_mux8 #(
|
||||
.PRIO (0),
|
||||
.WIDTH (DMA_STREAM_WIDTH+DMA_RX_DEST_WIDTH)
|
||||
) output_dma_mux (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst), .clear (|(dma_tx_clear)),
|
||||
.i0_tdata ({DMA_RX_DEST_WIDTH'(0), dma_tx_tdata_gt[0]}), .i0_tlast ( dma_tx_tlast_gt[0]),
|
||||
.i0_tvalid( dma_tx_tvalid_gt[0]), .i0_tready (dma_tx_tready_gt[0]),
|
||||
.i1_tdata ({DMA_RX_DEST_WIDTH'(1), dma_tx_tdata_gt[1]}), .i1_tlast ( dma_tx_tlast_gt[1]),
|
||||
.i1_tvalid( dma_tx_tvalid_gt[1]), .i1_tready (dma_tx_tready_gt[1]),
|
||||
.i2_tdata ({DMA_RX_DEST_WIDTH'(2), dma_tx_tdata_gt[2]}), .i2_tlast ( dma_tx_tlast_gt[2]),
|
||||
.i2_tvalid( dma_tx_tvalid_gt[2]), .i2_tready (dma_tx_tready_gt[2]),
|
||||
.i3_tdata ({DMA_RX_DEST_WIDTH'(3), dma_tx_tdata_gt[3]}), .i3_tlast ( dma_tx_tlast_gt[3]),
|
||||
.i3_tvalid( dma_tx_tvalid_gt[3]), .i3_tready (dma_tx_tready_gt[3]),
|
||||
.i4_tdata ({DMA_RX_DEST_WIDTH'(4), dma_tx_tdata_gt[4]}), .i4_tlast ( dma_tx_tlast_gt[4]),
|
||||
.i4_tvalid( dma_tx_tvalid_gt[4]), .i4_tready (dma_tx_tready_gt[4]),
|
||||
// Unused inputs tied off
|
||||
.i5_tdata ({DMA_RX_DEST_WIDTH'(5), {DMA_STREAM_WIDTH{1'b0}}}),.i5_tlast(1'b0),
|
||||
.i5_tvalid(1'b0), .i5_tready(),
|
||||
.i6_tdata ({DMA_RX_DEST_WIDTH'(6), {DMA_STREAM_WIDTH{1'b0}}}),.i6_tlast(1'b0),
|
||||
.i6_tvalid(1'b0), .i6_tready(),
|
||||
.i7_tdata ({DMA_RX_DEST_WIDTH'(7), {DMA_STREAM_WIDTH{1'b0}}}),.i7_tlast(1'b0),
|
||||
.i7_tvalid(1'b0), .i7_tready(),
|
||||
.o_tdata ({dma_tx_tuser_mux, dma_tx_tdata_mux}),
|
||||
.o_tlast (dma_tx_tlast_mux),
|
||||
.o_tvalid (dma_tx_tvalid_mux),
|
||||
.o_tready (dma_tx_tready_mux)
|
||||
);
|
||||
|
||||
axi_fifo_flop2 #(
|
||||
.WIDTH(DMA_STREAM_WIDTH+1+DMA_RX_DEST_WIDTH)
|
||||
) tx_pipeline_reg (
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(|(dma_tx_clear)),
|
||||
.i_tdata ({dma_tx_tuser_mux, dma_tx_tlast_mux, dma_tx_tdata_mux}),
|
||||
.i_tvalid (dma_tx_tvalid_mux),
|
||||
.i_tready (dma_tx_tready_mux),
|
||||
.o_tdata ({dma_tx_tuser, dma_tx_tlast, dma_tx_tdata}),
|
||||
.o_tvalid (dma_tx_tvalid),
|
||||
.o_tready (dma_tx_tready),
|
||||
.space (),
|
||||
.occupied ()
|
||||
);
|
||||
//
|
||||
//*******************************************************************************
|
||||
|
||||
//*******************************************************************************
|
||||
// RX DMA Datapath
|
||||
//
|
||||
wire [NUM_RX_STREAMS-1:0][DMA_STREAM_WIDTH-1:0] dma_rx_tdata_bclk, dma_rx_tdata_pad,
|
||||
dma_rx_tdata_out;
|
||||
wire [NUM_RX_STREAMS-1:0] dma_rx_tvalid_bclk, dma_rx_tvalid_pad,
|
||||
dma_rx_tvalid_out;
|
||||
wire [NUM_RX_STREAMS-1:0] dma_rx_tready_bclk, dma_rx_tready_pad,
|
||||
dma_rx_tready_out;
|
||||
wire [NUM_RX_STREAMS-1:0] dma_rx_tlast_bclk, dma_rx_tlast_pad,
|
||||
dma_rx_tlast_out;
|
||||
|
||||
wire [DMA_STREAM_WIDTH-1:0] dma_rx_tdata_mux;
|
||||
wire [DMA_RX_DEST_WIDTH-1:0] dma_rx_tuser_mux;
|
||||
wire dma_rx_tvalid_mux, dma_rx_tlast_mux,
|
||||
dma_rx_tready_mux;
|
||||
|
||||
axi_fifo_flop2 #(
|
||||
.WIDTH(DMA_STREAM_WIDTH+1+DMA_RX_DEST_WIDTH)
|
||||
) rx_pipeline_reg (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.clear (|(dma_rx_clear)),
|
||||
.i_tdata ({dma_rx_tuser, dma_rx_tlast, dma_rx_tdata}),
|
||||
.i_tvalid (dma_rx_tvalid),
|
||||
.i_tready (dma_rx_tready),
|
||||
.o_tdata ({dma_rx_tuser_mux, dma_rx_tlast_mux, dma_rx_tdata_mux}),
|
||||
.o_tvalid (dma_rx_tvalid_mux),
|
||||
.o_tready (dma_rx_tready_mux),
|
||||
.space (),
|
||||
.occupied ()
|
||||
);
|
||||
|
||||
|
||||
localparam [7:0] DMA_RX_ACTIVE_CHAN =
|
||||
(NUM_RX_STREAMS >= 8) ? 8'hFF : (8'hFF >> (8-NUM_RX_STREAMS));
|
||||
|
||||
axi_demux8 #(
|
||||
.ACTIVE_CHAN(DMA_RX_ACTIVE_CHAN),
|
||||
.WIDTH(DMA_STREAM_WIDTH)
|
||||
) input_dma_demux (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.clear (|(dma_rx_clear)),
|
||||
.header (),
|
||||
.dest (dma_rx_tuser_mux),
|
||||
.i_tdata (dma_rx_tdata_mux), .i_tlast (dma_rx_tlast_mux),
|
||||
.i_tvalid (dma_rx_tvalid_mux), .i_tready (dma_rx_tready_mux),
|
||||
.o0_tdata (dma_rx_tdata_bclk[0]), .o0_tlast (dma_rx_tlast_bclk[0]),
|
||||
.o0_tvalid (dma_rx_tvalid_bclk[0]), .o0_tready (dma_rx_tready_bclk[0]),
|
||||
.o1_tdata (dma_rx_tdata_bclk[1]), .o1_tlast (dma_rx_tlast_bclk[1]),
|
||||
.o1_tvalid (dma_rx_tvalid_bclk[1]), .o1_tready (dma_rx_tready_bclk[1]),
|
||||
.o2_tdata (dma_rx_tdata_bclk[2]), .o2_tlast (dma_rx_tlast_bclk[2]),
|
||||
.o2_tvalid (dma_rx_tvalid_bclk[2]), .o2_tready (dma_rx_tready_bclk[2]),
|
||||
.o3_tdata (dma_rx_tdata_bclk[3]), .o3_tlast (dma_rx_tlast_bclk[3]),
|
||||
.o3_tvalid (dma_rx_tvalid_bclk[3]), .o3_tready (dma_rx_tready_bclk[3]),
|
||||
.o4_tdata (dma_rx_tdata_bclk[4]), .o4_tlast (dma_rx_tlast_bclk[4]),
|
||||
.o4_tvalid (dma_rx_tvalid_bclk[4]), .o4_tready (dma_rx_tready_bclk[4]),
|
||||
// Unused outputs tied off
|
||||
.o5_tdata(), .o5_tlast(), .o5_tvalid(), .o5_tready(1'b0), //Unused port
|
||||
.o6_tdata(), .o6_tlast(), .o6_tvalid(), .o6_tready(1'b0), //Unused port
|
||||
.o7_tdata(), .o7_tlast(), .o7_tvalid(), .o7_tready(1'b0) //Unused port
|
||||
);
|
||||
|
||||
genvar rx_i;
|
||||
generate
|
||||
for (rx_i=0; rx_i<NUM_RX_STREAMS; rx_i=rx_i+1) begin: gen_rx_dma_path
|
||||
|
||||
assign dma_rx_samp_stb[rx_i] = dma_rx_tvalid_bclk[rx_i] & dma_rx_tready_bclk[rx_i];
|
||||
assign dma_rx_pkt_stb[rx_i] = dma_rx_samp_stb[rx_i] & dma_rx_tlast_bclk[rx_i];
|
||||
|
||||
chdr_chunker #(
|
||||
.DATA_WIDTH (DMA_STREAM_WIDTH),
|
||||
.PAD_VALUE ({DMA_STREAM_WIDTH{1'b1}})
|
||||
) rx_dma_chunker (
|
||||
.clk (bus_clk),
|
||||
.reset (bus_rst),
|
||||
.clear (dma_rx_clear[rx_i]),
|
||||
.frame_size (dma_rx_frame_size[rx_i]),
|
||||
.i_tdata (dma_rx_tdata_bclk[rx_i]),
|
||||
.i_tlast (dma_rx_tlast_bclk[rx_i]),
|
||||
.i_tvalid (dma_rx_tvalid_bclk[rx_i]),
|
||||
.i_tready (dma_rx_tready_bclk[rx_i]),
|
||||
.o_tdata (dma_rx_tdata_pad[rx_i]),
|
||||
.o_tlast (dma_rx_tlast_pad[rx_i]),
|
||||
.o_tvalid (dma_rx_tvalid_pad[rx_i]),
|
||||
.o_tready (dma_rx_tready_pad[rx_i]),
|
||||
.error (dma_rx_error[rx_i])
|
||||
);
|
||||
|
||||
pcie_lossy_samp_gate #(
|
||||
.DATA_WIDTH(DMA_STREAM_WIDTH)
|
||||
) rx_samp_gate (
|
||||
.i_tdata (dma_rx_tdata_pad[rx_i]),
|
||||
.i_tvalid (dma_rx_tvalid_pad[rx_i]),
|
||||
.i_tready (dma_rx_tready_pad[rx_i]),
|
||||
.o_tdata (dma_rx_tdata_out[rx_i]),
|
||||
.o_tvalid (dma_rx_tvalid_out[rx_i]),
|
||||
.o_tready (dma_rx_tready_out[rx_i]),
|
||||
.drop (~dma_rx_enabled[rx_i]),
|
||||
.dropping (dma_rx_busy[rx_i])
|
||||
);
|
||||
|
||||
axi_fifo_2clk #(
|
||||
.WIDTH (DMA_STREAM_WIDTH),
|
||||
.SIZE (DMA_CLK_XING_FIFO_SIZE)
|
||||
) rx_dma_clock_crossing_fifo (
|
||||
.reset (bus_rst),
|
||||
.i_aclk (bus_clk),
|
||||
.i_tdata (dma_rx_tdata_out[rx_i]),
|
||||
.i_tvalid (dma_rx_tvalid_out[rx_i]),
|
||||
.i_tready (dma_rx_tready_out[rx_i]),
|
||||
.o_aclk (dma_clk),
|
||||
.o_tdata (host_dma_rx_tdata[rx_i]),
|
||||
.o_tvalid (host_dma_rx_tvalid[rx_i]),
|
||||
.o_tready (host_dma_rx_tready[rx_i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
//
|
||||
//*******************************************************************************
|
||||
endmodule : b310_pcie_int
|
||||
93
fpga/usrp3/top/b300/b310_replay_rfnoc_image_core.yml
Normal file
93
fpga/usrp3/top/b300/b310_replay_rfnoc_image_core.yml
Normal file
@ -0,0 +1,93 @@
|
||||
#
|
||||
# Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
# General parameters
|
||||
# -----------------------------------------
|
||||
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
|
||||
copyright: >- # Copyright information used in file headers
|
||||
Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
license: >- # License information used in file headers
|
||||
SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
version: '1.0' # File version
|
||||
chdr_width: 128 # Bit width of the CHDR bus for this image
|
||||
device: 'b310'
|
||||
image_core_name: 'usrp_b310_fpga_replay' # This is used for the bitfile, DTS, and report
|
||||
default_target: 'B310'
|
||||
inherit:
|
||||
- 'yaml_include/b310_radio_base.yml'
|
||||
|
||||
parameters:
|
||||
NUM_PORTS_PER_RADIO: 2
|
||||
ENABLE_DRAM: True
|
||||
PCIE_LINK_WIDTH: 4
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
stream_endpoints:
|
||||
ep0: # Stream endpoint name
|
||||
buff_size_bytes: 262144 # Ingress buffer size for data
|
||||
ep1:
|
||||
buff_size_bytes: 262144
|
||||
ep2:
|
||||
buff_size_bytes: 65536
|
||||
ctrl: False
|
||||
data: True
|
||||
ep3:
|
||||
buff_size_bytes: 65536
|
||||
ctrl: False
|
||||
data: True
|
||||
|
||||
# A list of all NoC blocks in design
|
||||
# ----------------------------------
|
||||
noc_blocks:
|
||||
replay0:
|
||||
block_desc: 'replay.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
MEM_DATA_W: 64
|
||||
MEM_ADDR_W: 30
|
||||
priority: 99 # Make sure they come after the blocks defined in b310_radio_base.yml
|
||||
|
||||
# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect
|
||||
# - srcport = Port on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Port on the destination block to connect
|
||||
connections:
|
||||
# RF A TX
|
||||
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
|
||||
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
|
||||
# RF A RX
|
||||
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
|
||||
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
|
||||
#
|
||||
# RF B TX
|
||||
- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
|
||||
- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
|
||||
# RF B RX
|
||||
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
|
||||
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
|
||||
#
|
||||
# Replay Connections
|
||||
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
|
||||
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
|
||||
- { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 }
|
||||
- { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
171
fpga/usrp3/top/b300/b310_xadc_wrapper.sv
Normal file
171
fpga/usrp3/top/b300/b310_xadc_wrapper.sv
Normal file
@ -0,0 +1,171 @@
|
||||
//
|
||||
// Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: b310_xadc_wrapper
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This module wraps the XADC IP core to provide periodic temperature monitoring of
|
||||
// the FPGA die and configuration of the over-temperature shutdown threshold.
|
||||
//
|
||||
// This file heavily borrows the structure of the mig_7series_v4_2_tempmon example
|
||||
// design provided by Xilinx in their MIG 7 Series IP core.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// SHUTDOWN_TEMP_C: Over-temperature shutdown threshold (degrees C). When the FPGA
|
||||
// temperature exceeds this value, the FPGA will initiate a
|
||||
// shutdown sequence.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module b310_xadc_wrapper #(
|
||||
parameter int SHUTDOWN_TEMP_C = 125 // OT shutdown temperature (degrees C)
|
||||
) (
|
||||
input wire clk, // Fabric/XADC clock (same domain)
|
||||
input wire rst, // Synchronous reset
|
||||
output logic [11:0] device_temp
|
||||
);
|
||||
|
||||
localparam int XADC_WIDTH = 16;
|
||||
localparam int TEMP_WIDTH = 12;
|
||||
|
||||
// INIT_53: Over-Temperature alarm trigger
|
||||
// Xilinx transfer function: Temp(C) = (ADC_Code * 503.975 / 4096) - 273.15
|
||||
// => ADC_Code = (SHUTDOWN_TEMP_C + 273.15) * 4096 / 503.975
|
||||
// Register format: bits[15:4] = ADC_Code[11:0], bits[3:0] = 4'b0011 (per UG480)
|
||||
localparam logic [TEMP_WIDTH-1:0] OT_CODE = (SHUTDOWN_TEMP_C + 273.15) * 4096.0 / 503.975;
|
||||
localparam logic [XADC_WIDTH-1:0] INIT_53_VAL = {OT_CODE, 4'h3};
|
||||
|
||||
// FSM state encoding
|
||||
typedef enum logic [3:0] {
|
||||
IDLE,
|
||||
REQUEST_TEMP_READ,
|
||||
WAIT_FOR_READ_COMPLETE,
|
||||
LATCH_TEMP
|
||||
} tempmon_state_t;
|
||||
|
||||
tempmon_state_t tempmon_state;
|
||||
|
||||
// XADC interface
|
||||
logic xadc_den;
|
||||
logic xadc_drdy;
|
||||
logic [XADC_WIDTH-1:0] xadc_do;
|
||||
logic xadc_drdy_r;
|
||||
logic [XADC_WIDTH-1:0] xadc_do_r;
|
||||
|
||||
// Temperature storage
|
||||
logic [TEMP_WIDTH-1:0] temperature;
|
||||
|
||||
// FSM
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
temperature <= '0;
|
||||
xadc_den <= 1'b0;
|
||||
tempmon_state <= IDLE;
|
||||
end else begin
|
||||
|
||||
case (tempmon_state)
|
||||
|
||||
IDLE:
|
||||
tempmon_state <= REQUEST_TEMP_READ;
|
||||
|
||||
REQUEST_TEMP_READ: begin
|
||||
xadc_den <= 1'b1;
|
||||
tempmon_state <= WAIT_FOR_READ_COMPLETE;
|
||||
end
|
||||
|
||||
WAIT_FOR_READ_COMPLETE: begin
|
||||
// De-assert strobe signals.
|
||||
xadc_den <= 1'b0;
|
||||
// Wait for DRDY to go high, indicating data is ready
|
||||
if (xadc_drdy_r) begin
|
||||
tempmon_state <= LATCH_TEMP;
|
||||
end
|
||||
end
|
||||
|
||||
LATCH_TEMP: begin
|
||||
// Latch temperature and restart timer
|
||||
temperature <= xadc_do_r[4 +: TEMP_WIDTH];
|
||||
tempmon_state <= REQUEST_TEMP_READ;
|
||||
end
|
||||
|
||||
default:
|
||||
tempmon_state <= IDLE;
|
||||
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Register XADC outputs
|
||||
always_ff @(posedge clk)
|
||||
if (rst) begin
|
||||
xadc_drdy_r <= 1'b0;
|
||||
xadc_do_r <= '0;
|
||||
end else begin
|
||||
xadc_drdy_r <= xadc_drdy;
|
||||
xadc_do_r <= xadc_do;
|
||||
end
|
||||
|
||||
assign device_temp = temperature;
|
||||
|
||||
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter — 7 Series
|
||||
XADC #(
|
||||
// INIT_40 - INIT_42: XADC configuration registers
|
||||
.INIT_40(16'h1000), // config reg 0
|
||||
.INIT_41(16'h21fe), // config reg 1 - Enable OT alarm
|
||||
.INIT_42(16'h0800), // config reg 2
|
||||
// INIT_48 - INIT_4F: Sequence registers
|
||||
.INIT_48(16'h0101), // Sequencer channel selection
|
||||
.INIT_49(16'h0000), // Sequencer channel selection
|
||||
.INIT_4A(16'h0000), // Sequencer Average selection
|
||||
.INIT_4B(16'h0000), // Sequencer Average selection
|
||||
.INIT_4C(16'h0000), // Sequencer Bipolar selection
|
||||
.INIT_4D(16'h0000), // Sequencer Bipolar selection
|
||||
.INIT_4E(16'h0000), // Sequencer Acq time selection
|
||||
.INIT_4F(16'h0000), // Sequencer Acq time selection
|
||||
// INIT_50 - INIT_58, INIT_5C: Alarm limit registers
|
||||
.INIT_50(16'hb5ed), // Temp alarm trigger
|
||||
.INIT_51(16'h57e4), // Vccint upper alarm limit
|
||||
.INIT_52(16'ha147), // Vccaux upper alarm limit
|
||||
.INIT_53(INIT_53_VAL), // Temp alarm OT upper (derived from SHUTDOWN_TEMP_C)
|
||||
.INIT_54(16'ha93a), // Temp alarm reset
|
||||
.INIT_55(16'h52c6), // Vccint lower alarm limit
|
||||
.INIT_56(16'h9555), // Vccaux lower alarm limit
|
||||
.INIT_57(16'hb0de), // Temp alarm OT reset - reactivate FPGA at 75C
|
||||
.INIT_58(16'h5999), // VBRAM upper alarm limit
|
||||
.INIT_5C(16'h5111), // VBRAM lower alarm limit
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) XADC_inst (
|
||||
.ALM(),
|
||||
.OT(),
|
||||
.DO(xadc_do),
|
||||
.DRDY(xadc_drdy),
|
||||
.BUSY(),
|
||||
.CHANNEL(),
|
||||
.EOC(),
|
||||
.EOS(),
|
||||
.JTAGBUSY(),
|
||||
.JTAGLOCKED(),
|
||||
.JTAGMODIFIED(),
|
||||
.MUXADDR(),
|
||||
.VAUXN(16'b0),
|
||||
.VAUXP(16'b0),
|
||||
.CONVST(1'b0),
|
||||
.CONVSTCLK(1'b0),
|
||||
.RESET(rst),
|
||||
.VN(1'b0),
|
||||
.VP(1'b0),
|
||||
.DADDR(7'h00), // 0x00 = on-chip temperature sensor
|
||||
.DCLK(clk),
|
||||
.DEN(xadc_den),
|
||||
.DI({XADC_WIDTH{1'b0}}),
|
||||
.DWE(1'b0)
|
||||
);
|
||||
|
||||
endmodule: b310_xadc_wrapper
|
||||
|
||||
`default_nettype wire
|
||||
320
fpga/usrp3/top/b300/b3xx_pps_sync.sv
Normal file
320
fpga/usrp3/top/b300/b3xx_pps_sync.sv
Normal file
@ -0,0 +1,320 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: b3xx_pps_sync
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This module encapsulates the PPS handling and the related LMK SYNC signal.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
|
||||
module b3xx_pps_sync
|
||||
(
|
||||
// clock and reset
|
||||
input wire base_ref_clk, // BRC
|
||||
input wire radio_clk_shifted, // RC
|
||||
input wire radio_clk, // For LMK Sync output
|
||||
input wire ctrl_clk, // CC
|
||||
|
||||
input wire brc_rst,
|
||||
|
||||
// PPS
|
||||
input wire pps_in_brc,
|
||||
output logic pps_in_rclk,
|
||||
|
||||
// LMK control signal
|
||||
output logic lmk_sync_reva = 1'b0,
|
||||
output logic lmk_sync = 1'b0,
|
||||
input wire lmk_sync_clk_sel,
|
||||
input wire lmk_clkin0_sync_sel,
|
||||
|
||||
// Control signals (CC domain)
|
||||
// domain external to here? Or bring that logic in.
|
||||
input wire [26:0] lmk_sync_delay,
|
||||
input wire lmk_sync_trigger,
|
||||
output logic lmk_sync_done,
|
||||
input wire [9:0] pps_in_to_rclk_delay,
|
||||
output logic [3:0] debug
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// LMK sync generation (BRC domain)
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Detect rising edge of PPS
|
||||
// Ignore the first cycle after a new PPS source is selected as this might cause a change in the
|
||||
// PPS signal as the PPS sources are not aligned.
|
||||
// Skipping this switching cycle ensures the rising edge is detected from the selected PPS source.
|
||||
logic pps_brc_delayed, pps_rising_edge_brc;
|
||||
always_ff @(posedge base_ref_clk) begin
|
||||
pps_brc_delayed <= pps_in_brc;
|
||||
end
|
||||
assign pps_rising_edge_brc = pps_in_brc & ~pps_brc_delayed;
|
||||
|
||||
// There is no data coherency guaranteed by this synchronizer, but this is
|
||||
// not required. The information is derived in the same clock domain as the
|
||||
// sync trigger. Both information in the worst case arrive in the same clock
|
||||
// cycle. In the state machine the trigger is changing the state to ARMED.
|
||||
// The delay value is required in the ARMED state. This way there is one more
|
||||
// clock cycle for this synchronizer to propagate the correct value of all
|
||||
// bits.
|
||||
logic [26:0] lmk_sync_delay_brc;
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (1),
|
||||
.WIDTH (27)
|
||||
) synchronizer_sync_delay (
|
||||
.clk (base_ref_clk),
|
||||
.rst (1'b0),
|
||||
.in (lmk_sync_delay),
|
||||
.out (lmk_sync_delay_brc)
|
||||
);
|
||||
|
||||
logic lmk_sync_trigger_brc;
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (1),
|
||||
.WIDTH (1)
|
||||
) synchronizer_sync_trigger (
|
||||
.clk (base_ref_clk),
|
||||
.rst (1'b0),
|
||||
.in (lmk_sync_trigger),
|
||||
.out (lmk_sync_trigger_brc)
|
||||
);
|
||||
|
||||
// Synchronization state machine
|
||||
typedef enum logic [1:0] { IDLE, ARMED, COUNT, DONE } state_t;
|
||||
state_t state;
|
||||
|
||||
logic [26:0] delay_counter_brc = 27'd0;
|
||||
logic lmk_sync_done_brc = 1'b0;
|
||||
logic sync_brc = 1'b0;
|
||||
|
||||
always_ff @(posedge base_ref_clk) begin
|
||||
if (brc_rst) begin
|
||||
sync_brc <= 1'b0;
|
||||
lmk_sync_done_brc <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
else begin
|
||||
case (state)
|
||||
IDLE: begin
|
||||
// Wait for trigger from control interface
|
||||
if (lmk_sync_trigger_brc) begin
|
||||
state <= ARMED;
|
||||
end
|
||||
end
|
||||
|
||||
ARMED: begin
|
||||
// Wait for the rising edge of PPS and reset counter
|
||||
delay_counter_brc <= lmk_sync_delay_brc;
|
||||
if (pps_rising_edge_brc) begin
|
||||
state <= COUNT;
|
||||
end
|
||||
end
|
||||
|
||||
// Delay assertion of sync signal by the given number of cycles
|
||||
COUNT: begin
|
||||
delay_counter_brc <= delay_counter_brc - 1;
|
||||
if (delay_counter_brc == 0) begin
|
||||
state <= DONE;
|
||||
sync_brc <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Issue done signal until the trigger is released
|
||||
DONE: begin
|
||||
sync_brc <= 1'b0;
|
||||
lmk_sync_done_brc <= 1'b1;
|
||||
if (lmk_sync_trigger_brc == 0) begin
|
||||
state <= IDLE;
|
||||
lmk_sync_done_brc <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// In case we run into an undefined state
|
||||
default: begin
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Transfer done signal back to ctrl_clk domain
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (1)
|
||||
) synchronizer_pll_sync_done (
|
||||
.clk (ctrl_clk),
|
||||
.rst (1'b0),
|
||||
.in (lmk_sync_done_brc),
|
||||
.out (lmk_sync_done)
|
||||
);
|
||||
|
||||
logic lmk_clkin0_sync_sel_rc;
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (1)
|
||||
) synchronizer_sync_pin_ctrl (
|
||||
.clk (radio_clk),
|
||||
.rst (1'b0),
|
||||
.in (lmk_clkin0_sync_sel),
|
||||
.out (lmk_clkin0_sync_sel_rc)
|
||||
);
|
||||
|
||||
logic lmk_clkin0_sync_sel_brc;
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (1)
|
||||
) synchronizer_sync_pin_ctrl2 (
|
||||
.clk (base_ref_clk),
|
||||
.rst (1'b0),
|
||||
.in (lmk_clkin0_sync_sel),
|
||||
.out (lmk_clkin0_sync_sel_brc)
|
||||
);
|
||||
|
||||
logic sync_rc, sync_rc_out, sync_rc_out_reva;
|
||||
always_ff @(posedge radio_clk_shifted) begin
|
||||
// Go into radio_clk_shifted domain as it is shifted to right to account
|
||||
// for higher clock insertion delay of ext_ref_clk
|
||||
sync_rc <= sync_brc;
|
||||
end
|
||||
|
||||
always_ff @(posedge radio_clk) begin
|
||||
sync_rc_out_reva <= sync_rc && ~lmk_clkin0_sync_sel_rc ;
|
||||
sync_rc_out <= sync_rc && lmk_clkin0_sync_sel_rc ;
|
||||
end
|
||||
|
||||
logic sync_brc_out, sync_brc_out_reva;
|
||||
always_ff @(posedge base_ref_clk) begin
|
||||
sync_brc_out_reva <= sync_brc && ~lmk_clkin0_sync_sel_brc;
|
||||
sync_brc_out <= sync_brc && lmk_clkin0_sync_sel_brc;
|
||||
end
|
||||
|
||||
logic debug_3;
|
||||
always_comb begin : lmk_sync_select
|
||||
if (lmk_sync_clk_sel == 1'b0) begin
|
||||
lmk_sync_reva = sync_rc_out_reva;
|
||||
lmk_sync = sync_rc_out;
|
||||
debug_3 = sync_rc_out;
|
||||
end else begin
|
||||
lmk_sync_reva = sync_brc_out_reva;
|
||||
lmk_sync = sync_brc_out;
|
||||
debug_3 = sync_brc_out;
|
||||
end
|
||||
end
|
||||
|
||||
assign debug[3] = debug_3;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PPS clock domain crossings
|
||||
//---------------------------------------------------------------------------
|
||||
// In the section below the PPS crosses multiple clock domains.
|
||||
// From the generation in BRC clock domain we transfer the signal over to
|
||||
// RC using the aligned edge of the external LMK IC. x4xx also had
|
||||
// a radio clock, but for b3xx, our radio clock is the same frequency
|
||||
// as the RC (LMK dev_clock), thus our radio clock becomes the RC.
|
||||
|
||||
// BRC --\____/----\____/----\____/----\____/----\____/----\____/
|
||||
// RC ___/---\___/---\___/---\___/---\___/---\___/---\___/---\__
|
||||
// | aligned edge
|
||||
// PPS (BRC) __/--------------------------------------------------------
|
||||
// PPS (BRC delayed) ___________________/-------------------------------
|
||||
// Has to shift PPS to start on aligned edge.
|
||||
//
|
||||
// PPS (RC) __________________________________________/----------------
|
||||
// |------------->| 2 RC cycles
|
||||
// 2 stage synchronizer = 2 RC cycle delay on aligned edge
|
||||
//
|
||||
// PPS (RC delayed) __________/----------------------------------------
|
||||
// |------------------
|
||||
// ------------------------->| up to RC frequency cycles
|
||||
// Shifts PPS pulse by up to 1 second (PPS period) to be present in the
|
||||
// clock cycle before the aligned edge.
|
||||
//
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PPS delay (BRC domain)
|
||||
//---------------------------------------------------------------------------
|
||||
// This shift register delays the PPS trigger until the appearance of
|
||||
// the aligned edge of BRC and RC.
|
||||
// This delay has to incorporate the delay of the state machine above from
|
||||
// pps to sync output, the delay of the LMK chip from sync edge to aligned
|
||||
// edge and delay setting applied to the sync signal. Be sure to reduce the
|
||||
// number by 1 at the end to account for the final register.
|
||||
|
||||
logic [9:0] pps_in_to_rclk_delay_brc;
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (1),
|
||||
.WIDTH (10)
|
||||
) synchronizer_pps_brc_delay (
|
||||
.clk (base_ref_clk),
|
||||
.rst (1'b0),
|
||||
.in (pps_in_to_rclk_delay),
|
||||
.out (pps_in_to_rclk_delay_brc)
|
||||
);
|
||||
|
||||
logic [1023:0] pps_shift_reg_brc = 1024'b0;
|
||||
(* DONT_TOUCH = "TRUE" *) logic pps_delayed_brc = 1'b0;
|
||||
(* DONT_TOUCH = "TRUE" *) logic pps_delayed_brc_debug = 1'b0;
|
||||
always_ff @(posedge base_ref_clk) begin
|
||||
pps_shift_reg_brc <= {pps_shift_reg_brc[1022:0], pps_in_brc};
|
||||
pps_delayed_brc <= pps_shift_reg_brc[pps_in_to_rclk_delay_brc];
|
||||
pps_delayed_brc_debug <= pps_shift_reg_brc[pps_in_to_rclk_delay_brc];
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PPS clock domain crossing
|
||||
//---------------------------------------------------------------------------
|
||||
// On the aligned edge of BRC and RC this synchronizer is just a two stage
|
||||
// delay into the RC domain as the edges occur at the same time the tools
|
||||
// should make sure we close timing on this edge
|
||||
|
||||
synchronizer #(
|
||||
.FALSE_PATH_TO_IN (0)
|
||||
) synchronizer_pps_rclk (
|
||||
.clk (radio_clk_shifted),
|
||||
.rst (1'b0),
|
||||
.in (pps_delayed_brc),
|
||||
.out (pps_in_rclk)
|
||||
);
|
||||
|
||||
// Debug signals
|
||||
// Exported to verify clock alignment after a SYNC event.
|
||||
// This should happen synchronous to base_ref_clk and radio_clk_shifted.
|
||||
// It should rise just after the rising edge of both to be stable for the
|
||||
// next clock cycle
|
||||
assign debug[0] = pps_delayed_brc_debug;
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"), // Optional: "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT(1'b0), // Initial state of the O pin (output)
|
||||
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) ODDR_clk_debug_1 (
|
||||
.Q(debug[1]), // Connect to the OBUF input
|
||||
.C(radio_clk_shifted), // Clock input from the BUFG
|
||||
.CE(1'b1), // Clock Enable (always high for continuous clock)
|
||||
.R(1'b0), // Reset (always low)
|
||||
.S(1'b0), // Set (always low)
|
||||
.D1(1'b1), // Data input 1 (High)
|
||||
.D2(1'b0) // Data input 2 (Low)
|
||||
);
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"), // Optional: "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT(1'b0), // Initial state of the O pin (output)
|
||||
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) ODDR_clk_debug_2 (
|
||||
.Q(debug[2]), // Connect to the OBUF input
|
||||
.C(base_ref_clk), // Clock input from the BUFG
|
||||
.CE(1'b1), // Clock Enable (always high for continuous clock)
|
||||
.R(1'b0), // Reset (always low)
|
||||
.S(1'b0), // Set (always low)
|
||||
.D1(1'b1), // Data input 1 (High)
|
||||
.D2(1'b0) // Data input 2 (Low)
|
||||
);
|
||||
|
||||
endmodule : b3xx_pps_sync
|
||||
|
||||
`default_nettype wire
|
||||
50
fpga/usrp3/top/b300/build_b310.tcl
Normal file
50
fpga/usrp3/top/b300/build_b310.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
|
||||
source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
|
||||
|
||||
# STEP#1: Create project, add sources, refresh IP
|
||||
vivado_utils::initialize_project
|
||||
|
||||
# STEP#2: Run synthesis
|
||||
vivado_utils::synthesize_design
|
||||
vivado_utils::generate_post_synth_reports
|
||||
|
||||
# STEP#3: Run implementation strategy
|
||||
set b310_strategy [dict create]
|
||||
dict set b310_strategy "implementation.incremental" 0
|
||||
dict set b310_strategy "opt_design.is_enabled" 1
|
||||
dict set b310_strategy "opt_design.directive" "NoBramPowerOpt"
|
||||
dict set b310_strategy "post_opt_power_opt_design.is_enabled" 0
|
||||
dict set b310_strategy "place_design.directive" "ExtraNetDelay_high"
|
||||
dict set b310_strategy "post_place_power_opt_design.is_enabled" 0
|
||||
dict set b310_strategy "post_place_phys_opt_design.is_enabled" 1
|
||||
dict set b310_strategy "post_place_phys_opt_design.directive" "AggressiveExplore"
|
||||
dict set b310_strategy "route_design.directive" "Explore"
|
||||
dict set b310_strategy "route_design.more_options" "-tns_cleanup"
|
||||
dict set b310_strategy "post_route_phys_opt_design.is_enabled" 1
|
||||
dict set b310_strategy "post_route_phys_opt_design.directive" "Explore"
|
||||
vivado_strategies::implement_design $b310_strategy
|
||||
|
||||
# STEP#4: Generate reports
|
||||
vivado_utils::generate_post_route_reports
|
||||
|
||||
# STEP#5: Generate a bitstream, netlist and debug probes
|
||||
|
||||
# Enable over-temperature power down
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [get_designs *]
|
||||
# STC3 Requirement: Disable waiting for DCI Match
|
||||
set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [get_designs *]
|
||||
# STC3 Requirement: No bitstream compression
|
||||
set_property BITSTREAM.GENERAL.COMPRESS False [get_designs *]
|
||||
# Use 6MHz clock to configure bitstream
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 6 [get_designs *]
|
||||
|
||||
vivado_utils::write_implementation_outputs
|
||||
|
||||
# Cleanup
|
||||
vivado_utils::close_batch_project
|
||||
668
fpga/usrp3/top/b300/constraints/b310.xdc
Normal file
668
fpga/usrp3/top/b300/constraints/b310.xdc
Normal file
@ -0,0 +1,668 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
|
||||
######################################################################################
|
||||
# Pin Location Information
|
||||
######################################################################################
|
||||
|
||||
# CLOCKS
|
||||
set_property PACKAGE_PIN F6 [get_ports PCIE_REF_CLK_P]
|
||||
set_property PACKAGE_PIN F5 [get_ports PCIE_REF_CLK_N]
|
||||
|
||||
set_property PACKAGE_PIN AB17 [get_ports DEVCLK_P]
|
||||
set_property PACKAGE_PIN AC17 [get_ports DEVCLK_N]
|
||||
|
||||
set_property PACKAGE_PIN AD18 [get_ports FPGA_REFCLK_N]
|
||||
set_property PACKAGE_PIN AC18 [get_ports FPGA_REFCLK_P]
|
||||
set_property PACKAGE_PIN AC16 [get_ports EXT_REFCLK_N]
|
||||
set_property PACKAGE_PIN AB16 [get_ports EXT_REFCLK_P]
|
||||
set_property PACKAGE_PIN K5 [get_ports JESD_CLK_N]
|
||||
set_property PACKAGE_PIN K6 [get_ports JESD_CLK_P]
|
||||
set_property PACKAGE_PIN AA18 [get_ports SYSREF_N]
|
||||
set_property PACKAGE_PIN AA17 [get_ports SYSREF_P]
|
||||
|
||||
# RESETS
|
||||
|
||||
set_property PACKAGE_PIN A15 [get_ports PCIE_PRESENT_N]
|
||||
set_property PACKAGE_PIN K21 [get_ports PCIE_RESET_N]
|
||||
|
||||
set_property PACKAGE_PIN H26 [get_ports PG_1V2]
|
||||
set_property PACKAGE_PIN E16 [get_ports TYPEC_PWR_NEGOTIATED]
|
||||
set_property PACKAGE_PIN K17 [get_ports VBUS_ALERT_N]
|
||||
set_property PACKAGE_PIN B15 [get_ports GT_25W_PWR_SRC]
|
||||
|
||||
set_property PACKAGE_PIN V26 [get_ports {ADRV_GPINT[0]}]
|
||||
set_property PACKAGE_PIN Y26 [get_ports {ADRV_GPINT[1]}]
|
||||
set_property PACKAGE_PIN B19 [get_ports {ADRV_GPIO[0]}]
|
||||
set_property PACKAGE_PIN E21 [get_ports {ADRV_GPIO[1]}]
|
||||
set_property PACKAGE_PIN F23 [get_ports {ADRV_GPIO[2]}]
|
||||
set_property PACKAGE_PIN E23 [get_ports {ADRV_GPIO[3]}]
|
||||
set_property PACKAGE_PIN F22 [get_ports {ADRV_GPIO[4]}]
|
||||
set_property PACKAGE_PIN C23 [get_ports {ADRV_GPIO[5]}]
|
||||
set_property PACKAGE_PIN AE23 [get_ports {ADRV_GPIO[6]}]
|
||||
set_property PACKAGE_PIN AE22 [get_ports {ADRV_GPIO[7]}]
|
||||
set_property PACKAGE_PIN D23 [get_ports ADRV_ORXA_CTRL]
|
||||
set_property PACKAGE_PIN AC21 [get_ports ADRV_ORXB_CTRL]
|
||||
set_property PACKAGE_PIN E26 [get_ports ADRV_RESET_N]
|
||||
set_property PACKAGE_PIN J25 [get_ports ADRV_SPI_CLK]
|
||||
set_property PACKAGE_PIN AA25 [get_ports ADRV_SPI_DIO]
|
||||
set_property PACKAGE_PIN AE26 [get_ports ADRV_SPI_DO]
|
||||
set_property PACKAGE_PIN W25 [get_ports ADRV_SPI_EN_N]
|
||||
set_property PACKAGE_PIN AB20 [get_ports {ADRV_SYNCIN_N[0]}]
|
||||
set_property PACKAGE_PIN AE20 [get_ports {ADRV_SYNCIN_N[1]}]
|
||||
set_property PACKAGE_PIN AA20 [get_ports {ADRV_SYNCIN_N[2]}]
|
||||
set_property PACKAGE_PIN AB19 [get_ports {ADRV_SYNCIN_P[0]}]
|
||||
set_property PACKAGE_PIN AD20 [get_ports {ADRV_SYNCIN_P[1]}]
|
||||
set_property PACKAGE_PIN AA19 [get_ports {ADRV_SYNCIN_P[2]}]
|
||||
set_property PACKAGE_PIN AD19 [get_ports {ADRV_SYNCOUT_N[0]}]
|
||||
set_property PACKAGE_PIN AB15 [get_ports {ADRV_SYNCOUT_N[1]}]
|
||||
set_property PACKAGE_PIN AC19 [get_ports {ADRV_SYNCOUT_P[0]}]
|
||||
set_property PACKAGE_PIN AB14 [get_ports {ADRV_SYNCOUT_P[1]}]
|
||||
set_property PACKAGE_PIN Y25 [get_ports ADRV_TEST_EN]
|
||||
set_property PACKAGE_PIN C19 [get_ports ADRV_TRXA_CTRL]
|
||||
set_property PACKAGE_PIN A19 [get_ports ADRV_TRXB_CTRL]
|
||||
set_property PACKAGE_PIN F24 [get_ports ADRV_TRXC_CTRL]
|
||||
set_property PACKAGE_PIN D24 [get_ports ADRV_TRXD_CTRL]
|
||||
set_property PACKAGE_PIN AD21 [get_ports ADRV_TRXE_CTRL]
|
||||
set_property PACKAGE_PIN AF22 [get_ports ADRV_TRXF_CTRL]
|
||||
set_property PACKAGE_PIN AC22 [get_ports ADRV_TRXG_CTRL]
|
||||
set_property PACKAGE_PIN AF23 [get_ports ADRV_TRXH_CTRL]
|
||||
|
||||
set_property PACKAGE_PIN U24 [get_ports JTAG_CPLD_TCK]
|
||||
set_property PACKAGE_PIN U26 [get_ports JTAG_CPLD_TDI]
|
||||
set_property PACKAGE_PIN J26 [get_ports JTAG_CPLD_TDO]
|
||||
set_property PACKAGE_PIN U25 [get_ports JTAG_CPLD_TMS]
|
||||
set_property PACKAGE_PIN V13 [get_ports JTAG_TBOLT_TCK]
|
||||
set_property PACKAGE_PIN M16 [get_ports JTAG_TBOLT_TDI]
|
||||
set_property PACKAGE_PIN D15 [get_ports JTAG_TBOLT_TDO]
|
||||
set_property PACKAGE_PIN L17 [get_ports JTAG_TBOLT_TMS]
|
||||
|
||||
set_property PACKAGE_PIN T20 [get_ports LMK32_CS_N]
|
||||
set_property PACKAGE_PIN T22 [get_ports LMK32_MISO]
|
||||
set_property PACKAGE_PIN U19 [get_ports LMK32_MOSI]
|
||||
set_property PACKAGE_PIN P19 [get_ports LMK32_RESET]
|
||||
set_property PACKAGE_PIN T18 [get_ports LMK32_SCLK]
|
||||
set_property PACKAGE_PIN R22 [get_ports LMK32_STATUS]
|
||||
set_property PACKAGE_PIN U20 [get_ports LMK32_VCXO_SEL_122M88]
|
||||
set_property PACKAGE_PIN T24 [get_ports LMK053_CS_N]
|
||||
set_property PACKAGE_PIN R25 [get_ports LMK053_MISO]
|
||||
set_property PACKAGE_PIN R26 [get_ports LMK053_MOSI]
|
||||
set_property PACKAGE_PIN R23 [get_ports LMK053_SCLK]
|
||||
set_property PACKAGE_PIN AF15 [get_ports LMK_SYNC_REVA]
|
||||
set_property PACKAGE_PIN P18 [get_ports LMK_SYNC]
|
||||
|
||||
set_property PACKAGE_PIN R21 [get_ports GPS_PPS_OUT]
|
||||
set_property PACKAGE_PIN N24 [get_ports GPS_PWR_FAULT_N]
|
||||
set_property PACKAGE_PIN Y23 [get_ports {GPS_REF[0]}]
|
||||
set_property PACKAGE_PIN Y22 [get_ports {GPS_REF[1]}]
|
||||
set_property PACKAGE_PIN N26 [get_ports GPS_REFSEL]
|
||||
set_property PACKAGE_PIN M26 [get_ports GPS_RESET_N]
|
||||
set_property PACKAGE_PIN AF20 [get_ports GPS_SECREF_N]
|
||||
set_property PACKAGE_PIN AF19 [get_ports GPS_SECREF_P]
|
||||
set_property PACKAGE_PIN K25 [get_ports GPS_EXTINT]
|
||||
set_property PACKAGE_PIN T25 [get_ports GPS_UART_TOFPGA]
|
||||
set_property PACKAGE_PIN T23 [get_ports GPS_UART_TOGPS]
|
||||
|
||||
set_property PACKAGE_PIN E15 [get_ports CPLD_EXT_RST_R_N]
|
||||
set_property PACKAGE_PIN F25 [get_ports CPLD_OSC_EN]
|
||||
set_property PACKAGE_PIN G17 [get_ports CPLD_RX_CLK]
|
||||
set_property PACKAGE_PIN B17 [get_ports CPLD_RX_CLKEN]
|
||||
set_property PACKAGE_PIN G15 [get_ports {CPLD_RX_DATA[0]}]
|
||||
set_property PACKAGE_PIN J15 [get_ports {CPLD_RX_DATA[1]}]
|
||||
set_property PACKAGE_PIN G19 [get_ports {CPLD_RX_DATA[2]}]
|
||||
set_property PACKAGE_PIN H18 [get_ports {CPLD_RX_DATA[3]}]
|
||||
set_property PACKAGE_PIN A17 [get_ports {CPLD_RX_DATA[4]}]
|
||||
set_property PACKAGE_PIN D18 [get_ports {CPLD_RX_DATA[5]}]
|
||||
set_property PACKAGE_PIN J16 [get_ports {CPLD_RX_DATA[6]}]
|
||||
set_property PACKAGE_PIN D19 [get_ports {CPLD_RX_DATA[7]}]
|
||||
set_property PACKAGE_PIN E18 [get_ports CPLD_TX_CLK]
|
||||
set_property PACKAGE_PIN F20 [get_ports CPLD_TX_CLKEN]
|
||||
set_property PACKAGE_PIN H17 [get_ports {CPLD_TX_DATA[0]}]
|
||||
set_property PACKAGE_PIN H16 [get_ports {CPLD_TX_DATA[1]}]
|
||||
set_property PACKAGE_PIN D20 [get_ports {CPLD_TX_DATA[2]}]
|
||||
set_property PACKAGE_PIN F15 [get_ports {CPLD_TX_DATA[3]}]
|
||||
set_property PACKAGE_PIN F19 [get_ports {CPLD_TX_DATA[4]}]
|
||||
set_property PACKAGE_PIN E20 [get_ports {CPLD_TX_DATA[5]}]
|
||||
set_property PACKAGE_PIN H19 [get_ports {CPLD_TX_DATA[6]}]
|
||||
set_property PACKAGE_PIN G20 [get_ports {CPLD_TX_DATA[7]}]
|
||||
set_property PACKAGE_PIN D25 [get_ports PCIE_RESET_N_TO_CPLD]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN B10 [get_ports {FP_GPIO[0]}]
|
||||
set_property PACKAGE_PIN A9 [get_ports {FP_GPIO[1]}]
|
||||
set_property PACKAGE_PIN D9 [get_ports {FP_GPIO[2]}]
|
||||
set_property PACKAGE_PIN A13 [get_ports {FP_GPIO[3]}]
|
||||
set_property PACKAGE_PIN B11 [get_ports {FP_GPIO[4]}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {FP_GPIO[5]}]
|
||||
set_property PACKAGE_PIN B9 [get_ports {FP_GPIO[6]}]
|
||||
set_property PACKAGE_PIN C9 [get_ports {FP_GPIO[7]}]
|
||||
set_property PACKAGE_PIN A12 [get_ports {FP_GPIO[8]}]
|
||||
set_property PACKAGE_PIN B12 [get_ports {FP_GPIO[9]}]
|
||||
|
||||
set_property PACKAGE_PIN W13 [get_ports LED_CLK_STS_GRN]
|
||||
set_property PACKAGE_PIN AA15 [get_ports LED_PWR_STS_BLUE]
|
||||
set_property PACKAGE_PIN AC14 [get_ports LED_PWR_STS_ORANGE]
|
||||
set_property PACKAGE_PIN AB25 [get_ports {LED_TX_GRN[0]}]
|
||||
set_property PACKAGE_PIN AC26 [get_ports {LED_TX_GRN[1]}]
|
||||
set_property PACKAGE_PIN AB22 [get_ports {LED_TX_RED[0]}]
|
||||
set_property PACKAGE_PIN AD26 [get_ports {LED_TX_RED[1]}]
|
||||
set_property PACKAGE_PIN G26 [get_ports {LED_RX_GRN[0]}]
|
||||
set_property PACKAGE_PIN AD25 [get_ports {LED_RX_GRN[1]}]
|
||||
set_property PACKAGE_PIN D8 [get_ports LED_FPGA_CONFIG_GRN]
|
||||
|
||||
set_property PACKAGE_PIN L25 [get_ports ANT_PWR_EN]
|
||||
set_property PACKAGE_PIN R20 [get_ports {RX_SW_CTRL[0]}]
|
||||
set_property PACKAGE_PIN D14 [get_ports {RX_SW_CTRL[1]}]
|
||||
set_property PACKAGE_PIN B14 [get_ports {ENABLE_TXRX_TDR[0]}]
|
||||
set_property PACKAGE_PIN A14 [get_ports {ENABLE_TXRX_TDR[1]}]
|
||||
|
||||
set_property PACKAGE_PIN U17 [get_ports DAC_CS_N]
|
||||
set_property PACKAGE_PIN R17 [get_ports DAC_MOSI]
|
||||
set_property PACKAGE_PIN T17 [get_ports DAC_SCLK]
|
||||
set_property PACKAGE_PIN R16 [get_ports DAC_CLR_N]
|
||||
|
||||
set_property PACKAGE_PIN R18 [get_ports MISC_I2C_SCL]
|
||||
set_property PACKAGE_PIN T19 [get_ports MISC_I2C_SDA]
|
||||
|
||||
set_property PACKAGE_PIN K16 [get_ports TBOLT_SCL]
|
||||
set_property PACKAGE_PIN K15 [get_ports TBOLT_SDA]
|
||||
set_property PACKAGE_PIN C14 [get_ports {TBOLT_RIDGE_RESET_N}]
|
||||
set_property PACKAGE_PIN G16 [get_ports {TBOLT_PD_CTRL_RESET}]
|
||||
|
||||
set_property PACKAGE_PIN K26 [get_ports NSYNC_GPIO0]
|
||||
set_property PACKAGE_PIN P25 [get_ports NSYNC_PDN]
|
||||
set_property PACKAGE_PIN M25 [get_ports {NSYNC_STATUS[0]}]
|
||||
set_property PACKAGE_PIN P21 [get_ports {NSYNC_STATUS[1]}]
|
||||
|
||||
set_property PACKAGE_PIN A8 [get_ports {EXT_PPS_IN}]
|
||||
set_property PACKAGE_PIN G9 [get_ports {PPS_OUT[0]}]
|
||||
set_property PACKAGE_PIN G10 [get_ports {PPS_OUT[1]}]
|
||||
set_property PACKAGE_PIN H8 [get_ports {PPS_OUT[2]}]
|
||||
set_property PACKAGE_PIN H9 [get_ports {PPS_OUT[3]}]
|
||||
|
||||
set_property PACKAGE_PIN U16 [get_ports REF_CLK_SEL]
|
||||
set_property PACKAGE_PIN P24 [get_ports TCXO_EN_N]
|
||||
|
||||
set_property PACKAGE_PIN F8 [get_ports AUTH_SDA]
|
||||
|
||||
# JESD204B
|
||||
set_property PACKAGE_PIN P1 [get_ports {JESD_TX_N[0]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {JESD_TX_P[0]}]
|
||||
set_property PACKAGE_PIN M1 [get_ports {JESD_TX_N[1]}]
|
||||
set_property PACKAGE_PIN M2 [get_ports {JESD_TX_P[1]}]
|
||||
|
||||
set_property PACKAGE_PIN R3 [get_ports {JESD_RX_N[0]}]
|
||||
set_property PACKAGE_PIN R4 [get_ports {JESD_RX_P[0]}]
|
||||
set_property PACKAGE_PIN N3 [get_ports {JESD_RX_N[1]}]
|
||||
set_property PACKAGE_PIN N4 [get_ports {JESD_RX_P[1]}]
|
||||
|
||||
# These pins are routed, but unused
|
||||
# set_property PACKAGE_PIN K1 [get_ports {JESD_TX_N[2]}]
|
||||
# set_property PACKAGE_PIN K2 [get_ports {JESD_TX_P[2]}]
|
||||
# set_property PACKAGE_PIN H1 [get_ports {JESD_TX_N[3]}]
|
||||
# set_property PACKAGE_PIN H2 [get_ports {JESD_TX_P[3]}]
|
||||
# set_property PACKAGE_PIN L3 [get_ports {JESD_RX_N[2]}]
|
||||
# set_property PACKAGE_PIN L4 [get_ports {JESD_RX_P[2]}]
|
||||
# set_property PACKAGE_PIN J3 [get_ports {JESD_RX_N[3]}]
|
||||
# set_property PACKAGE_PIN J4 [get_ports {JESD_RX_P[3]}]
|
||||
|
||||
|
||||
######################################################################################
|
||||
# Pin Drive information
|
||||
######################################################################################
|
||||
#Defaulted drives to 8mA slow, may change driver strength from there as starting point
|
||||
|
||||
set_property IOSTANDARD LVDS [get_ports {DEVCLK_*}]
|
||||
set_property DIFF_TERM TRUE [get_ports {DEVCLK_*}]
|
||||
set_property IOSTANDARD LVDS [get_ports {FPGA_REFCLK_*}]
|
||||
set_property DIFF_TERM TRUE [get_ports {FPGA_REFCLK_*}]
|
||||
set_property IOSTANDARD LVDS [get_ports {EXT_REFCLK_*}]
|
||||
set_property DIFF_TERM TRUE [get_ports {EXT_REFCLK_*}]
|
||||
set_property IOSTANDARD LVDS [get_ports {SYSREF_*}]
|
||||
set_property DIFF_TERM TRUE [get_ports {SYSREF_*}]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PRESENT_N]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports PG_1V2]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports TYPEC_PWR_NEGOTIATED]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports VBUS_ALERT_N]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GT_25W_PWR_SRC]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPINT[0]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPINT[0]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPINT[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPINT[1]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPINT[1]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPINT[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[0]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[0]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[1]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[1]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[2]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[2]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[3]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[3]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[4]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[4]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[4]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[5]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[5]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[5]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[6]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[6]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[6]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {ADRV_GPIO[7]}]
|
||||
set_property DRIVE 8 [get_ports {ADRV_GPIO[7]}]
|
||||
set_property SLEW SLOW [get_ports {ADRV_GPIO[7]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_SPI_DIO]
|
||||
set_property DRIVE 8 [get_ports ADRV_SPI_DIO]
|
||||
set_property SLEW SLOW [get_ports ADRV_SPI_DIO]
|
||||
set_property IOSTANDARD LVDS [get_ports {ADRV_SYNCOUT_*}]
|
||||
set_property DIFF_TERM TRUE [get_ports {ADRV_SYNCOUT_*}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_ORXA_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_ORXA_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_ORXA_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_ORXB_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_ORXB_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_ORXB_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_RESET_N]
|
||||
set_property DRIVE 8 [get_ports ADRV_RESET_N]
|
||||
set_property SLEW SLOW [get_ports ADRV_RESET_N]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_SPI_CLK]
|
||||
set_property DRIVE 8 [get_ports ADRV_SPI_CLK]
|
||||
set_property SLEW SLOW [get_ports ADRV_SPI_CLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_SPI_DO]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_SPI_EN_N]
|
||||
set_property DRIVE 8 [get_ports ADRV_SPI_EN_N]
|
||||
set_property SLEW SLOW [get_ports ADRV_SPI_EN_N]
|
||||
set_property IOSTANDARD LVDS [get_ports {ADRV_SYNCIN_*}]
|
||||
set_property DIFF_TERM TRUE [get_ports {ADRV_SYNCIN_*}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TEST_EN]
|
||||
set_property DRIVE 8 [get_ports ADRV_TEST_EN]
|
||||
set_property SLEW SLOW [get_ports ADRV_TEST_EN]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXA_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXA_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXA_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXB_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXB_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXB_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXC_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXC_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXC_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXD_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXD_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXD_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXE_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXE_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXE_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXF_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXF_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXF_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXG_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXG_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXG_CTRL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADRV_TRXH_CTRL]
|
||||
set_property DRIVE 8 [get_ports ADRV_TRXH_CTRL]
|
||||
set_property SLEW SLOW [get_ports ADRV_TRXH_CTRL]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_CPLD_TCK]
|
||||
set_property DRIVE 8 [get_ports JTAG_CPLD_TCK]
|
||||
set_property SLEW SLOW [get_ports JTAG_CPLD_TCK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_CPLD_TDI]
|
||||
set_property DRIVE 8 [get_ports JTAG_CPLD_TDI]
|
||||
set_property SLEW SLOW [get_ports JTAG_CPLD_TDI]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_CPLD_TMS]
|
||||
set_property DRIVE 8 [get_ports JTAG_CPLD_TMS]
|
||||
set_property SLEW SLOW [get_ports JTAG_CPLD_TMS]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_TBOLT_TCK]
|
||||
set_property DRIVE 8 [get_ports JTAG_TBOLT_TCK]
|
||||
set_property SLEW SLOW [get_ports JTAG_TBOLT_TCK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_TBOLT_TDI]
|
||||
set_property DRIVE 8 [get_ports JTAG_TBOLT_TDI]
|
||||
set_property SLEW SLOW [get_ports JTAG_TBOLT_TDI]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_TBOLT_TMS]
|
||||
set_property DRIVE 8 [get_ports JTAG_TBOLT_TMS]
|
||||
set_property SLEW SLOW [get_ports JTAG_TBOLT_TMS]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_CPLD_TDO]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports JTAG_TBOLT_TDO]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK053_MISO]
|
||||
set_property DRIVE 8 [get_ports LMK053_MISO]
|
||||
set_property SLEW SLOW [get_ports LMK053_MISO]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK053_MOSI]
|
||||
set_property DRIVE 8 [get_ports LMK053_MOSI]
|
||||
set_property SLEW SLOW [get_ports LMK053_MOSI]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_MISO]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_STATUS]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_CS_N]
|
||||
set_property DRIVE 8 [get_ports LMK32_CS_N]
|
||||
set_property SLEW SLOW [get_ports LMK32_CS_N]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_MOSI]
|
||||
set_property DRIVE 8 [get_ports LMK32_MOSI]
|
||||
set_property SLEW SLOW [get_ports LMK32_MOSI]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_RESET]
|
||||
set_property DRIVE 8 [get_ports LMK32_RESET]
|
||||
set_property SLEW SLOW [get_ports LMK32_RESET]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_SCLK]
|
||||
set_property DRIVE 8 [get_ports LMK32_SCLK]
|
||||
set_property SLEW SLOW [get_ports LMK32_SCLK]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK32_VCXO_SEL_122M88]
|
||||
set_property DRIVE 8 [get_ports LMK32_VCXO_SEL_122M88]
|
||||
set_property SLEW SLOW [get_ports LMK32_VCXO_SEL_122M88]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK053_CS_N]
|
||||
set_property DRIVE 8 [get_ports LMK053_CS_N]
|
||||
set_property SLEW SLOW [get_ports LMK053_CS_N]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK053_SCLK]
|
||||
set_property DRIVE 8 [get_ports LMK053_SCLK]
|
||||
set_property SLEW SLOW [get_ports LMK053_SCLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports LMK_SYNC_REVA]
|
||||
set_property DRIVE 16 [get_ports LMK_SYNC_REVA]
|
||||
set_property SLEW FAST [get_ports LMK_SYNC_REVA]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LMK_SYNC]
|
||||
set_property DRIVE 16 [get_ports LMK_SYNC]
|
||||
set_property SLEW FAST [get_ports LMK_SYNC]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_PPS_OUT]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_PWR_FAULT_N]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPS_REF[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPS_REF[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_UART_TOFPGA]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_REFSEL]
|
||||
set_property DRIVE 8 [get_ports GPS_REFSEL]
|
||||
set_property SLEW SLOW [get_ports GPS_REFSEL]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_RESET_N]
|
||||
set_property DRIVE 8 [get_ports GPS_RESET_N]
|
||||
set_property SLEW SLOW [get_ports GPS_RESET_N]
|
||||
set_property IOSTANDARD LVDS [get_ports {GPS_SECREF_*}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_EXTINT]
|
||||
set_property DRIVE 8 [get_ports GPS_EXTINT]
|
||||
set_property SLEW SLOW [get_ports GPS_EXTINT]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports GPS_UART_TOGPS]
|
||||
set_property DRIVE 8 [get_ports GPS_UART_TOGPS]
|
||||
set_property SLEW SLOW [get_ports GPS_UART_TOGPS]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CPLD_TX_CLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CPLD_TX_CLKEN]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[4]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[5]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[6]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_TX_DATA[7]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CPLD_EXT_RST_R_N]
|
||||
set_property DRIVE 8 [get_ports CPLD_EXT_RST_R_N]
|
||||
set_property SLEW FAST [get_ports CPLD_EXT_RST_R_N]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CPLD_OSC_EN]
|
||||
set_property DRIVE 4 [get_ports CPLD_OSC_EN]
|
||||
set_property SLEW SLOW [get_ports CPLD_OSC_EN]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CPLD_RX_CLK]
|
||||
set_property DRIVE 8 [get_ports CPLD_RX_CLK]
|
||||
set_property SLEW FAST [get_ports CPLD_RX_CLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CPLD_RX_CLKEN]
|
||||
set_property DRIVE 8 [get_ports CPLD_RX_CLKEN]
|
||||
set_property SLEW FAST [get_ports CPLD_RX_CLKEN]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[0]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[0]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[1]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[1]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[2]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[2]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[3]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[3]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[4]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[4]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[4]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[5]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[5]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[5]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[6]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[6]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[6]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {CPLD_RX_DATA[7]}]
|
||||
set_property DRIVE 8 [get_ports {CPLD_RX_DATA[7]}]
|
||||
set_property SLEW FAST [get_ports {CPLD_RX_DATA[7]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N_TO_CPLD]
|
||||
set_property DRIVE 8 [get_ports PCIE_RESET_N_TO_CPLD]
|
||||
set_property SLEW SLOW [get_ports PCIE_RESET_N_TO_CPLD]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[0]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[0]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[1]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[1]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[2]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[2]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[3]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[3]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[4]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[4]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[5]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[5]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[6]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[6]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[7]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[7]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[8]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[8]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {FP_GPIO[9]}]
|
||||
set_property DRIVE 8 [get_ports {FP_GPIO[9]}]
|
||||
set_property SLEW SLOW [get_ports {FP_GPIO[9]}]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports LED_CLK_STS_GRN]
|
||||
set_property DRIVE 4 [get_ports LED_CLK_STS_GRN]
|
||||
set_property SLEW SLOW [get_ports LED_CLK_STS_GRN]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports LED_PWR_STS_BLUE]
|
||||
set_property DRIVE 4 [get_ports LED_PWR_STS_BLUE]
|
||||
set_property SLEW SLOW [get_ports LED_PWR_STS_BLUE]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports LED_PWR_STS_ORANGE]
|
||||
set_property DRIVE 4 [get_ports LED_PWR_STS_ORANGE]
|
||||
set_property SLEW SLOW [get_ports LED_PWR_STS_ORANGE]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {LED_TX_GRN[0]}]
|
||||
set_property DRIVE 4 [get_ports {LED_TX_GRN[0]}]
|
||||
set_property SLEW SLOW [get_ports {LED_TX_GRN[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {LED_TX_GRN[1]}]
|
||||
set_property DRIVE 4 [get_ports {LED_TX_GRN[1]}]
|
||||
set_property SLEW SLOW [get_ports {LED_TX_GRN[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {LED_TX_RED[0]}]
|
||||
set_property DRIVE 4 [get_ports {LED_TX_RED[0]}]
|
||||
set_property SLEW SLOW [get_ports {LED_TX_RED[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {LED_TX_RED[1]}]
|
||||
set_property DRIVE 4 [get_ports {LED_TX_RED[1]}]
|
||||
set_property SLEW SLOW [get_ports {LED_TX_RED[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {LED_RX_GRN[0]}]
|
||||
set_property DRIVE 4 [get_ports {LED_RX_GRN[0]}]
|
||||
set_property SLEW SLOW [get_ports {LED_RX_GRN[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {LED_RX_GRN[1]}]
|
||||
set_property DRIVE 4 [get_ports {LED_RX_GRN[1]}]
|
||||
set_property SLEW SLOW [get_ports {LED_RX_GRN[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports LED_FPGA_CONFIG_GRN]
|
||||
set_property DRIVE 8 [get_ports LED_FPGA_CONFIG_GRN]
|
||||
set_property SLEW SLOW [get_ports LED_FPGA_CONFIG_GRN]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ANT_PWR_EN]
|
||||
set_property DRIVE 4 [get_ports ANT_PWR_EN]
|
||||
set_property SLEW SLOW [get_ports ANT_PWR_EN]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {RX_SW_CTRL[0]}]
|
||||
set_property DRIVE 8 [get_ports {RX_SW_CTRL[0]}]
|
||||
set_property SLEW SLOW [get_ports {RX_SW_CTRL[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {RX_SW_CTRL[1]}]
|
||||
set_property DRIVE 8 [get_ports {RX_SW_CTRL[1]}]
|
||||
set_property SLEW SLOW [get_ports {RX_SW_CTRL[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE_TXRX_TDR[0]}]
|
||||
set_property DRIVE 8 [get_ports {ENABLE_TXRX_TDR[0]}]
|
||||
set_property SLEW SLOW [get_ports {ENABLE_TXRX_TDR[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE_TXRX_TDR[1]}]
|
||||
set_property DRIVE 8 [get_ports {ENABLE_TXRX_TDR[1]}]
|
||||
set_property SLEW SLOW [get_ports {ENABLE_TXRX_TDR[1]}]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_CS_N]
|
||||
set_property DRIVE 8 [get_ports DAC_CS_N]
|
||||
set_property SLEW SLOW [get_ports DAC_CS_N]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_MOSI]
|
||||
set_property DRIVE 8 [get_ports DAC_MOSI]
|
||||
set_property SLEW SLOW [get_ports DAC_MOSI]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_SCLK]
|
||||
set_property DRIVE 8 [get_ports DAC_SCLK]
|
||||
set_property SLEW SLOW [get_ports DAC_SCLK]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_CLR_N]
|
||||
set_property DRIVE 8 [get_ports DAC_CLR_N]
|
||||
set_property SLEW SLOW [get_ports DAC_CLR_N]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports MISC_I2C_SCL]
|
||||
set_property DRIVE 8 [get_ports MISC_I2C_SCL]
|
||||
set_property SLEW SLOW [get_ports MISC_I2C_SCL]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports MISC_I2C_SDA]
|
||||
set_property DRIVE 8 [get_ports MISC_I2C_SDA]
|
||||
set_property SLEW SLOW [get_ports MISC_I2C_SDA]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports TBOLT_SCL]
|
||||
set_property DRIVE 8 [get_ports TBOLT_SCL]
|
||||
set_property SLEW SLOW [get_ports TBOLT_SCL]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports TBOLT_SDA]
|
||||
set_property DRIVE 8 [get_ports TBOLT_SDA]
|
||||
set_property SLEW SLOW [get_ports TBOLT_SDA]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {TBOLT_RIDGE_RESET_N}]
|
||||
set_property DRIVE 8 [get_ports {TBOLT_RIDGE_RESET_N}]
|
||||
set_property SLEW SLOW [get_ports {TBOLT_RIDGE_RESET_N}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {TBOLT_PD_CTRL_RESET}]
|
||||
set_property DRIVE 8 [get_ports {TBOLT_PD_CTRL_RESET}]
|
||||
set_property SLEW SLOW [get_ports {TBOLT_PD_CTRL_RESET}]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports NSYNC_GPIO0]
|
||||
set_property DRIVE 8 [get_ports NSYNC_GPIO0]
|
||||
set_property SLEW SLOW [get_ports NSYNC_GPIO0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports NSYNC_PDN]
|
||||
set_property SLEW SLOW [get_ports NSYNC_PDN]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {NSYNC_STATUS[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {NSYNC_STATUS[1]}]
|
||||
|
||||
set_property IOSTANDARD PCI33_3 [get_ports EXT_PPS_IN]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {PPS_OUT[0]}]
|
||||
set_property DRIVE 16 [get_ports {PPS_OUT[0]}]
|
||||
set_property SLEW FAST [get_ports {PPS_OUT[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {PPS_OUT[1]}]
|
||||
set_property DRIVE 16 [get_ports {PPS_OUT[1]}]
|
||||
set_property SLEW FAST [get_ports {PPS_OUT[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {PPS_OUT[2]}]
|
||||
set_property DRIVE 16 [get_ports {PPS_OUT[2]}]
|
||||
set_property SLEW FAST [get_ports {PPS_OUT[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {PPS_OUT[3]}]
|
||||
set_property DRIVE 16 [get_ports {PPS_OUT[3]}]
|
||||
set_property SLEW FAST [get_ports {PPS_OUT[3]}]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports REF_CLK_SEL]
|
||||
set_property DRIVE 8 [get_ports REF_CLK_SEL]
|
||||
set_property SLEW SLOW [get_ports REF_CLK_SEL]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports TCXO_EN_N]
|
||||
set_property DRIVE 4 [get_ports TCXO_EN_N]
|
||||
set_property SLEW SLOW [get_ports TCXO_EN_N]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports AUTH_SDA]
|
||||
set_property DRIVE 4 [get_ports AUTH_SDA]
|
||||
set_property SLEW SLOW [get_ports AUTH_SDA]
|
||||
|
||||
# DRAM internal VREF - (Required for SYSCLK)
|
||||
set_property INTERNAL_VREF 0.75 [get_iobanks 33]
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# PCI Express Section. Most constraints here come from adapting a Xilinx generated
|
||||
# constraint.
|
||||
#-------------------------------------------------------------
|
||||
|
||||
#--------------
|
||||
# PCIe Reset pin IO Standard.
|
||||
#
|
||||
# Formerly these constraints were provided (copied from the Xilinx example project).
|
||||
# Since the InChWORM really only cares about the reset input to the core (which may be
|
||||
# composed of the pin and other components) the actual PCIe reset pin constraints
|
||||
# are left to the user to select whatever polarity (pullup or pulldown) and IO standard
|
||||
# fit best the product design.
|
||||
|
||||
#--------------
|
||||
# PCIe RefClock IBUFDS location
|
||||
#
|
||||
# Location of the IBUFDS cell that receives the PCIe reference clock. This is
|
||||
# equivalent of constraining the location of each of the two clock pins (P and N)
|
||||
#
|
||||
|
||||
set_property LOC IBUFDS_GTE2_X0Y3 [get_cells PcieRefClkIBufds]
|
||||
|
||||
#--------------
|
||||
# PCIe Transceiver locations
|
||||
#
|
||||
# These constraints select the transceivers to be used, which also dictates the pinout
|
||||
# for the transmit and receive differential pairs.
|
||||
#
|
||||
# To find a relation between GTXE2 channel, pins and MGT_Banks, see pages 390-394 of the
|
||||
# following document:
|
||||
#
|
||||
# http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
|
||||
|
||||
# PCIe Lane 0 (GTXE2_CHANNEL_X0Y7 uses pins AR2, AR1, AP8 and AP7)
|
||||
set_property LOC GTXE2_CHANNEL_X0Y7 [get_cells {PcieIp/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
|
||||
# PCIe Lane 1 (GTXE2_CHANNEL_X0Y6 uses pins AT4, AT3, AR6 and AR5)
|
||||
set_property LOC GTXE2_CHANNEL_X0Y6 [get_cells {PcieIp/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
|
||||
# PCIe Lane 2 (GTXE2_CHANNEL_X0Y5 uses pins AV8, AV7, AU4 and AU3)
|
||||
set_property LOC GTXE2_CHANNEL_X0Y5 [get_cells {PcieIp/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
|
||||
# PCIe Lane 3 (GTXE2_CHANNEL_X0Y4 uses pins AY2, AY1, AX8 and AX7)
|
||||
set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells {PcieIp/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
|
||||
|
||||
set_property PACKAGE_PIN B5 [get_ports {PCIE_RX_N[0]}]
|
||||
set_property PACKAGE_PIN B6 [get_ports {PCIE_RX_P[0]}]
|
||||
set_property PACKAGE_PIN A3 [get_ports {PCIE_TX_N[0]}]
|
||||
set_property PACKAGE_PIN A4 [get_ports {PCIE_TX_P[0]}]
|
||||
set_property PACKAGE_PIN C3 [get_ports {PCIE_RX_N[1]}]
|
||||
set_property PACKAGE_PIN C4 [get_ports {PCIE_RX_P[1]}]
|
||||
set_property PACKAGE_PIN B1 [get_ports {PCIE_TX_N[1]}]
|
||||
set_property PACKAGE_PIN B2 [get_ports {PCIE_TX_P[1]}]
|
||||
set_property PACKAGE_PIN E3 [get_ports {PCIE_RX_N[2]}]
|
||||
set_property PACKAGE_PIN E4 [get_ports {PCIE_RX_P[2]}]
|
||||
set_property PACKAGE_PIN D1 [get_ports {PCIE_TX_N[2]}]
|
||||
set_property PACKAGE_PIN D2 [get_ports {PCIE_TX_P[2]}]
|
||||
set_property PACKAGE_PIN G3 [get_ports {PCIE_RX_N[3]}]
|
||||
set_property PACKAGE_PIN G4 [get_ports {PCIE_RX_P[3]}]
|
||||
set_property PACKAGE_PIN F1 [get_ports {PCIE_TX_N[3]}]
|
||||
set_property PACKAGE_PIN F2 [get_ports {PCIE_TX_P[3]}]
|
||||
|
||||
|
||||
#--------------
|
||||
# PCI Express Block location.
|
||||
# This constraint selects the PCI Express Block to be used.
|
||||
#
|
||||
|
||||
set_property LOC PCIE_X0Y0 [get_cells {PcieIp/inst/inst/pcie_top_i/pcie_7x_i/pcie_block_i}]
|
||||
|
||||
#
|
||||
# BlockRAM placement
|
||||
#
|
||||
set_property LOC RAMB36_X5Y35 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y36 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y35 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y34 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y33 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y32 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y31 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
set_property LOC RAMB36_X4Y30 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
|
||||
12
fpga/usrp3/top/b300/constraints/b310_dram.xdc
Normal file
12
fpga/usrp3/top/b300/constraints/b310_dram.xdc
Normal file
@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
create_generated_clock -name ddr3_axi_clk [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT"}]
|
||||
create_generated_clock -name ddr3_axi_clk_x2 [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0"}]
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks mmcm_ps_clk_bufg_in]
|
||||
set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks ddr3_axi_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks ddr3_axi_clk_x2]
|
||||
820
fpga/usrp3/top/b300/constraints/timing.xdc
Normal file
820
fpga/usrp3/top/b300/constraints/timing.xdc
Normal file
@ -0,0 +1,820 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
# *******************************************************************************
|
||||
# Clocking
|
||||
|
||||
create_clock -period 10.000 -name pcie_clk [get_ports PCIE_REF_CLK_P]
|
||||
|
||||
create_clock -period 8.000 -name dev_clk [get_ports DEVCLK_P]
|
||||
|
||||
# Ref Clocks have max frequency of 125MHz
|
||||
create_clock -period 8.000 -name local_ref_clk [get_ports FPGA_REFCLK_P]
|
||||
create_clock -period 8.000 -name ext_ref_clk [get_ports EXT_REFCLK_P]
|
||||
|
||||
# Virtual clocks for constraining I/O
|
||||
create_clock -name async_in_clk -period 50.00
|
||||
create_clock -name async_out_clk -period 50.00
|
||||
|
||||
# dev_clk is related to ext_ref_clk, but through an LMK configured in pass through mode.
|
||||
# That delay has variation over process/temperature.
|
||||
# Specify the min and max delay here so that vivado times the clock crossings with this.
|
||||
# Typically seeing 0.62ns delay through the part
|
||||
# 3.2in ref_clk_buf --> ref_clk at fpga
|
||||
# 2.7in ref_clk_buf --> ref_clk at lmk
|
||||
# 1.4in lmk to dev_clk fpga
|
||||
# total additional delay = 2.7 + 1.4 - 3.2 = 0.9in * 1ns / 6in = 0.133ns)
|
||||
# Thus total typ delay seen by FPGA is 0.753ns or 0.75ns.
|
||||
# With min delay of 0.3ns below, this gives 0.45ns of margin on min side, thus a lmk with min delay of 0.17ns would start failing
|
||||
# Conversely we have max delay of 1.9ns, and thus have 1.15ns of margin on the high side. The lmk would need to slow down to 1.77ns to start failing.
|
||||
# The lmk varies over temperature by +-0.04ns, so temperature is not a large factor
|
||||
# It would be process that would break this. NI measured 0.5ns on one part and 0.65ns on another part. TI measured 0.8ns.
|
||||
# Measured: 0.65ns +- 0.15ns
|
||||
# Tollerate: 0.17ns to 1.77ns
|
||||
# Measured: 0.65ns/1.3 to 0.65ns*1.23
|
||||
# Tollerate: 0.65ns/3.82 to 0.65ns*2.72
|
||||
set lmk_min_delay 0.3
|
||||
set lmk_max_delay 1.9
|
||||
set_clock_latency -source -early [expr $lmk_min_delay] [get_clocks dev_clk]
|
||||
set_clock_latency -source -late [expr $lmk_max_delay] [get_clocks dev_clk]
|
||||
|
||||
|
||||
|
||||
create_clock -name txoutclk -period 10 [get_pins {b310_host_interface_i/b310_host_interfacex/TargetHostInterfacex/InchwormWrapperGen.PcieInchwormWrapper/InchwormNetlist/PcieIpWrapper/PcieIp/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK}]
|
||||
|
||||
# JESD
|
||||
|
||||
create_clock -period 8.000 -name jesd_ref_clk [get_ports JESD_CLK_P]
|
||||
|
||||
create_clock -period 8.0 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ b310_jesd204b*gt0_gtwizard_0_i*gtxe2_i*}]]
|
||||
create_clock -period 8.0 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLKFABRIC} -of_objects [get_cells -hierarchical -filter {NAME =~ b310_jesd204b*gt0_gtwizard_0_i*gtxe2_i*}]]
|
||||
create_clock -period 8.0 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLKFABRIC} -of_objects [get_cells -hierarchical -filter {NAME =~ b310_jesd204b*gt0_gtwizard_0_i*gtxe2_i*}]]
|
||||
create_clock -period 8.0 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ b310_jesd204b*gt0_gtwizard_0_i*gtxe2_i*}]]
|
||||
|
||||
set_false_path -to [get_cells -hierarchical -filter {NAME =~ b310_jesd204b*data_sync_reg1}]
|
||||
|
||||
|
||||
# Create clocks for the clock wizard outputs
|
||||
create_generated_clock -name radio_clk [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen_i/*/CLKOUT0"}]
|
||||
|
||||
create_generated_clock -name radio_clk_shifted [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen_i/*/CLKOUT3"}]
|
||||
# Shift to meet timing from ext_ref_clk capture of pps_in into this clock.
|
||||
# PPS_IN then transfers from this clock into the non shifted radio_clk.
|
||||
# This is due to the phase difference between ext_ref_clk and devclk through the LMK.
|
||||
set_property CLKOUT3_PHASE 45.000 [get_cells -hierarchical -filter {NAME =~ "*radio_clk_gen_i/*/plle2_adv_inst"}]
|
||||
# set PHASESHIFT_MODE to cause capture edge to be 360deg + 45 deg out, rather than even harder to meet just 45deg out.
|
||||
set_property PHASESHIFT_MODE LATENCY [get_cells -hierarchical -filter {NAME =~ "*radio_clk_gen_i/*/plle2_adv_inst"}]
|
||||
|
||||
create_generated_clock -name radio_clk_2x [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen_i/*/CLKOUT1"}]
|
||||
create_generated_clock -name bus_clk [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen_i/*/CLKOUT0"}]
|
||||
create_generated_clock -name clk_40mhz [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen_i/*/CLKOUT1"}]
|
||||
create_generated_clock -name ce_clk [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen_i/*/CLKOUT2"}]
|
||||
|
||||
create_generated_clock -name DmaClockSource [get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieMmcm/CLKOUT3"}]
|
||||
create_generated_clock -name clk_125mhz_x0y0 [get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieMmcm/CLKOUT0"}]
|
||||
create_generated_clock -name clk_250mhz_x0y0 [get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieMmcm/CLKOUT1"}]
|
||||
create_generated_clock -name clk_125mhz_mux_x0y0 \
|
||||
-source [get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieBufgctrl/I0"}] \
|
||||
-divide_by 1 \
|
||||
[get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieBufgctrl/O"}]
|
||||
create_generated_clock -name clk_250mhz_mux_x0y0 \
|
||||
-source [get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieBufgctrl/I1"}] \
|
||||
-divide_by 1 -add -master_clock [get_clocks -of [get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieBufgctrl/I1"}]] \
|
||||
[get_pins -hierarchical -filter {NAME =~ "*Pcie7SeriesBimClockGenx/PcieBufgctrl/O"}]
|
||||
|
||||
# Remove analysis over clock update logic.
|
||||
set_clock_groups -name pcieclkmux -physically_exclusive -group clk_125mhz_mux_x0y0 -group clk_250mhz_mux_x0y0
|
||||
|
||||
# PPS OUT
|
||||
# Trace delays below are from simulations. See "Multi Device Synchronization.docx" for theory of operation.
|
||||
|
||||
# Shift phase of PPS_OUT to be centered around window of when needed to meet PPS_IN timing into the FPGA.
|
||||
# PHASE must be multiple of 45 / 7
|
||||
set_property CLKOUT0_PHASE 218.57 [get_cells -hierarchical -filter {NAME =~ "*ref_clk_pll_inst/*/plle2_adv_inst"}]
|
||||
# force these into an IOB, as Vivado could also decide to fan out the IO to 4 IO cells
|
||||
set_property IOB TRUE [get_ports PPS_OUT*]
|
||||
# Tighten these up to timing results from FPGA build to be used below also for input timing.
|
||||
set min_tco 5.5
|
||||
set max_tco 6.7
|
||||
set_output_delay -clock local_ref_clk -max [expr 8 - $max_tco] [get_ports PPS_OUT*]
|
||||
set_output_delay -clock local_ref_clk -min [expr 0 - $min_tco] [get_ports PPS_OUT*]
|
||||
|
||||
# PPS IN
|
||||
set_property IOB TRUE [get_ports EXT_PPS_IN]
|
||||
# vivado auto insters zero delay buffer which has extra slop when clocking directly from a pin
|
||||
# Remove as we can't use a PLL on this as PLL can't be used with 10Mhz input
|
||||
set_property IOBDELAY "NONE" [get_cells EXT_PPS_IN_IBUF_inst]
|
||||
|
||||
# Each of these are + tcable, but cable length cancels out since clock and PPS both travel a cable length
|
||||
# Below simulated with 1.5ft cable
|
||||
# tadclk948min (-0.025) + trefclk_cable_min (3.998) + tadclk944_min (0.07) + adclk944_to_fpga_min (0.07) + ttrace_min(0.541) + balon delay (0.5)
|
||||
set clk_in_trace_min 5.154
|
||||
# additional amount to subtract from min when assuming 0ft cable and minimum capacitances
|
||||
set clk_in_0ft_correction_min -0.443
|
||||
# tadclk948max (0.025) + trefclk_cable_max (2.025) + tadclk944_max (0.13) + ttrace_max(0.15)
|
||||
set clk_in_trace_max 5.553
|
||||
# ttrace_min (0) + tpps_in_min (3.265) - tpps_in_min_correction_for_min_cap_on_diodes_passfet (1.026)
|
||||
set pps_in_trace_min 5.232
|
||||
# ttrace_max (0.15) + tpps_in_max (7.906) (only consider rising edge as that is when we do the clock cross of time)
|
||||
set pps_in_trace_max 8.056
|
||||
# min: 5.5 + 5.232 - 5.553 - 0.443 = 4.732
|
||||
set_input_delay -clock ext_ref_clk -min [expr $min_tco + $pps_in_trace_min + $clk_in_0ft_correction_min - $clk_in_trace_max] [get_ports EXT_PPS_IN]
|
||||
|
||||
# max: 6.7 + 8.056 - 5.145 = 9.611
|
||||
set_input_delay -clock ext_ref_clk -max [expr $max_tco + $pps_in_trace_max - $clk_in_trace_min] [get_ports EXT_PPS_IN]
|
||||
|
||||
# LMK SYNC out
|
||||
set lmk_hold_req 0.02
|
||||
set lmk_setup_req 0.02
|
||||
set sync_trace_min 0.119
|
||||
set sync_trace_max 1.087
|
||||
set extra_30p72_setup 24
|
||||
|
||||
# There are two paths
|
||||
# 10MHz ext ref: Timing is to ext_ref_clock (input of LMK) and sourced from ext_ref_clk in the FPGA
|
||||
# Reason for this is that radio_clk is a diferent frequency than ext_ref_clock (125Mhz vs 10/30.72Mhz)
|
||||
# LMK is synchronous to ext_ref_clock thus makes sense to drive it from that.
|
||||
# 10MHz is slow enough to meet timing
|
||||
# High freq ref (122.88MHz/125MHz). Timing is to ext_ref_clock (input of LMK) and sourced from radio_clk in the FPGA
|
||||
# Reason for this is that ext_ref_clock and radio_clk are the same frequency, thus related
|
||||
# We get better timing characteristics when driving this output from a PLL vs directly from IO pin to
|
||||
# meet the higher 125MHz timing to sync in of the LMK
|
||||
set_output_delay -clock ext_ref_clk -min [expr $sync_trace_min - $lmk_hold_req] [get_ports LMK_SYNC]
|
||||
set_output_delay -clock ext_ref_clk -max [expr $sync_trace_max + $lmk_setup_req] [get_ports LMK_SYNC]
|
||||
# One more path for when a 30p72 clock, give extra setup. This path is never fasle pathed, above is for 30p72MHz case
|
||||
set_output_delay -add_delay -clock ext_ref_clk -max [expr $sync_trace_max + $lmk_setup_req - $extra_30p72_setup] [get_ports LMK_SYNC]
|
||||
# not guaranteed to meet timing to LMK on RevA, but here for testing with RevA
|
||||
set_output_delay -clock ext_ref_clk -min [expr $sync_trace_min - $lmk_hold_req] [get_ports LMK_SYNC_REVA]
|
||||
set_output_delay -clock ext_ref_clk -max [expr $sync_trace_max + $lmk_setup_req] [get_ports LMK_SYNC_REVA]
|
||||
set_output_delay -clock ext_ref_clk -max [expr $sync_trace_max + $lmk_setup_req] [get_ports LMK_SYNC_REVA]
|
||||
set_output_delay -add_delay -clock ext_ref_clk -max [expr $sync_trace_max + $lmk_setup_req - $extra_30p72_setup] [get_ports LMK_SYNC_REVA]
|
||||
|
||||
# False path the selection between having ext_ref_clk or radio_clk register drive LMK_SYNC
|
||||
set_false_path -from [get_pins b310_core_i/core_regsx/lmk_sync_clk_sel_reg/C] -to [get_ports LMK_SYNC_REVA]
|
||||
set_false_path -from [get_pins b310_core_i/core_regsx/lmk_sync_clk_sel_reg/C] -to [get_ports LMK_SYNC]
|
||||
|
||||
# False path from ext_ref_clock source to output. In this case clock is 30.72MHz max, so easier to meet
|
||||
# TODO: Don't false path this, but make Vivado analyze this path at 30.72Mhz
|
||||
# Tricky part is I can't seem to find a way to get Vivado to analyze from 125MHz radio clock to ext_ref_clk
|
||||
# as well as from 30.72MHz ext_ref_clk to ext_ref_clk
|
||||
# No way I know of yet to false path the 30.72Mhz path for the 125MHz case but not 30.72MHz case
|
||||
# So just false pathing it all together. Need to manually check timing of that port for now
|
||||
set_false_path -from [get_pins b310_core_i/b3xx_pps_sync_i/sync_brc_out_reg/C] -to [get_ports LMK_SYNC]
|
||||
set_false_path -from [get_pins b310_core_i/b3xx_pps_sync_i/sync_brc_out_reva_reg/C] -to [get_ports LMK_SYNC_REVA]
|
||||
|
||||
set BasePath b310_host_interface_i/b310_host_interfacex/CoreRegPortToCtrlPort/BaRegPortClockCrossingx/RequestHandshake
|
||||
## Start include, file HandshakeSLV_RSD.xml
|
||||
set HandshakeSlvRsdPath $BasePath
|
||||
set BasePath $BasePath/HBx
|
||||
## Start add from file HandshakeBaseRSD.xdc
|
||||
# ---------------------------------------------------------------------------------------
|
||||
# HandshakeBaseRSD
|
||||
# ---------------------------------------------------------------------------------------
|
||||
# Save incoming path
|
||||
set HandshakeBaseRsdPath $BasePath
|
||||
|
||||
# Data
|
||||
set TNM_HS_iData [get_cells "$BasePath/BlkIn.iStoredDatax/*/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_oData [get_cells "$BasePath/*oDataFlopx/*/*" -filter {IS_SEQUENTIAL==true}]
|
||||
# Toggle
|
||||
set TNM_HS_iTog [get_cells "$BasePath/*iPushTogglex/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_oTog_ms [get_cells "$BasePath/*oPushToggle0_msx/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_oTog [get_cells "$BasePath/*oPushToggle1x/*" -filter {IS_SEQUENTIAL==true}]
|
||||
# Ready
|
||||
set TNM_HS_oRdy [get_cells "$BasePath/*oPushToggleToReadyx/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_iRdy_ms [get_cells "$BasePath/*iRdyPushToggle_msx/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_iRdy [get_cells "$BasePath/*iRdyPushTogglex/*" -filter {IS_SEQUENTIAL==true}]
|
||||
|
||||
# Find out the minimum period of the clocks related to the previous groups.
|
||||
set T_IClkMin [expr "min([join [get_property PERIOD [get_clocks -of $TNM_HS_iData]] ,])"]
|
||||
set T_OClkMin [expr "min([join [get_property PERIOD [get_clocks -of $TNM_HS_oData]] ,])"]
|
||||
|
||||
# The datapath clock crossings must be less than 2X the period of the destination clock.
|
||||
set_max_delay -from $TNM_HS_iData -to $TNM_HS_oData -datapath_only [expr 2 * $T_OClkMin - 0.5]
|
||||
|
||||
# Toggle
|
||||
set_false_path -from $TNM_HS_iTog -to $TNM_HS_oTog_ms
|
||||
set_max_delay -from $TNM_HS_oTog_ms -to $TNM_HS_oTog -datapath_only [expr 0.5 * $T_OClkMin]
|
||||
|
||||
# The return ready path isn't very important here.
|
||||
set_false_path -from $TNM_HS_oRdy -to $TNM_HS_iRdy_ms
|
||||
set_max_delay -from $TNM_HS_iRdy_ms -to $TNM_HS_iRdy -datapath_only [expr 0.5 * $T_IClkMin]
|
||||
|
||||
|
||||
set BasePath $HandshakeSlvRsdPath
|
||||
|
||||
|
||||
set BasePath b310_host_interface_i/b310_host_interfacex/CoreRegPortToCtrlPort/BaRegPortClockCrossingx/ResponseHandshake
|
||||
## Start include, file HandshakeSLV_RSD.xml
|
||||
set HandshakeSlvRsdPath $BasePath
|
||||
set BasePath $BasePath/HBx
|
||||
## Start add from file HandshakeBaseRSD.xdc
|
||||
# ---------------------------------------------------------------------------------------
|
||||
# HandshakeBaseRSD
|
||||
# ---------------------------------------------------------------------------------------
|
||||
# Save incoming path
|
||||
set HandshakeBaseRsdPath $BasePath
|
||||
|
||||
# Data
|
||||
set TNM_HS_iData [get_cells "$BasePath/BlkIn.iStoredDatax/*/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_oData [get_cells "$BasePath/*oDataFlopx/*/*" -filter {IS_SEQUENTIAL==true}]
|
||||
# Toggle
|
||||
set TNM_HS_iTog [get_cells "$BasePath/*iPushTogglex/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_oTog_ms [get_cells "$BasePath/*oPushToggle0_msx/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_oTog [get_cells "$BasePath/*oPushToggle1x/*" -filter {IS_SEQUENTIAL==true}]
|
||||
# Ready
|
||||
set TNM_HS_oRdy [get_cells "$BasePath/*oPushToggleToReadyx/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_iRdy_ms [get_cells "$BasePath/*iRdyPushToggle_msx/*" -filter {IS_SEQUENTIAL==true}]
|
||||
set TNM_HS_iRdy [get_cells "$BasePath/*iRdyPushTogglex/*" -filter {IS_SEQUENTIAL==true}]
|
||||
|
||||
# Find out the minimum period of the clocks related to the previous groups.
|
||||
set T_IClkMin [expr "min([join [get_property PERIOD [get_clocks -of $TNM_HS_iData]] ,])"]
|
||||
set T_OClkMin [expr "min([join [get_property PERIOD [get_clocks -of $TNM_HS_oData]] ,])"]
|
||||
|
||||
# The datapath clock crossings must be less than 2X the period of the destination clock.
|
||||
set_max_delay -from $TNM_HS_iData -to $TNM_HS_oData -datapath_only [expr 2 * $T_OClkMin - 0.5]
|
||||
|
||||
# Toggle
|
||||
set_false_path -from $TNM_HS_iTog -to $TNM_HS_oTog_ms
|
||||
set_max_delay -from $TNM_HS_oTog_ms -to $TNM_HS_oTog -datapath_only [expr 0.5 * $T_OClkMin]
|
||||
|
||||
# The return ready path isn't very important here.
|
||||
set_false_path -from $TNM_HS_oRdy -to $TNM_HS_iRdy_ms
|
||||
set_max_delay -from $TNM_HS_iRdy_ms -to $TNM_HS_iRdy -datapath_only [expr 0.5 * $T_IClkMin]
|
||||
|
||||
#*******************************************************************************
|
||||
## Asynchronous clock groups
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk] -group [get_clocks clk_40mhz]
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk] -group [get_clocks bus_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk_2x] -group [get_clocks bus_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk_2x] -group [get_clocks clk_40mhz]
|
||||
set_clock_groups -asynchronous -group [get_clocks ce_clk] -group [get_clocks clk_40mhz]
|
||||
set_clock_groups -asynchronous -group [get_clocks ce_clk] -group [get_clocks radio_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk] -group [get_clocks txoutclk]
|
||||
set_clock_groups -asynchronous -group [get_clocks txoutclk] -group [get_clocks clk_40mhz]
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_40mhz] -group [get_clocks clk_125mhz_x0y0]
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_40mhz] -group [get_clocks clk_250mhz_x0y0]
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_40mhz] -group [get_clocks DmaClockSource]
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk] -group [get_clocks DmaClockSource]
|
||||
set_clock_groups -asynchronous -group [get_clocks radio_clk_2x] -group [get_clocks DmaClockSource]
|
||||
set_clock_groups -asynchronous -group [get_clocks jesd_ref_clk -include_generated_clocks]
|
||||
set_clock_groups -asynchronous -group [get_clocks async_in_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks async_out_clk]
|
||||
|
||||
#*******************************************************************************
|
||||
## CPLD Interface Clocks and Timing
|
||||
|
||||
# CPLD to FPGA RX Clock: 80 MHz (from CPLD_TX_CLK port)
|
||||
create_clock -name cpld_to_fpga_clk -period 12.5 [get_ports CPLD_TX_CLK]
|
||||
|
||||
# FPGA to CPLD TX Clock (from CPLD_RX_CLK port) - generated from bus_clk
|
||||
create_generated_clock -name fpga_to_cpld_clk \
|
||||
-source [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen_i*CLKOUT1"}] \
|
||||
-divide_by 1 \
|
||||
[get_ports CPLD_RX_CLK]
|
||||
|
||||
set CpldToFpgaClkPeriod [get_property period [get_clocks cpld_to_fpga_clk]]
|
||||
set BusClkPeriod [get_property period [get_clocks bus_clk]]
|
||||
|
||||
# Set input/output delays for CPLD interface signals
|
||||
#
|
||||
# FPGA-to-CPLD OUTPUT TIMING CALCULATION:
|
||||
# =======================================
|
||||
# Board measurements: CPLD_RX_CLK=0.1483ns, CPLD_RX_DATA=0.2133ns (longest), 0.1466ns (shortest)
|
||||
# Clock-to-data skew: longest=0.065ns (data arrives 65ps after clock), shortest=-0.0017ns (data arrives 1.7ps before clock)
|
||||
#
|
||||
# Available time per half-cycle: BusClkPeriod/2 = 25ns/2 = 12.5ns
|
||||
# CPLD setup requirement: ~2.0ns (typical for CPLD)
|
||||
# Board delay + skew worst case: 0.2133ns + safety margin
|
||||
# FPGA internal routing margin: ~1.0ns
|
||||
# Total external budget: 2.0 + 0.22 + 1.0 = 3.22ns
|
||||
# Conservative constraint: 5.0ns (provides 1.8ns extra margin)
|
||||
#
|
||||
# Tightened timing margins based on successful timing closure
|
||||
|
||||
set FpgaToCpldTcoMax 5.0
|
||||
set FpgaToCpldTcoMin -1.0
|
||||
|
||||
set FpgaToCpldMaxOutputDelay [expr $BusClkPeriod / 2 - $FpgaToCpldTcoMax]
|
||||
set FpgaToCpldMinOutputDelay [expr 0 - $FpgaToCpldTcoMin]
|
||||
|
||||
set_output_delay -clock [get_clocks fpga_to_cpld_clk] -max $FpgaToCpldMaxOutputDelay [get_ports {CPLD_RX_DATA[*]}]
|
||||
set_output_delay -clock [get_clocks fpga_to_cpld_clk] -min $FpgaToCpldMinOutputDelay [get_ports {CPLD_RX_DATA[*]}]
|
||||
set_output_delay -clock [get_clocks fpga_to_cpld_clk] -max $FpgaToCpldMaxOutputDelay [get_ports CPLD_RX_CLKEN]
|
||||
set_output_delay -clock [get_clocks fpga_to_cpld_clk] -min $FpgaToCpldMinOutputDelay [get_ports CPLD_RX_CLKEN]
|
||||
|
||||
# Additional constraints for CPLD_RX_DATA bus trace length extremes
|
||||
# Longest trace (1.28 in = 0.2133ns): Provides worst-case delay from FPGA to CPLD
|
||||
# Shortest trace (0.88 in = 0.1466ns): Provides best-case delay from FPGA to CPLD
|
||||
# Clock trace (0.89 in = 0.1483ns): Reference for skew calculations
|
||||
|
||||
# Make sure the clock to the CPLD is in the IOB
|
||||
# Board measurement: CPLD_RX_CLK trace = 0.1483ns
|
||||
# Relaxed constraint for better timing closure
|
||||
set_max_delay -datapath_only -from [get_pins {*cpld_interface_i/*/CpldClockFlop/C}] -to [get_ports {CPLD_RX_CLK}] 3.0
|
||||
|
||||
# The following numbers are the calculated FPGA available setup and hold and
|
||||
# include the CPLD Tco numbers plus any board skew numbers.
|
||||
#
|
||||
# CPLD-to-FPGA INPUT TIMING CALCULATION:
|
||||
# ======================================
|
||||
# Updated board measurements: CPLD_TX_CLK=0.155ns, CPLD_TX_DATA=0.1666ns (longest), 0.1166ns (shortest), CPLD_TX_CLKEN=0.1433ns
|
||||
# Clock-to-data skew: longest=0.0116ns (data arrives 11.6ps after clock), shortest=-0.0384ns (data arrives 38.4ps before clock)
|
||||
# Clock-to-clken skew = -0.0117ns (clken arrives 11.7ps before clock)
|
||||
#
|
||||
# Available time per half-cycle: CpldToFpgaClkPeriod/2 = 12.5ns/2 = 6.25ns
|
||||
# CPLD internal Tco (clock-to-output): ~2.0ns typical, ~2.5ns max
|
||||
# Board trace delays: 0.155ns (clock) vs 0.1166-0.1666ns (data)
|
||||
# Board skew: 0.0116ns worst case (data after clock)
|
||||
# Power supply noise margin: ~0.2ns
|
||||
# Temperature variation: ~0.1ns
|
||||
# Manufacturing tolerance: ~0.1ns
|
||||
# Safety margin: ~0.1ns
|
||||
# Total budget: 2.5 + 0.17 + 0.01 + 0.2 + 0.1 + 0.1 + 0.1 = 3.18ns
|
||||
# Conservative constraint: 3.0ns
|
||||
# Remaining time for FPGA: 6.25 - 3.0 = 3.25ns
|
||||
# Tightened timing margins based on successful timing closure
|
||||
|
||||
set CpldDataAtFpgaSetupTime 3.0
|
||||
set CpldDataAtFpgaHoldTime 3.0
|
||||
|
||||
set CpldToFpgaMaxOutputDelay [expr $CpldToFpgaClkPeriod / 2 - $CpldDataAtFpgaSetupTime]
|
||||
set CpldToFpgaMinOutputDelay [expr $CpldDataAtFpgaHoldTime - $CpldToFpgaClkPeriod / 2]
|
||||
|
||||
set_input_delay -clock_fall -clock [get_clocks cpld_to_fpga_clk] -max $CpldToFpgaMaxOutputDelay [get_ports {CPLD_TX_DATA[*] CPLD_TX_CLKEN}]
|
||||
set_input_delay -clock_fall -clock [get_clocks cpld_to_fpga_clk] -min $CpldToFpgaMinOutputDelay [get_ports {CPLD_TX_DATA[*] CPLD_TX_CLKEN}]
|
||||
|
||||
# Additional constraints for data bus trace length extremes
|
||||
# Updated board measurements: CPLD_TX_DATA longest trace (1.00 in = 0.1666ns), shortest trace (0.70 in = 0.1166ns)
|
||||
# This ensures timing closure across all data bit trace length variations
|
||||
|
||||
# CPLD Reset Output
|
||||
# Updated board measurement: CPLD_EXT_RST trace = 0.215ns
|
||||
# Tightened constraint based on actual board measurement and successful timing closure
|
||||
set_max_delay -datapath_only -from [all_registers -edge_triggered] -to [get_ports {CPLD_EXT_RST_R_N}] 12
|
||||
|
||||
# CPLD oscillator enable - static control signal
|
||||
set_false_path -to [get_ports CPLD_OSC_EN]
|
||||
|
||||
# ---------------------------------
|
||||
# Clock Domain Crossings Exceptions
|
||||
# ---------------------------------
|
||||
|
||||
#### CPLD Exceptions ####
|
||||
|
||||
# Constrain the asynchronous rResetCpld propagation delay to less than one cpld_to_fpga_clk cycle
|
||||
# Software would then be able to assert/de-assert the rResetCpld with no timing requirement in
|
||||
# between the assertion/de-assertion of this reset signal.
|
||||
# Note that rResetCpld is generated off the bus_clk and is received by the CPLD code
|
||||
# on both the cpld_to_fpga_clk and bus_clk domains. We only want to place a set_max_delay
|
||||
# constraint on this signal to registers that are clocked off the cpld_to_fpga_clk, so that we
|
||||
# do not override and prevent the tools from analyzing the bus_clk period constraint on these paths
|
||||
# Tightened constraint based on successful timing closure
|
||||
|
||||
set_max_delay -from [get_cells {*cpld_interface_i/*/rResetCpldInt*} -filter {IS_SEQUENTIAL==true}] \
|
||||
-to [all_registers -clock cpld_to_fpga_clk] \
|
||||
-datapath_only 20.0;
|
||||
|
||||
# cSerialData is shifted in from the CPLD into the FPGA using the CpldToFpgaClk
|
||||
# The CpldToFpgaClk is not continuous so a double-sync, as opposed to a handshake,
|
||||
# was used to cross the cSerialData from the CpldToFpgaClk clock domain to the
|
||||
# reliable clock domain. SW waits on cCpldDataValid to assert before reading the data.
|
||||
# cCpldDataValid gets double-synced to the reliable clock domain before being available
|
||||
# for SW to read. We place a 20 ns (less than one reliableClk cycle) on the data paths
|
||||
# to ensure that the code sampling the data on the reliable clock domain is sampling
|
||||
# non-metastable data.
|
||||
|
||||
set_max_delay -from [get_cells {*cpld_interface_i/*/cSerialData*} -filter {IS_SEQUENTIAL==true}] \
|
||||
-to [get_pins {*cpld_interface_i/*/SerialDataFlops/*/D}] \
|
||||
-datapath_only 20.0;
|
||||
|
||||
# Double-Sync crossing (cpld_to_fpga_clk --> bus_clk)
|
||||
# A strict requirement is not needed on these double-sync flops, but constraining
|
||||
# them to 20 ns for reasonable timing closure
|
||||
|
||||
set_max_delay -from [get_cells {*cpld_interface_i/*/cCpldDataValid*} -filter {IS_SEQUENTIAL==true}] \
|
||||
-to [get_pins {*cpld_interface_i/*/DoubleSyncDataValid/*/oSig_msx/*/D}] \
|
||||
-datapath_only 20.0;
|
||||
|
||||
set_max_delay -from [get_cells {*cpld_interface_i/*/cCpldHoldoff*} -filter {IS_SEQUENTIAL==true}] \
|
||||
-to [get_pins {*cpld_interface_i/*/DoubleSyncHoldoff/*/oSig_msx/*/D}] \
|
||||
-datapath_only 20.0;
|
||||
|
||||
set_max_delay -from [get_cells {*cpld_interface_i/*/cCpldInitialized*} -filter {IS_SEQUENTIAL==true}] \
|
||||
-to [get_pins {*cpld_interface_i/*/DoubleSyncInitialized/*/oSig_msx/*/D}] \
|
||||
-datapath_only 20.0;
|
||||
|
||||
set_max_delay -from [get_cells {*cpld_interface_i/*/cCpldReady*} -filter {IS_SEQUENTIAL==true}] \
|
||||
-to [get_pins {*cpld_interface_i/*/DoubleSyncReady/*/oSig_msx/*/D}] \
|
||||
-datapath_only 20.0;
|
||||
|
||||
# Mark CPLD clocks as asynchronous to all system clocks
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks bus_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks radio_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks radio_clk_2x]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks ce_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks clk_40mhz]
|
||||
# Enable PCIe clock relationships for proper timing analysis
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks DmaClockSource]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks clk_125mhz_x0y0]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks clk_250mhz_x0y0]
|
||||
set_clock_groups -asynchronous -group [get_clocks cpld_to_fpga_clk] -group [get_clocks jesd_ref_clk]
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks radio_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks radio_clk_2x]
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks ce_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks clk_40mhz]
|
||||
# Enable PCIe clock relationships for proper timing analysis
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks DmaClockSource]
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks clk_125mhz_x0y0]
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks clk_250mhz_x0y0]
|
||||
set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks jesd_ref_clk]
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Authentication chip interface timing
|
||||
|
||||
# We are using a single wire interface to the authentication chip which is a asynchronous interface.
|
||||
# Max delay of 15 ns is a conservative number as minimum time when "AUTH_SDA" signal can change it's state
|
||||
# is 15 us.
|
||||
set_max_delay -datapath_only -from [all_registers -edge_triggered] -to [get_ports AUTH_SDA] 15.000;
|
||||
set_max_delay -datapath_only -from [get_ports AUTH_SDA] -to [all_registers -edge_triggered] 15.000;
|
||||
|
||||
|
||||
# #*******************************************************************************
|
||||
# ## ADRV9032 SPI Interface
|
||||
|
||||
set adrv_spi_clk_register [get_pins {b310_core_i/ctrlport_spi_adrv_i/axis_spi_i/sclk_reg/Q}]
|
||||
|
||||
create_generated_clock -source [get_clocks radio_clk] \
|
||||
-name adrv_spi_clk $adrv_spi_clk_register \
|
||||
-divide_by 30
|
||||
|
||||
create_generated_clock \
|
||||
-source $adrv_spi_clk_register \
|
||||
-name adrv_spi_clk_out [get_ports {ADRV_SPI_CLK}]
|
||||
|
||||
# DIO trace length is 2138.37 nils, which is roughly 0.36 ns. The main source for propagation delay
|
||||
# in this trace comes from filtering circuitry on the ADRV side slowing down rise times. The measured
|
||||
# delay is ~32ns. The constraint below is a conservative number to ensure timing closure.
|
||||
set adrv_dio_max_trace_delay 75.0
|
||||
set adrv_dio_min_trace_delay 0.0
|
||||
# DO and CS has similar considerations as DIO, with both having a measured delay of ~45ns.
|
||||
set adrv_do_max_trace_delay 75.0
|
||||
set adrv_do_min_trace_delay 0.0
|
||||
set adrv_cs_max_trace_delay 75.0
|
||||
set adrv_cs_min_trace_delay 0.0
|
||||
# And yet again, we conservatively constraint the delay of the SPI clock, measured at ~25ns.
|
||||
set adrv_clk_max_trace_delay 50.0
|
||||
set adrv_clk_min_trace_delay 0.0
|
||||
|
||||
# Values from the ADRV9032 datasheet, in ns
|
||||
set adrv_spi_setup 4.0
|
||||
set adrv_spi_hold 0.0
|
||||
set adrv_spi_max_tco 3.5
|
||||
set adrv_spi_min_tco 0.0
|
||||
|
||||
# ----------------------------------------
|
||||
# -- Constraint for ADRV SPI CS and SDIO --
|
||||
# ----------------------------------------
|
||||
|
||||
set_output_delay -clock adrv_spi_clk_out \
|
||||
-max [expr {$adrv_spi_setup + $adrv_cs_max_trace_delay - $adrv_clk_min_trace_delay}] \
|
||||
[get_ports {ADRV_SPI_EN_N}]
|
||||
set_output_delay -clock adrv_spi_clk_out \
|
||||
-min [expr {0 - $adrv_clk_max_trace_delay - $adrv_spi_hold + $adrv_cs_min_trace_delay }] \
|
||||
[get_ports {ADRV_SPI_EN_N}]
|
||||
|
||||
set_output_delay -clock adrv_spi_clk_out \
|
||||
-max [expr {$adrv_spi_setup + $adrv_dio_max_trace_delay - $adrv_clk_min_trace_delay}] \
|
||||
[get_ports {ADRV_SPI_DIO}]
|
||||
set_output_delay -clock adrv_spi_clk_out \
|
||||
-min [expr {0 - $adrv_clk_max_trace_delay - $adrv_spi_hold + $adrv_dio_min_trace_delay }] \
|
||||
[get_ports {ADRV_SPI_DIO}]
|
||||
|
||||
# ----------------------------------------
|
||||
# -- Multi-cycle path for ADRVSPI EN_N and SDIO --
|
||||
# ----------------------------------------
|
||||
# Both the EN_N and SDIO timing are defined in reference to the falling edge of SCLK,
|
||||
# so we can merge the analysis (EN_N is driven half a period before the first rising edge of SCLK).
|
||||
#
|
||||
# edge # 1 2 3 14 15 16 17 29 30 31 32
|
||||
# radio_clk __/--\__/--\__/--\_..._/--\__/--\__/--\__/--\..._/--\__/--\__/--\__/
|
||||
# ADRV_SPI_CLK __/----------------...-------\_______________..._______/------------
|
||||
# | launch edge
|
||||
# | | | ... | | |
|
||||
# 0 1 2 ... 14 15* 16
|
||||
# Edge used for
|
||||
# setup analysis N = 15
|
||||
# | | | | | | | ... | |
|
||||
# 29 28 27 ... 16 15 14 13 ... 1 0
|
||||
# (Setup -1) edge, in case
|
||||
# of no hold multi-cycle path
|
||||
# |
|
||||
# \____ Edge used for hold = 29
|
||||
#
|
||||
set_multicycle_path -setup -start -to [get_ports {ADRV_SPI_EN_N ADRV_SPI_DIO}] 15
|
||||
set_multicycle_path -hold -start -to [get_ports {ADRV_SPI_EN_N ADRV_SPI_DIO}] 29
|
||||
|
||||
# ----------------------------------------
|
||||
# -- Constraint for ADRV SPI SDO --
|
||||
set_input_delay -clock adrv_spi_clk_out -clock_fall \
|
||||
-max [expr {$adrv_clk_max_trace_delay + $adrv_spi_max_tco + $adrv_do_max_trace_delay}] \
|
||||
[get_ports {ADRV_SPI_DO}]
|
||||
|
||||
set_input_delay -clock adrv_spi_clk_out -clock_fall \
|
||||
-min [expr {$adrv_clk_min_trace_delay + $adrv_spi_min_tco + $adrv_do_min_trace_delay}] \
|
||||
[get_ports {ADRV_SPI_DO}]
|
||||
|
||||
# -- Multi-cycle path for ADRV SPI SDO --
|
||||
# SDO is launched on the falling edge of SCLK and captured on the rising edge,
|
||||
# so we can use the same multi-cycle path analysis as the EN_N and SDIO signals.
|
||||
set_multicycle_path -setup -end -from [get_ports {ADRV_SPI_DO}] 15
|
||||
set_multicycle_path -hold -end -from [get_ports {ADRV_SPI_DO}] 29
|
||||
|
||||
#*******************************************************************************
|
||||
## Clocking SPI Interface
|
||||
|
||||
# This interface interacts with the LMK05318 and LMK04832 clock chips, as well as the AD5623 DAC.
|
||||
# The DAC is placed the furthest away from the FPGA, at around 2.7 inches of trace length,
|
||||
# we will use conservative numbers that far exceed its trace delay to ensure timing closure
|
||||
# for all devices on this interface.
|
||||
|
||||
set clocking_output_max_trace_delay 50.0
|
||||
set clocking_output_min_trace_delay 0.0
|
||||
set clocking_miso_max_trace_delay 50.0
|
||||
set clocking_miso_min_trace_delay 0.0
|
||||
set clocking_sclk_max_trace_delay 50.0
|
||||
set clocking_sclk_min_trace_delay 0.0
|
||||
|
||||
# Values from datasheets, in ns
|
||||
# Setup requirements for AD5623 = 13ns, LMK05318 = 10ns, LMK04832 = 20ns
|
||||
set clock_spi_setup 20.0
|
||||
# Hold requirements for AD5623 = 5ns, LMK05318 = 10ns, LMK04832 = 10ns. Using 0 ns.
|
||||
set clock_spi_hold 0.0
|
||||
# Tco specifications LMK05318 = 20ns, LMK04832 = 60ns. AD5623 has no read capability.
|
||||
set clock_spi_max_tco 60.0
|
||||
set clock_spi_min_tco 0.0
|
||||
|
||||
set clocking_sclk_register [get_pins {b310_core_i/clocking_spi_engine/sclk_reg_reg/Q}]
|
||||
|
||||
# SPI divider uses default value of 30.
|
||||
create_generated_clock -source [get_clocks bus_clk] \
|
||||
-name clocking_spi_clk $clocking_sclk_register \
|
||||
-divide_by 30
|
||||
|
||||
create_generated_clock \
|
||||
-source $clocking_sclk_register \
|
||||
-name clocking_spi_clk_out [get_ports {LMK32_SCLK LMK053_SCLK DAC_SCLK}]
|
||||
|
||||
|
||||
# ---------------------------------------------
|
||||
# -- Constraint for Clocking SPI CS and MOSI --
|
||||
# ---------------------------------------------
|
||||
|
||||
set CLOCKING_SPI_OUTPUTS [get_ports {LMK32_CS_N LMK32_MOSI LMK053_CS_N LMK053_MOSI DAC_CS_N DAC_MOSI}]
|
||||
|
||||
set_output_delay -clock clocking_spi_clk_out \
|
||||
-max [expr {$clock_spi_setup + $clocking_output_max_trace_delay - $clocking_sclk_min_trace_delay}] \
|
||||
$CLOCKING_SPI_OUTPUTS
|
||||
set_output_delay -clock clocking_spi_clk_out \
|
||||
-min [expr {0 - $clocking_sclk_max_trace_delay - $clock_spi_hold + $clocking_output_min_trace_delay }] \
|
||||
$CLOCKING_SPI_OUTPUTS
|
||||
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# -- Multi-cycle path for Clocking SPI CS_N and MOSI (LMKs only) --
|
||||
# -----------------------------------------------------------------
|
||||
# Both the CS_N and MOSI timing are defined in reference to the falling edge of SCLK,
|
||||
# so we can merge the analysis (CS_N is driven half a period before the first rising edge of SCLK).
|
||||
#
|
||||
# edge # 1 2 3 14 15 16 17 29 30 31 32
|
||||
# bus_clk __/--\__/--\__/--\_..._/--\__/--\__/--\__/--\..._/--\__/--\__/--\__/
|
||||
# SCLK __/----------------...-------\_______________..._______/------------
|
||||
# | launch edge
|
||||
# | | | ... | | |
|
||||
# 0 1 2 ... 14 15* 16
|
||||
# Edge used for
|
||||
# setup analysis N = 15
|
||||
# | | | | | | | ... | |
|
||||
# 29 28 27 ... 16 15 14 13 ... 1 0
|
||||
# (Setup -1) edge, in case
|
||||
# of no hold multi-cycle path
|
||||
# |
|
||||
# \____ Edge used for hold = 29
|
||||
#
|
||||
# For the DAC MOSI, we will use the same multi-cycle path analysis as the LMKs, even though the DAC is
|
||||
# launched on the rising edge of SCLK. This is because the DAC MOSI is captured on the falling edge of SCLK,
|
||||
# so the same analysis applies, just with the edges reversed.
|
||||
set_multicycle_path -setup -start -to $CLOCKING_SPI_OUTPUTS 15
|
||||
set_multicycle_path -hold -start -to $CLOCKING_SPI_OUTPUTS 29
|
||||
|
||||
# ----------------------------------------
|
||||
# -- Constraint for Clocking SPI MISO --
|
||||
set_input_delay -clock clocking_spi_clk_out -clock_fall \
|
||||
-max [expr {$clocking_sclk_max_trace_delay + $clock_spi_max_tco + $clocking_miso_max_trace_delay}] \
|
||||
[get_ports {LMK053_MISO LMK32_MISO}]
|
||||
|
||||
set_input_delay -clock clocking_spi_clk_out -clock_fall \
|
||||
-min [expr {$clocking_sclk_min_trace_delay + $clock_spi_min_tco + $clocking_miso_min_trace_delay}] \
|
||||
[get_ports {LMK053_MISO LMK32_MISO}]
|
||||
|
||||
# -- Multi-cycle path for Clocking SPI MISO --
|
||||
# MISO is launched on the falling edge of SCLK and captured on the rising edge,
|
||||
# so we can use the same multi-cycle path analysis as the CS_N and MOSI signals.
|
||||
set_multicycle_path -setup -end -from [get_ports {LMK053_MISO LMK32_MISO}] 15
|
||||
set_multicycle_path -hold -end -from [get_ports {LMK053_MISO LMK32_MISO}] 29
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Asynchronous inputs/output signals
|
||||
# Consolidated groups used by the coarse timing model
|
||||
|
||||
# ADRV sideband signals
|
||||
set async_adrv_input_ports [get_ports {
|
||||
ADRV_GPIO[*]
|
||||
ADRV_GPINT[*]
|
||||
}]
|
||||
set async_adrv_output_ports [get_ports {
|
||||
ADRV_GPIO[*]
|
||||
ADRV_RESET_N
|
||||
ADRV_TEST_EN
|
||||
ADRV_TRXA_CTRL
|
||||
ADRV_TRXB_CTRL
|
||||
ADRV_TRXC_CTRL
|
||||
ADRV_TRXD_CTRL
|
||||
ADRV_TRXE_CTRL
|
||||
ADRV_TRXF_CTRL
|
||||
ADRV_TRXG_CTRL
|
||||
ADRV_TRXH_CTRL
|
||||
}]
|
||||
|
||||
# GPS / timing sideband signals
|
||||
set async_gps_input_ports [get_ports {
|
||||
GPS_PWR_FAULT_N
|
||||
GPS_PPS_OUT
|
||||
GPS_REF[*]
|
||||
NSYNC_STATUS[*]
|
||||
}]
|
||||
set async_gps_output_ports [get_ports {
|
||||
GPS_EXTINT
|
||||
GPS_REFSEL
|
||||
GPS_RESET_N
|
||||
NSYNC_GPIO0
|
||||
NSYNC_PDN
|
||||
}]
|
||||
|
||||
# Clocking SPI control/status
|
||||
set async_clocking_input_ports [get_ports {
|
||||
LMK32_STATUS
|
||||
}]
|
||||
set async_clocking_output_ports [get_ports {
|
||||
LMK32_RESET
|
||||
LMK32_VCXO_SEL_122M88
|
||||
DAC_CLR_N
|
||||
TCXO_EN_N
|
||||
REF_CLK_SEL
|
||||
}]
|
||||
|
||||
# Board control / status signals
|
||||
set async_board_input_ports [get_ports {
|
||||
PG_1V2
|
||||
TYPEC_PWR_NEGOTIATED
|
||||
VBUS_ALERT_N
|
||||
GT_25W_PWR_SRC
|
||||
}]
|
||||
set async_board_output_ports [get_ports {
|
||||
ANT_PWR_EN
|
||||
ENABLE_TXRX_TDR[*]
|
||||
PCIE_RESET_N_TO_CPLD
|
||||
RX_SW_CTRL[*]
|
||||
TBOLT_PD_CTRL_RESET
|
||||
TBOLT_RIDGE_RESET_N
|
||||
}]
|
||||
|
||||
# User-visible GPIO and LED sideband
|
||||
set async_panel_output_ports [get_ports {
|
||||
LED_RX_GRN[*]
|
||||
LED_TX_GRN[*]
|
||||
LED_TX_RED[*]
|
||||
LED_PWR_STS_BLUE
|
||||
LED_PWR_STS_ORANGE
|
||||
}]
|
||||
|
||||
# DDR3 Reset
|
||||
set async_ddr3_output_ports [get_ports {
|
||||
ddr3_reset_n
|
||||
}]
|
||||
|
||||
set async_panel_bidir_ports [get_ports {
|
||||
FP_GPIO[*]
|
||||
}]
|
||||
|
||||
# UART and I2C inputs treated as asynchronous by their
|
||||
# respective logic engines. Grouping them here creates
|
||||
# a very loose timing constraint to the first synchronizer
|
||||
# stage of the logic engine.
|
||||
set slow_input_ports [get_ports {
|
||||
GPS_UART_TOFPGA
|
||||
MISC_I2C_SCL
|
||||
MISC_I2C_SDA
|
||||
TBOLT_SCL
|
||||
TBOLT_SDA
|
||||
}]
|
||||
|
||||
set slow_output_ports [get_ports {
|
||||
GPS_UART_TOGPS
|
||||
MISC_I2C_SCL
|
||||
MISC_I2C_SDA
|
||||
TBOLT_SCL
|
||||
TBOLT_SDA
|
||||
}]
|
||||
|
||||
set async_input_ports [list $async_adrv_input_ports \
|
||||
$async_clocking_input_ports \
|
||||
$async_gps_input_ports \
|
||||
$async_board_input_ports \
|
||||
$slow_input_ports]
|
||||
set async_output_ports [list $async_adrv_output_ports \
|
||||
$async_board_output_ports \
|
||||
$async_clocking_output_ports \
|
||||
$async_gps_output_ports \
|
||||
$async_panel_output_ports\
|
||||
$async_ddr3_output_ports \
|
||||
$slow_output_ports]
|
||||
set async_bidir_ports [list $async_panel_bidir_ports]
|
||||
|
||||
set_input_delay -clock [get_clocks async_in_clk] 0.000 $async_input_ports
|
||||
set_max_delay -from $async_input_ports 50.000
|
||||
set_min_delay -from $async_input_ports 0.000
|
||||
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 $async_output_ports
|
||||
set_max_delay -to $async_output_ports 50.000
|
||||
set_min_delay -to $async_output_ports 0.000
|
||||
|
||||
set_input_delay -clock [get_clocks async_in_clk] 0.000 $async_bidir_ports
|
||||
set_max_delay -from $async_bidir_ports 50.000
|
||||
set_min_delay -from $async_bidir_ports 0.000
|
||||
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 $async_bidir_ports
|
||||
set_max_delay -to $async_bidir_ports 50.000
|
||||
set_min_delay -to $async_bidir_ports 0.000
|
||||
|
||||
|
||||
#*******************************************************************************
|
||||
## Asynchronous paths
|
||||
|
||||
set_false_path -from [get_ports PCIE_RESET_N]
|
||||
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]
|
||||
# Async reset
|
||||
set_max_delay -from [get_cells -hier -filter {NAME =~ *b310_host_interface_i/*/PcieIp/inst/inst/user_reset_out_reg*}] 20.0
|
||||
## Host IP
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */PcieBufgctrl/S0}]
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */PcieBufgctrl/S1}]
|
||||
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */DoubleSyncAsyncInBasex/oSig_msx/*/D}]
|
||||
|
||||
#*******************************************************************************
|
||||
# Define PLL location of critical PLLs
|
||||
|
||||
# both radio_clk and local_ref_clk PLL ideal placement is in the same clock region
|
||||
# Define which one gets it to provide for further consistency in compiles
|
||||
# Give priority to dev_clk since that is used for JESD IP
|
||||
create_pblock radio_clk_pblock
|
||||
resize_pblock radio_clk_pblock -add CLOCKREGION_X1Y0:CLOCKREGION_X1Y0
|
||||
add_cells_to_pblock radio_clk_pblock [get_cells [list radio_clk_gen_i/inst/plle2_adv_inst]]
|
||||
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets ref_clk_pll_inst/inst/clk_in1]
|
||||
|
||||
#*******************************************************************************
|
||||
## SYSREF/SYNC JESD Timing
|
||||
#
|
||||
# SYNC is async, SYSREF is tightly timed.
|
||||
|
||||
# The SYNC output (to ADC) for both DBs is governed by the JESD cores, which are solely
|
||||
# driven by radio_clk... but it is an asynchronous signal so we use the async_out_clk.
|
||||
set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports {ADRV_SYNCIN_*}]
|
||||
set_max_delay -to [get_ports {ADRV_SYNCIN_*}] 50.000
|
||||
set_min_delay -to [get_ports {ADRV_SYNCIN_*}] 0.000
|
||||
|
||||
# The SYNC input (from DAC) for both DBs is received by the radio_clk inside the JESD
|
||||
# cores... but again, it is asynchronous and therefore uses the async_in_clk.
|
||||
set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports {ADRV_SYNCOUT_*}]
|
||||
set_max_delay -from [get_ports {ADRV_SYNCOUT_*}] 50.000
|
||||
set_min_delay -from [get_ports {ADRV_SYNCOUT_*}] 0.000
|
||||
|
||||
# SYSREF Input timing
|
||||
# The LMK either launches this on the falling edge of DEVCLK + 282ps for distribution mode
|
||||
# and -200ps for non distribution mode.
|
||||
# This is essentially a min delay of 3.8ns and max delay of 4.283ns
|
||||
# To provide margin for LMK variation/jitter, we and add/subtract 0.7ns from these.
|
||||
# We subtract out lmk_min/max_delay because the tools assume that the min/delay max delay is not tracked
|
||||
# by the PLL, and thus the radio_clk it assumes can see this delay. The delay is static
|
||||
# thus the PLL can track it, so subtract that out here.
|
||||
set_property IOB TRUE [get_ports SYSREF_P]
|
||||
set_input_delay -clock dev_clk -min [expr 3.8 - 0.7 - $lmk_min_delay] [get_ports SYSREF_P]
|
||||
set_input_delay -clock dev_clk -max [expr 4.283 + 0.7 - $lmk_max_delay] [get_ports SYSREF_P]
|
||||
1903
fpga/usrp3/top/b300/core/b310_core.sv
Normal file
1903
fpga/usrp3/top/b300/core/b310_core.sv
Normal file
File diff suppressed because it is too large
Load Diff
255
fpga/usrp3/top/b300/core/basic_regs.sv
Normal file
255
fpga/usrp3/top/b300/core/basic_regs.sv
Normal file
@ -0,0 +1,255 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: basic_regs
|
||||
//
|
||||
// Description:
|
||||
// Basic Registers to inform software about version and capabilities.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module basic_regs #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
ctrlport_if.slave s_ctrlport
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
`include "../regmap/basic_regs_regmap_utils.vh"
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//----------------------------------------------------------
|
||||
wire address_in_range = (s_ctrlport.req.addr >= BASE_ADDRESS) && (s_ctrlport.req.addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
|
||||
logic [SCRATCH_REG_SIZE-1:0] scratch_reg;
|
||||
|
||||
always_ff @(posedge s_ctrlport.clk) begin
|
||||
// reset internal registers and responses
|
||||
if (s_ctrlport.rst) begin
|
||||
scratch_reg <= '0;
|
||||
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
s_ctrlport.resp.data <= 'x;
|
||||
s_ctrlport.resp.status <= STS_OKAY;
|
||||
|
||||
end else begin
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport.req.wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport.resp.ack <= 1'b1;
|
||||
s_ctrlport.resp.data <= 'x;
|
||||
s_ctrlport.resp.status <= STS_OKAY;
|
||||
|
||||
case (s_ctrlport.req.addr)
|
||||
BASE_ADDRESS + CORE_SCRATCH: begin
|
||||
scratch_reg <= s_ctrlport.req.data[ SCRATCH_REG_MSB : SCRATCH_REG];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport.resp.status <= STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (s_ctrlport.req.rd) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport.resp.ack <= 1'b1;
|
||||
s_ctrlport.resp.status <= STS_OKAY;
|
||||
s_ctrlport.resp.data <= '0;
|
||||
|
||||
case (s_ctrlport.req.addr)
|
||||
BASE_ADDRESS + CORE_SIGNATURE: begin
|
||||
s_ctrlport.resp.data[BOARD_ID_MSB : BOARD_ID]
|
||||
<= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_REVISION: begin
|
||||
s_ctrlport.resp.data[CURRENT_REV_MAJOR_MSB : CURRENT_REV_MAJOR]
|
||||
<= FPGA_CURRENT_VERSION_MAJOR[CURRENT_REV_MAJOR_SIZE-1:0];
|
||||
s_ctrlport.resp.data[CURRENT_REV_MINOR_MSB : CURRENT_REV_MINOR]
|
||||
<= FPGA_CURRENT_VERSION_MINOR[CURRENT_REV_MINOR_SIZE-1:0];
|
||||
s_ctrlport.resp.data[CURRENT_REV_BUILD_MSB : CURRENT_REV_BUILD]
|
||||
<= FPGA_CURRENT_VERSION_BUILD[CURRENT_REV_BUILD_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_OLDEST_REVISION: begin
|
||||
s_ctrlport.resp.data[OLDEST_REVISION_MAJOR_MSB : OLDEST_REVISION_MAJOR]
|
||||
<= FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR[OLDEST_REVISION_MAJOR_SIZE-1:0];
|
||||
s_ctrlport.resp.data[OLDEST_REVISION_MINOR_MSB : OLDEST_REVISION_MINOR]
|
||||
<= FPGA_OLDEST_COMPATIBLE_VERSION_MINOR[OLDEST_REVISION_MINOR_SIZE-1:0];
|
||||
s_ctrlport.resp.data[OLDEST_REVISION_BUILD_MSB : OLDEST_REVISION_BUILD]
|
||||
<= FPGA_OLDEST_COMPATIBLE_VERSION_BUILD[OLDEST_REVISION_BUILD_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_SCRATCH: begin
|
||||
s_ctrlport.resp.data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + GIT_HASH_REGISTER: begin
|
||||
`ifdef GIT_HASH
|
||||
s_ctrlport.resp.data <= `GIT_HASH;
|
||||
`else
|
||||
s_ctrlport.resp.data <= 32'hDEADBEEF;
|
||||
`endif
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
s_ctrlport.resp.data <= '0;
|
||||
if (address_in_range) begin
|
||||
s_ctrlport.resp.status <= STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="BASIC_REGS_REGMAP" readablestrobes="false" generateverilog="true" generatesv="false" ettusguidelines="true">
|
||||
// <group name="BASIC_REGS_REGISTERS" size="0x020">
|
||||
// <info>
|
||||
// This regmap contains the revision registers, signature register, a scratch register, and a slave control reg.
|
||||
// </info>
|
||||
//
|
||||
// <enumeratedtype name="FPGA_VERSION" showhex="true">
|
||||
// <info>
|
||||
// FPGA version.{BR/}
|
||||
// For guidance on when to update these revision numbers,
|
||||
// please refer to the register map documentation accordingly:
|
||||
// <li> Current version: @.BASIC_REGS_REGMAP..CORE_REVISION
|
||||
// <li> Oldest compatible version: @.BASIC_REGS_REGMAP..CORE_OLDEST_REVISION
|
||||
// <li> Version last modified: @.BASIC_REGS_REGMAP..VERSION_LAST_MODIFIED
|
||||
// </info>
|
||||
// <value name="BOARD_ID_VALUE" integer="0xB310"/>
|
||||
// <value name="FPGA_CURRENT_VERSION_MAJOR" integer="2"/>
|
||||
// <value name="FPGA_CURRENT_VERSION_MINOR" integer="1"/>
|
||||
// <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/>
|
||||
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="2"/>
|
||||
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
|
||||
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
|
||||
// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x26061611"/>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
// <register name="CORE_SIGNATURE" size="32" offset="0x00" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the unique signature of the MB. This signature is the same value as the one
|
||||
// stored on the board ID EEPROM
|
||||
// </info>
|
||||
// <bitfield name="BOARD_ID" range="15..0" type="integer">
|
||||
// <info>
|
||||
// Board ID corresponds to the las 16 digits of the motherboard part number.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_REVISION" size="32" offset="0x04" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the revision number of the current build
|
||||
// </info>
|
||||
// <bitfield name="CURRENT_REV_MAJOR" range="31..24">
|
||||
// <info>
|
||||
// Major version number of the current build
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CURRENT_REV_MINOR" range="23..16">
|
||||
// <info>
|
||||
// Minor version number of the current build
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CURRENT_REV_BUILD" range="15..0">
|
||||
// <info>
|
||||
// Build number of the current build
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_OLDEST_REVISION" size="32" offset="0x08" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the revision number of the oldest compatible revision
|
||||
// </info>
|
||||
// <bitfield name="OLDEST_REVISION_MAJOR" range="31..24">
|
||||
// <info>
|
||||
// Major version number of the oldest compatible revision
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="OLDEST_REVISION_MINOR" range="23..16">
|
||||
// <info>
|
||||
// Minor version number of the oldest compatible revision
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="OLDEST_REVISION_BUILD" range="15..0">
|
||||
// <info>
|
||||
// Build number of the oldest compatible revision
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="VERSION_LAST_MODIFIED" size="32" offset="0x0C" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the date/time when the version was last modified.
|
||||
// The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
|
||||
// </info>
|
||||
// <bitfield name="YY" range="31..24">
|
||||
// <info>This is the year number after 2000 (e.g. 2019 = 0x19).</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="MM" range="23..16"/>
|
||||
// <bitfield name="DD" range="15..8"/>
|
||||
// <bitfield name="HH" range="7..0"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_SCRATCH" size="32" offset="0x10" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Read/write scratch register
|
||||
// </info>
|
||||
// <bitfield name="SCRATCH_REG" range="31..0" initialvalue="0">
|
||||
// <info>
|
||||
// Returns the value written here previously.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="GIT_HASH_REGISTER" offset="0x14" size="32" writable="false">
|
||||
// <info>
|
||||
// Git hash of commit used to build this image.{br}
|
||||
// Value equals 0xDEADBEEF if the git hash was not used during synthesis.
|
||||
// </info>
|
||||
// <bitfield name="GIT_CLEAN" range="31..28">
|
||||
// <info>
|
||||
// 0x0 in case the git status was clean{br}
|
||||
// 0xF in case there were uncommitted changes
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GIT_HASH" range="27..0">
|
||||
// <info>7 hex digit hash code of the commit</info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
857
fpga/usrp3/top/b300/core/core_regs.sv
Normal file
857
fpga/usrp3/top/b300/core/core_regs.sv
Normal file
@ -0,0 +1,857 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: core_regs
|
||||
//
|
||||
// Description:
|
||||
// Implements register endpoints for B310 FPGA core
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module core_regs #(
|
||||
parameter logic [19:0] BASE_ADDRESS = 0,
|
||||
parameter logic [19:0] SIZE_ADDRESS = 0,
|
||||
parameter logic [15:0] PROTOVER = {8'd1, 8'd0},
|
||||
parameter int CHDR_WIDTH = 64,
|
||||
parameter int NUM_TIMEKEEPERS = 1
|
||||
) (
|
||||
ctrlport_if.slave s_ctrlport,
|
||||
output logic [15:0] device_id,
|
||||
|
||||
// CORE_SW_RESETS
|
||||
output logic radio_clk_gen_rst,
|
||||
|
||||
// CORE_CLOCK_CTRL
|
||||
output logic ref_clk_source,
|
||||
output logic lmk_source_select,
|
||||
output logic tcxo_en,
|
||||
output logic lmk_reset,
|
||||
output logic use_external_pps,
|
||||
|
||||
// CORE_CLOCK_STATUS
|
||||
input wire lmk_lock_status,
|
||||
|
||||
// Device DNA
|
||||
input wire [63:0] dev_dna,
|
||||
|
||||
// Radio Timestamp
|
||||
input wire [63:0] radio_time,
|
||||
|
||||
// PPS generator Divider
|
||||
output logic [31:0] int_pps_div,
|
||||
|
||||
// PPS in to rclock delay
|
||||
output logic [ 9:0] pps_in_to_rclk_delay,
|
||||
output logic [26:0] lmk_sync_delay,
|
||||
output logic lmk_sync_clk_sel,
|
||||
output logic lmk_clkin0_sync_sel,
|
||||
output logic lmk_sync_trigger,
|
||||
input wire lmk_sync_done,
|
||||
output logic lmk05318_pd_n,
|
||||
|
||||
// FP_GPIO Source
|
||||
output logic [19:0] fp_gpio_src,
|
||||
|
||||
// GPS control
|
||||
output logic gps_reset_n,
|
||||
output logic gps_ant_pwr_en,
|
||||
input wire [1:0] gps_lmk_status,
|
||||
input wire gps_pw_fault,
|
||||
output logic gps_lmk_gpio,
|
||||
input wire gps_lmk_pps_monitor,
|
||||
output logic gps_bypass_lmk,
|
||||
|
||||
// Thunderbolt resets
|
||||
output logic tbolt_pd_ctrl_pulse_rst,
|
||||
// Power control and status
|
||||
input wire pwr_1v2_pg,
|
||||
input wire pwr_25w_src,
|
||||
input wire pwr_typec_negotiated,
|
||||
input wire pwr_monitor_alert,
|
||||
output logic pwr_led_orange,
|
||||
|
||||
// Temperature monitor
|
||||
input wire [11:0] device_temp
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
`include "../regmap/core_regs_regmap_utils.vh"
|
||||
|
||||
//vhook_sigstart
|
||||
//vhook_sigend
|
||||
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//----------------------------------------------------------
|
||||
wire address_in_range = (s_ctrlport.req.addr >= BASE_ADDRESS) &&
|
||||
(s_ctrlport.req.addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
|
||||
// Local register copies
|
||||
logic [DEVICE_ID_SIZE-1:0] device_id_reg = '0;
|
||||
logic [ 31:0] int_pps_div_reg = 32'd122_880_000;
|
||||
logic ref_clk_source_reg = 1'b1;
|
||||
|
||||
logic [31:0] radio_time_hi;
|
||||
|
||||
assign device_id = device_id_reg;
|
||||
assign ref_clk_source = ref_clk_source_reg;
|
||||
assign int_pps_div = int_pps_div_reg;
|
||||
|
||||
always_ff @(posedge s_ctrlport.clk) begin
|
||||
// reset internal registers and responses
|
||||
if (s_ctrlport.rst) begin
|
||||
device_id_reg <= '0;
|
||||
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
s_ctrlport.resp.data <= 'x;
|
||||
s_ctrlport.resp.status <= STS_OKAY;
|
||||
|
||||
// reset controls
|
||||
radio_clk_gen_rst <= 1'b0;
|
||||
// By default, use internal reference clock
|
||||
ref_clk_source_reg <= 1'b1;
|
||||
lmk_source_select <= 1'b0;
|
||||
tcxo_en <= 1'b0;
|
||||
lmk_reset <= 1'b0;
|
||||
use_external_pps <= 1'b0;
|
||||
int_pps_div_reg <= 32'd122_880_000;
|
||||
pps_in_to_rclk_delay <= 10'b0;
|
||||
lmk_sync_delay <= 27'b0;
|
||||
lmk_sync_trigger <= 1'b0;
|
||||
lmk_sync_clk_sel <= 1'b0;
|
||||
lmk_clkin0_sync_sel <= 1'b0;
|
||||
lmk05318_pd_n <= 1'b0;
|
||||
radio_time_hi <= 'X;
|
||||
|
||||
// Thunderbolt defaults
|
||||
tbolt_pd_ctrl_pulse_rst <= 1'b0;
|
||||
pwr_led_orange <= 1'b0;
|
||||
|
||||
// MISC defaults
|
||||
fp_gpio_src <= '0;
|
||||
gps_reset_n <= 1'b0;
|
||||
gps_ant_pwr_en <= 1'b0;
|
||||
gps_lmk_gpio <= 1'b0;
|
||||
gps_bypass_lmk <= 1'b0;
|
||||
end else begin
|
||||
|
||||
// Clear pulse reset signals by default
|
||||
tbolt_pd_ctrl_pulse_rst <= 1'b0;
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport.req.wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport.resp.ack <= 1'b1;
|
||||
s_ctrlport.resp.data <= 'x;
|
||||
s_ctrlport.resp.status <= STS_OKAY;
|
||||
|
||||
case (s_ctrlport.req.addr)
|
||||
BASE_ADDRESS + FPGA_DEVICE_ID: begin
|
||||
device_id_reg <= s_ctrlport.req.data[ DEVICE_ID_MSB : DEVICE_ID ];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_SW_RESETS: begin
|
||||
radio_clk_gen_rst <= s_ctrlport.req.data[ RADIO_CLK_GEN_RST ];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_CLOCK_CTRL: begin
|
||||
ref_clk_source_reg <= s_ctrlport.req.data[ REF_CLK_SOURCE ];
|
||||
lmk_source_select <= s_ctrlport.req.data[ LMK_SOURCE_SELECT ];
|
||||
tcxo_en <= s_ctrlport.req.data[ TCXO_EN ];
|
||||
lmk_reset <= s_ctrlport.req.data[ LMK_RESET ];
|
||||
use_external_pps <= s_ctrlport.req.data[ USE_EXTERNAL_PPS ];
|
||||
lmk05318_pd_n <= s_ctrlport.req.data[ LMK05318_PD_N ];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + FP_GPIO_SRC: begin
|
||||
fp_gpio_src[ FP_GPIO9_SRC_MSB : FP_GPIO9_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO9_SRC_MSB : FP_GPIO9_SRC ];
|
||||
fp_gpio_src[ FP_GPIO8_SRC_MSB : FP_GPIO8_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO8_SRC_MSB : FP_GPIO8_SRC ];
|
||||
fp_gpio_src[ FP_GPIO7_SRC_MSB : FP_GPIO7_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO7_SRC_MSB : FP_GPIO7_SRC ];
|
||||
fp_gpio_src[ FP_GPIO6_SRC_MSB : FP_GPIO6_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO6_SRC_MSB : FP_GPIO6_SRC ];
|
||||
fp_gpio_src[ FP_GPIO5_SRC_MSB : FP_GPIO5_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO5_SRC_MSB : FP_GPIO5_SRC ];
|
||||
fp_gpio_src[ FP_GPIO4_SRC_MSB : FP_GPIO4_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO4_SRC_MSB : FP_GPIO4_SRC ];
|
||||
fp_gpio_src[ FP_GPIO3_SRC_MSB : FP_GPIO3_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO3_SRC_MSB : FP_GPIO3_SRC ];
|
||||
fp_gpio_src[ FP_GPIO2_SRC_MSB : FP_GPIO2_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO2_SRC_MSB : FP_GPIO2_SRC ];
|
||||
fp_gpio_src[ FP_GPIO1_SRC_MSB : FP_GPIO1_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO1_SRC_MSB : FP_GPIO1_SRC ];
|
||||
fp_gpio_src[ FP_GPIO0_SRC_MSB : FP_GPIO0_SRC ] <=
|
||||
s_ctrlport.req.data[ FP_GPIO0_SRC_MSB : FP_GPIO0_SRC ];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + GPS_CTRL: begin
|
||||
gps_reset_n <= s_ctrlport.req.data[ REG_GPS_RESET_N ];
|
||||
gps_ant_pwr_en <= s_ctrlport.req.data[ REG_GPS_ANT_PWR_EN ];
|
||||
gps_bypass_lmk <= s_ctrlport.req.data[ GPS_BYPASS_LMK ];
|
||||
gps_lmk_gpio <= s_ctrlport.req.data[ GPS_LMK_GPIO ];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + INT_PPS_DIVIDER: begin
|
||||
int_pps_div_reg <= s_ctrlport.req.data[INT_PPS_DIV_MSB : INT_PPS_DIV];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + PPS_IN_CTRL: begin
|
||||
pps_in_to_rclk_delay <=
|
||||
s_ctrlport.req.data[PPS_IN_TO_RCLK_DELAY_MSB : PPS_IN_TO_RCLK_DELAY];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + LMK_SYNC_CTRL: begin
|
||||
lmk_sync_delay <= s_ctrlport.req.data[LMK_SYNC_DELAY_MSB : LMK_SYNC_DELAY];
|
||||
lmk_sync_trigger <= s_ctrlport.req.data[LMK_SYNC_TRIGGER];
|
||||
lmk_sync_clk_sel <= s_ctrlport.req.data[LMK_SYNC_CLK_SEL];
|
||||
lmk_clkin0_sync_sel <= s_ctrlport.req.data[LMK_CLKIN0_SYNC_SEL];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + TBOLT_CTRL: begin
|
||||
tbolt_pd_ctrl_pulse_rst <= s_ctrlport.req.data[TBOLT_PD_CTRL_PULSE_RST];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + POWER_CONTROL_STS: begin
|
||||
pwr_led_orange <= s_ctrlport.req.data[POWER_LED_OVERRIDE];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport.resp.status <= STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (s_ctrlport.req.rd) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport.resp.ack <= 1'b1;
|
||||
s_ctrlport.resp.status <= STS_OKAY;
|
||||
s_ctrlport.resp.data <= '0;
|
||||
|
||||
case (s_ctrlport.req.addr)
|
||||
BASE_ADDRESS + FPGA_DEVICE_ID: begin
|
||||
s_ctrlport.resp.data[DEVICE_ID_MSB : DEVICE_ID]
|
||||
<= device_id_reg;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_SW_RESETS: begin
|
||||
s_ctrlport.resp.data[RADIO_CLK_GEN_RST]
|
||||
<= radio_clk_gen_rst;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_CLOCK_CTRL: begin
|
||||
s_ctrlport.resp.data[REF_CLK_SOURCE]
|
||||
<= ref_clk_source_reg;
|
||||
s_ctrlport.resp.data[LMK_SOURCE_SELECT]
|
||||
<= lmk_source_select;
|
||||
s_ctrlport.resp.data[TCXO_EN]
|
||||
<= tcxo_en;
|
||||
s_ctrlport.resp.data[LMK_RESET]
|
||||
<= lmk_reset;
|
||||
s_ctrlport.resp.data[USE_EXTERNAL_PPS]
|
||||
<= use_external_pps;
|
||||
s_ctrlport.resp.data[LMK05318_PD_N]
|
||||
<= lmk05318_pd_n;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_CLOCK_STATUS: begin
|
||||
s_ctrlport.resp.data[LMK_LOCK_STATUS]
|
||||
<= lmk_lock_status;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + DEVICE_DNA_LOW: begin
|
||||
s_ctrlport.resp.data[DEV_DNA_LO_MSB : DEV_DNA_LO]
|
||||
<= dev_dna[31:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + DEVICE_DNA_HIGH: begin
|
||||
s_ctrlport.resp.data[DEV_DNA_HI_MSB : DEV_DNA_HI]
|
||||
<= dev_dna[63:32];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_COMPAT_NUM: begin
|
||||
s_ctrlport.resp.data[CORE_MAJOR_COMPAT_MSB : CORE_MAJOR_COMPAT]
|
||||
<= CORE_COMPAT_MAJOR_VAL[CORE_MAJOR_COMPAT_SIZE-1:0];
|
||||
s_ctrlport.resp.data[CORE_MINOR_COMPAT_MSB : CORE_MINOR_COMPAT]
|
||||
<= CORE_COMPAT_MINOR_VAL[CORE_MINOR_COMPAT_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_RFNOC_INFO: begin
|
||||
s_ctrlport.resp.data[RFNOC_PROTO_VERSION_MSB : RFNOC_PROTO_VERSION]
|
||||
<= PROTOVER[RFNOC_PROTO_VERSION_SIZE-1:0];
|
||||
s_ctrlport.resp.data[RFNOC_CHDR_WIDTH_MSB : RFNOC_CHDR_WIDTH]
|
||||
<= CHDR_WIDTH[RFNOC_CHDR_WIDTH_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + RADIO_TIME_LOW: begin
|
||||
s_ctrlport.resp.data <= radio_time[31:0];
|
||||
radio_time_hi <= radio_time[63:32];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + RADIO_TIME_HIGH: begin
|
||||
s_ctrlport.resp.data <= radio_time_hi;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + INT_PPS_DIVIDER: begin
|
||||
s_ctrlport.resp.data[INT_PPS_DIV_MSB : INT_PPS_DIV]
|
||||
<= int_pps_div_reg;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + PPS_IN_CTRL: begin
|
||||
s_ctrlport.resp.data[PPS_IN_TO_RCLK_DELAY_MSB : PPS_IN_TO_RCLK_DELAY]
|
||||
<= pps_in_to_rclk_delay;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + LMK_SYNC_CTRL: begin
|
||||
s_ctrlport.resp.data[LMK_SYNC_DELAY_MSB : LMK_SYNC_DELAY]
|
||||
<= lmk_sync_delay;
|
||||
s_ctrlport.resp.data[LMK_SYNC_DONE]
|
||||
<= lmk_sync_done;
|
||||
s_ctrlport.resp.data[LMK_SYNC_TRIGGER]
|
||||
<= lmk_sync_trigger;
|
||||
s_ctrlport.resp.data[LMK_SYNC_CLK_SEL]
|
||||
<= lmk_sync_clk_sel;
|
||||
s_ctrlport.resp.data[LMK_CLKIN0_SYNC_SEL]
|
||||
<= lmk_clkin0_sync_sel;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_NUM_TIMEKEEPERS: begin
|
||||
s_ctrlport.resp.data[CORE_NUM_TIMEKEEPERS_VAL_MSB : CORE_NUM_TIMEKEEPERS_VAL]
|
||||
<= NUM_TIMEKEEPERS[CORE_NUM_TIMEKEEPERS_VAL_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CORE_BUILD_SEED: begin
|
||||
`ifndef BUILD_SEED
|
||||
`define BUILD_SEED 32'b0
|
||||
`endif
|
||||
s_ctrlport.resp.data[CORE_BUILD_SEED_VAL_MSB : CORE_BUILD_SEED_VAL]
|
||||
<= `BUILD_SEED;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + FP_GPIO_SRC: begin
|
||||
s_ctrlport.resp.data[FP_GPIO9_SRC_MSB : FP_GPIO9_SRC]
|
||||
<= fp_gpio_src[FP_GPIO9_SRC_MSB : FP_GPIO9_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO8_SRC_MSB : FP_GPIO8_SRC]
|
||||
<= fp_gpio_src[FP_GPIO8_SRC_MSB : FP_GPIO8_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO7_SRC_MSB : FP_GPIO7_SRC]
|
||||
<= fp_gpio_src[FP_GPIO7_SRC_MSB : FP_GPIO7_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO6_SRC_MSB : FP_GPIO6_SRC]
|
||||
<= fp_gpio_src[FP_GPIO6_SRC_MSB : FP_GPIO6_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO5_SRC_MSB : FP_GPIO5_SRC]
|
||||
<= fp_gpio_src[FP_GPIO5_SRC_MSB : FP_GPIO5_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO4_SRC_MSB : FP_GPIO4_SRC]
|
||||
<= fp_gpio_src[FP_GPIO4_SRC_MSB : FP_GPIO4_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO3_SRC_MSB : FP_GPIO3_SRC]
|
||||
<= fp_gpio_src[FP_GPIO3_SRC_MSB : FP_GPIO3_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO2_SRC_MSB : FP_GPIO2_SRC]
|
||||
<= fp_gpio_src[FP_GPIO2_SRC_MSB : FP_GPIO2_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO1_SRC_MSB : FP_GPIO1_SRC]
|
||||
<= fp_gpio_src[FP_GPIO1_SRC_MSB : FP_GPIO1_SRC];
|
||||
s_ctrlport.resp.data[FP_GPIO0_SRC_MSB : FP_GPIO0_SRC]
|
||||
<= fp_gpio_src[FP_GPIO0_SRC_MSB : FP_GPIO0_SRC];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + GPS_CTRL: begin
|
||||
s_ctrlport.resp.data[REG_GPS_RESET_N]
|
||||
<= gps_reset_n;
|
||||
s_ctrlport.resp.data[REG_GPS_ANT_PWR_EN]
|
||||
<= gps_ant_pwr_en;
|
||||
s_ctrlport.resp.data[GPS_PW_FAULT]
|
||||
<= gps_pw_fault;
|
||||
s_ctrlport.resp.data[GPS_LMK_PPS_MONITOR]
|
||||
<= gps_lmk_pps_monitor;
|
||||
s_ctrlport.resp.data[GPS_LMK_STATUS_MSB : GPS_LMK_STATUS]
|
||||
<= gps_lmk_status;
|
||||
s_ctrlport.resp.data[GPS_LMK_GPIO]
|
||||
<= gps_lmk_gpio;
|
||||
s_ctrlport.resp.data[GPS_BYPASS_LMK]
|
||||
<= gps_bypass_lmk;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + TEMP_MON: begin
|
||||
s_ctrlport.resp.data[DEVICE_TEMP_MSB : DEVICE_TEMP]
|
||||
<= device_temp;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + TBOLT_CTRL: begin
|
||||
// Return a value to service IO mapped accesses that expect to read back
|
||||
// from the address they write.
|
||||
s_ctrlport.resp.data[TBOLT_PD_CTRL_PULSE_RST] <= '0;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + POWER_CONTROL_STS: begin
|
||||
s_ctrlport.resp.data[POWER_GOOD_1V2]
|
||||
<= pwr_1v2_pg;
|
||||
s_ctrlport.resp.data[POWER_MONITOR_ALERT]
|
||||
<= pwr_monitor_alert;
|
||||
s_ctrlport.resp.data[POWER_25W_SRC]
|
||||
<= pwr_25w_src;
|
||||
s_ctrlport.resp.data[TYPEC_POWER_NEGOTIATED]
|
||||
<= pwr_typec_negotiated;
|
||||
s_ctrlport.resp.data[POWER_LED_OVERRIDE]
|
||||
<= pwr_led_orange;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
s_ctrlport.resp.data <= '0;
|
||||
if (address_in_range) begin
|
||||
s_ctrlport.resp.status <= STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule : core_regs
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="CORE_REGS_REGMAP" readablestrobes="false" generatesv="false" generateverilog="true" ettusguidelines="true">
|
||||
// <group name="CORE_REGS_REGISTERS" size="0x080">
|
||||
// <info>
|
||||
// This regmap contains general control registers for the FPGA core.
|
||||
// </info>
|
||||
//
|
||||
// <enumeratedtype name="CLOCKING_SPI_SLAVES" showhex="true">
|
||||
// <info>
|
||||
// Mapping of the SPI slaves on the FPGA core.
|
||||
// </info>
|
||||
// <value name="CLOCKING_SPI_LMK04832_SS" integer="0"/>
|
||||
// <value name="CLOCKING_SPI_TCXO_DAC_SS" integer="1"/>
|
||||
// <value name="CLOCKING_SPI_LMK053_SS" integer="2"/>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
// <enumeratedtype name="CORE_COMPATIBILITY" showhex="true">
|
||||
// <info>
|
||||
// Mapping of the SPI slaves on the FPGA core.
|
||||
// </info>
|
||||
// <value name="CORE_COMPAT_MAJOR_VAL" integer="2"/>
|
||||
// <value name="CORE_COMPAT_MINOR_VAL" integer="1"/>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
// <register name="FPGA_DEVICE_ID" size="32" offset="0x00" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Sets the device ID of the FPGA core. This is used to enumerate the device in RFNoC.
|
||||
// </info>
|
||||
// <bitfield name="DEVICE_ID" range="15..0" type="integer">
|
||||
// <info>
|
||||
// Device ID.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_SW_RESETS" size="32" offset="0x04" attributes="Writable">
|
||||
// <info>
|
||||
// Controls soft-resets across the FPGA
|
||||
// </info>
|
||||
// <bitfield name="RADIO_CLK_GEN_RST" range="0">
|
||||
// <info>
|
||||
// Resets clocking resources for radio clock generation.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_CLOCK_CTRL" size="32" offset="0x08" attributes="Writable">
|
||||
// <info>
|
||||
// Miscellaneous clock control register.
|
||||
// </info>
|
||||
// <bitfield name="REF_CLK_SOURCE" range="0" initialvalue="1">
|
||||
// <info>
|
||||
// Selects the reference clock source. 0 = GPSDO, 1 = Internal.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK_SOURCE_SELECT" range="4">
|
||||
// <info>
|
||||
// Selects the LMK clock source. 0 = 122.88MHz, 1 = 125MHz
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TCXO_EN" range="8">
|
||||
// <info>
|
||||
// Enable external TCXO oscillator.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK_RESET" range="12">
|
||||
// <info>
|
||||
// Controls the reset pin on the LMK clock generator.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK05318_PD_N" range="13">
|
||||
// <info>
|
||||
// Controls the power down pin to the LMK05318 chip. 0 = power down. 1 = power up.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="USE_EXTERNAL_PPS" range="16">
|
||||
// <info>
|
||||
// Selects if the FPGA should use the internal PPS signal for its timekeeping.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_CLOCK_STATUS" size="32" offset="0x0C" attributes="Readable">
|
||||
// <info>
|
||||
// Miscellaneous clock status register.
|
||||
// </info>
|
||||
// <bitfield name="LMK_LOCK_STATUS" range="8">
|
||||
// <info>
|
||||
// Reports the lock status of the LMK clock generator.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="DEVICE_DNA_LOW" size="32" offset="0x10" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the lower 32 bits of the device DNA.
|
||||
// </info>
|
||||
// <bitfield name="DEV_DNA_LO" range="31..0">
|
||||
// <info>
|
||||
// DNA low bits.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="DEVICE_DNA_HIGH" size="32" offset="0x14" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the upper 32 bits of the device DNA.
|
||||
// </info>
|
||||
// <bitfield name="DEV_DNA_HI" range="31..0">
|
||||
// <info>
|
||||
// DNA high bits.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_COMPAT_NUM" size="32" offset="0x18" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the compatibility number for the core.
|
||||
// </info>
|
||||
// <bitfield name="CORE_MAJOR_COMPAT" range="31..16" type="integer">
|
||||
// <info>
|
||||
// Major compatibility number.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CORE_MINOR_COMPAT" range="15..0" type="integer">
|
||||
// <info>
|
||||
// Minor compatibility number.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_RFNOC_INFO" size="32" offset="0x1C" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the RFNoC Core settings.
|
||||
// </info>
|
||||
// <bitfield name="RFNOC_PROTO_VERSION" range="15..0" type="integer">
|
||||
// <info>
|
||||
// RFNoC protocol version.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFNOC_CHDR_WIDTH" range="31..16" type="integer">
|
||||
// <info>
|
||||
// RFNoC CHDR width.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RADIO_TIME_LOW" size="32" offset="0x20" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the lower 32 bits of the current radio time. Read the LOW
|
||||
// register followed by the HIGH register to get a coherent 64-bit value.
|
||||
// </info>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RADIO_TIME_HIGH" size="32" offset="0x24" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the upper 32 bits of the radio time from when the LOW register
|
||||
// was read. Read the LOW register followed by the HIGH register to get a
|
||||
// coherent 64-bit value.
|
||||
// </info>
|
||||
// </register>
|
||||
//
|
||||
// <register name="INT_PPS_DIVIDER" size="32" offset="0x28" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// Controls the divider for the internal PPS generator.
|
||||
// </info>
|
||||
// <bitfield name="INT_PPS_DIV" range="31..0" type="integer" initialvalue="122880000">
|
||||
// <info>
|
||||
// Divider value for internal PPS generator.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_NUM_TIMEKEEPERS" size="32" offset="0x2C" attributes="Readable">
|
||||
// <info>
|
||||
// Reports the number of timekeepers in the system.
|
||||
// </info>
|
||||
// <bitfield name="CORE_NUM_TIMEKEEPERS_VAL" range="31..0" type="integer">
|
||||
// <info>
|
||||
// Number of timekeepers in the system.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CORE_BUILD_SEED" size="32" offset="0x30" attributes="Readable">
|
||||
// <info>
|
||||
// Holds the build seed for the current FPGA build.
|
||||
// </info>
|
||||
// <bitfield name="CORE_BUILD_SEED_VAL" range="31..0" type="integer">
|
||||
// <info>
|
||||
// Build seed value.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="FP_GPIO_SRC" size="32" offset="0x34" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// Controls the source of the front panel GPIOs.
|
||||
// </info>
|
||||
// <bitfield name="FP_GPIO0_SRC" range="1..0">
|
||||
// <info>
|
||||
// Source for front panel GPIO0. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO1_SRC" range="3..2">
|
||||
// <info>
|
||||
// Source for front panel GPIO1. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO2_SRC" range="5..4">
|
||||
// <info>
|
||||
// Source for front panel GPIO2. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO3_SRC" range="7..6">
|
||||
// <info>
|
||||
// Source for front panel GPIO3. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO4_SRC" range="9..8">
|
||||
// <info>
|
||||
// Source for front panel GPIO4. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO5_SRC" range="11..10">
|
||||
// <info>
|
||||
// Source for front panel GPIO5. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO6_SRC" range="13..12">
|
||||
// <info>
|
||||
// Source for front panel GPIO6. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO7_SRC" range="15..14">
|
||||
// <info>
|
||||
// Source for front panel GPIO7. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO8_SRC" range="17..16">
|
||||
// <info>
|
||||
// Source for front panel GPIO8. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FP_GPIO9_SRC" range="19..18">
|
||||
// <info>
|
||||
// Source for front panel GPIO9. 0 = CH0_ATR, 1 = CH1_ATR.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="GPS_CTRL" size="32" offset="0x38" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// Controls GPIO lines to the GPS circuits.
|
||||
// </info>
|
||||
// <bitfield name="REG_GPS_RESET_N" range="0">
|
||||
// <info>
|
||||
// 0 = GPS in reset. 1 = GPS out of reset.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="REG_GPS_ANT_PWR_EN" range="1">
|
||||
// <info>
|
||||
// 0 = GPS antenna power disabled. 1 = GPS antenna power enabled.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GPS_PW_FAULT" range="4" attributes="Readable">
|
||||
// <info>
|
||||
// Read-only bit that indicates an overcurrent fault on the GPS power
|
||||
// for active antennas.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GPS_LMK_PPS_MONITOR" range="8" attributes="Readable">
|
||||
// <info>
|
||||
// This bit toggles on the rising edge of the GPS LMK PPS signal.
|
||||
// Can be used to monitor the GPS LMK PPS signal in software.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GPS_LMK_STATUS" range="13..12" attributes="Readable">
|
||||
// <info>
|
||||
// Reports the state of the status indicators from the LMK05318.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GPS_LMK_GPIO" range="16">
|
||||
// <info>
|
||||
// Controls output to the LMK05318's GPIO0/SYNCN line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GPS_BYPASS_LMK" range="20">
|
||||
// <info>
|
||||
// Allows using the PPS signal directly from the GPS chip instead of the LMK05318 when
|
||||
// using the GPSDO.
|
||||
// 0 = LMK05318 is used to generate the GPS PPS signal.
|
||||
// 1 = Use PPS signal from an GPS chip.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="TEMP_MON" size="32" offset="0x3C" attributes="Readable">
|
||||
// <info>
|
||||
// Reports values from the FPGA temperature monitor.
|
||||
// </info>
|
||||
// <bitfield name="DEVICE_TEMP" range="11..0" type="integer">
|
||||
// <info>
|
||||
// Current FPGA temperature. To convert to degrees Celsius, use the
|
||||
// formula: Temp (C) = [(DEVICE_TEMP x 503.975) / 4096 - 273.15]
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="LMK_SYNC_CTRL" size="32" offset="0x40" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// </info>
|
||||
// <bitfield name="LMK_CLKIN0_SYNC_SEL" range="31">
|
||||
// <info>
|
||||
// REVA sets this to 0 to select SYNC pin as syc pin with not as good
|
||||
// setup/hold time.
|
||||
// REVB sets this to 1 to select ClkIN0 pin as sync pin with better
|
||||
// setup/hold time. When setting this pin to 1, then 1 needs
|
||||
// subtracted from the @PPS_IN_TO_RCLK_DELAY field as the LMK has one
|
||||
// register delay on ClkIN0 vs Sync.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK_SYNC_CLK_SEL" range="30">
|
||||
// <info>
|
||||
// Set to 0 to make lmk sync output synchronous to radio_clk (for clock distribution mode)
|
||||
// Set to 1 to make lmk sync output synchronous to ref_clk (for ext 10MHz ref in)
|
||||
// - "0" needed for clock distribution mode to meet setup/hold of flip
|
||||
// flop inside the LMK04832 synchronous to ref_clk. Not intuitive this
|
||||
// is needed, but reason why timing is better is radio_clk is from
|
||||
// a pll where ref_clk is from an IO buffer with large delay.
|
||||
// - "1" needed for external 10MHz mode because during synchronization
|
||||
// the radio_clk looses lock due to clk0 being reset. Thus sync needs
|
||||
// driven from active ref_clk. It is easy to meet timing to LMK with
|
||||
// 10MHz clock due to it having a 100ns period.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK_SYNC_DONE" range="29" attributes = "Readable">
|
||||
// <info>Indicates the success of the PLL reset started by @.PLL_SYNC_TRIGGER. Reset on deassertion of @.PLL_SYNC_TRIGGER.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK_SYNC_TRIGGER" range="28">
|
||||
// <info>
|
||||
// Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge.
|
||||
// There is no self reset on this trigger.
|
||||
// Keep this trigger asserted until @.PLL_SYNC_DONE is asserted.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LMK_SYNC_DELAY" range="26..0">
|
||||
// <info>
|
||||
// Controls the delay from PPS_IN to LMK_SYNC being sent to the LMK
|
||||
// chip in in ext_ref_clk cycles.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="PPS_IN_CTRL" size="32" offset="0x44" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// </info>
|
||||
// <bitfield name="PPS_IN_TO_RCLK_DELAY" range="9..0">
|
||||
// Due to the HDL implementation the rising edge of the SYNC signal for
|
||||
// the LMK04832 is generated 2 clock cycles after the PPS rising edge.
|
||||
// This delay can be further increased by setting this delay value
|
||||
// (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).{br}
|
||||
//
|
||||
// Controls the delay from PPS_IN to radio clock PPS IN, in ext_ref_clk
|
||||
// cycles. Sync gets sent to LMK, LMK clears its output counters to
|
||||
// zero. DEV_CLK/radio_clk start toggling now synchronized to the
|
||||
// 10Mhz ref_clk edge. Every PPS signal DEV_CLK/radio_clk will
|
||||
// have the same relationship, but offset in phase.
|
||||
// Delay PPS this many 10Mhz ext_ref_clk cycles such that its
|
||||
// rising edge aligns with the radio_clk domain. Internal PLL divider
|
||||
// is 250 for 10MHz clock, therefore 250 is a typical delay for this.
|
||||
// Set this register to 248 to get zero offset between the two clocks.
|
||||
// We however don't want 0 offset, so we set to 251 instead (253 actual
|
||||
// delay) to cause radio_clk to be 7.03125ns out of 8.128021ns for an
|
||||
// offset of 1.10677ns.
|
||||
// In practice it is off slightly to account for extra RTL delays.
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="TBOLT_CTRL" size="32" offset="0x48" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// Control register for Thunderbolt controller resets.
|
||||
// </info>
|
||||
// <bitfield name="TBOLT_PD_CTRL_PULSE_RST" range="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Writing a 1 to this bit will pulse the reset line to the Thunderbolt PD
|
||||
// controller, forcing the FPGA to reconfigure. There's is a 500ms delay
|
||||
// before the pulse is generated to allow software to service the write
|
||||
// transaction and return an ACK before the FPGA resets.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="POWER_CONTROL_STS" size="32" offset="0x4C" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// Control/status register for power signals
|
||||
// </info>
|
||||
// <bitfield name="POWER_GOOD_1V2" range="0" attributes="Readable">
|
||||
// <info>
|
||||
// Status of 1.2V power supply.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="POWER_MONITOR_ALERT" range="1" attributes="Readable">
|
||||
// <info>
|
||||
// Indicates if the INA219 power monitor has asserted an alert.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="POWER_25W_SRC" range="4" attributes="Readable">
|
||||
// <info>
|
||||
// Indicates if an external source is providing 25W of power to the device.
|
||||
// 0: Power is provided by PCIe slot, 1: Power is provided by external source.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TYPEC_POWER_NEGOTIATED" range="5" attributes="Readable">
|
||||
// <info>
|
||||
// Indicates if the USB Type-C power negotiation has completed successfully.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="POWER_LED_OVERRIDE" range="8" attributes="Writable|Readable">
|
||||
// <info>
|
||||
// Control for power status LED.
|
||||
// 0 = Blue if powered up, 1 = force orange.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
876
fpga/usrp3/top/b300/core/radio_control_regs.sv
Normal file
876
fpga/usrp3/top/b300/core/radio_control_regs.sv
Normal file
@ -0,0 +1,876 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: radio_control_regs
|
||||
//
|
||||
// Description:
|
||||
// Implements radio block ctrlport endpoints for B310 FPGA
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module radio_control_regs #(
|
||||
parameter logic [19:0] BASE_ADDRESS = 0,
|
||||
parameter logic [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
ctrlport_if.slave s_ctrlport,
|
||||
|
||||
// Radio Misc. Control/Status
|
||||
output logic radio_adrv_reset,
|
||||
output logic radio_test_enable,
|
||||
|
||||
// Radio LED Controls
|
||||
output logic [1:0] radio_led_tx_green,
|
||||
output logic [1:0] radio_led_tx_red,
|
||||
output logic [1:0] radio_led_rx_green,
|
||||
|
||||
// Radio FP GPIO Controls
|
||||
output logic [9:0] radio_ch0_fp_gpio_out,
|
||||
output logic [9:0] radio_ch1_fp_gpio_out,
|
||||
input wire [9:0] radio_fp_gpio_in,
|
||||
output logic [9:0] radio_ch0_fp_gpio_dir,
|
||||
output logic [9:0] radio_ch1_fp_gpio_dir,
|
||||
|
||||
// Radio ADRV GPIO Controls
|
||||
output logic [3:0] radio_ch0_adrv_gpio_out,
|
||||
output logic [3:0] radio_ch1_adrv_gpio_out,
|
||||
input wire [3:0] radio_ch0_adrv_gpio_in,
|
||||
input wire [3:0] radio_ch1_adrv_gpio_in,
|
||||
output logic [3:0] radio_ch0_adrv_gpio_dir,
|
||||
output logic [3:0] radio_ch1_adrv_gpio_dir,
|
||||
output logic [3:0] radio_ch0_adrv_trx_out,
|
||||
output logic [3:0] radio_ch1_adrv_trx_out,
|
||||
input wire radio_ch0_adrv_int,
|
||||
input wire radio_ch1_adrv_int,
|
||||
|
||||
// Radio path control signals
|
||||
output logic [1:0] radio_enable_tdr,
|
||||
output logic [1:0] radio_rx_bypass,
|
||||
|
||||
// Radio ATR state
|
||||
input wire [1:0] rx_running,
|
||||
input wire [1:0] tx_running
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
`include "../regmap/radio_control_regmap_utils.vh"
|
||||
|
||||
//vhook_sigstart
|
||||
//vhook_sigend
|
||||
|
||||
// ATR readback signals
|
||||
logic [7:0] ch0_led_atr_rb;
|
||||
logic [7:0] ch1_led_atr_rb;
|
||||
logic [9:0] ch0_fp_gpio_atr_rb;
|
||||
logic [9:0] ch1_fp_gpio_atr_rb;
|
||||
logic [7:0] ch0_adrv_gpio_atr_rb;
|
||||
logic [7:0] ch1_adrv_gpio_atr_rb;
|
||||
logic [1:0] ch0_path_ctrl_rb;
|
||||
logic [1:0] ch1_path_ctrl_rb;
|
||||
|
||||
// Split incoming ctrlport into two interfaces:
|
||||
// - One for the registers implemented in this module
|
||||
// - One for the ATR registers
|
||||
localparam int NUM_REG_BLOCKS = 2; // Number of core blocks in the B310 core
|
||||
|
||||
ctrlport_if m_radio_regs_ctrlport_array [NUM_REG_BLOCKS] (.clk(s_ctrlport.clk), .rst(s_ctrlport.rst));
|
||||
|
||||
//vhook_e ctrlport_if_splitter
|
||||
//vhook_a NUM_SLAVES NUM_REG_BLOCKS
|
||||
//vhook_a m_ctrlport m_radio_regs_ctrlport_array
|
||||
ctrlport_if_splitter #(
|
||||
.NUM_SLAVES(NUM_REG_BLOCKS) //int:=2
|
||||
) ctrlport_if_splitterx (
|
||||
.s_ctrlport(s_ctrlport), // ctrlport_if.slave
|
||||
.m_ctrlport(m_radio_regs_ctrlport_array) // ctrlport_if.master[(NUM_SLAVES-1):0]
|
||||
);
|
||||
|
||||
ctrlport_if m_radio_regs_ctrlport_lcl(.clk(s_ctrlport.clk), .rst(s_ctrlport.rst));
|
||||
ctrlport_if m_radio_sb_ctrlport(.clk(s_ctrlport.clk), .rst(s_ctrlport.rst));
|
||||
|
||||
assign m_radio_regs_ctrlport_lcl.req = m_radio_regs_ctrlport_array[0].req;
|
||||
assign m_radio_regs_ctrlport_array[0].resp = m_radio_regs_ctrlport_lcl.resp;
|
||||
assign m_radio_sb_ctrlport.req = m_radio_regs_ctrlport_array[1].req;
|
||||
assign m_radio_regs_ctrlport_array[1].resp = m_radio_sb_ctrlport.resp;
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//----------------------------------------------------------
|
||||
wire address_in_range = (m_radio_regs_ctrlport_lcl.req.addr >= BASE_ADDRESS) &&
|
||||
(m_radio_regs_ctrlport_lcl.req.addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
// Indicate the transaction is targeting the ATR registers. The upper boundary considers all
|
||||
// the addresses in the last ATR table.
|
||||
wire address_is_atr_wr = (m_radio_regs_ctrlport_lcl.req.addr >= BASE_ADDRESS + CH0_LED_ATR) &&
|
||||
(m_radio_regs_ctrlport_lcl.req.addr < BASE_ADDRESS + CH1_PATH_CTRL_ATR + 8);
|
||||
|
||||
always_ff @(posedge m_radio_regs_ctrlport_lcl.clk) begin
|
||||
// reset internal registers and responses
|
||||
if (m_radio_regs_ctrlport_lcl.rst) begin
|
||||
radio_adrv_reset <= '0;
|
||||
radio_test_enable <= '0;
|
||||
|
||||
m_radio_regs_ctrlport_lcl.resp.ack <= 1'b0;
|
||||
m_radio_regs_ctrlport_lcl.resp.data <= 'x;
|
||||
m_radio_regs_ctrlport_lcl.resp.status <= STS_OKAY;
|
||||
|
||||
end else begin
|
||||
|
||||
// write requests
|
||||
if (m_radio_regs_ctrlport_lcl.req.wr) begin
|
||||
// always issue an ack and no data
|
||||
m_radio_regs_ctrlport_lcl.resp.ack <= 1'b1;
|
||||
m_radio_regs_ctrlport_lcl.resp.data <= 'x;
|
||||
m_radio_regs_ctrlport_lcl.resp.status <= STS_OKAY;
|
||||
|
||||
case (m_radio_regs_ctrlport_lcl.req.addr)
|
||||
BASE_ADDRESS + MISC_OUTPUTS: begin
|
||||
radio_adrv_reset <= m_radio_regs_ctrlport_lcl.req.data[ADRV9032_RESET];
|
||||
radio_test_enable <= m_radio_regs_ctrlport_lcl.req.data[ADRV9032_TEST_EN];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
if (!address_is_atr_wr) begin
|
||||
m_radio_regs_ctrlport_lcl.resp.status <= STS_CMDERR;
|
||||
end
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
m_radio_regs_ctrlport_lcl.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (m_radio_regs_ctrlport_lcl.req.rd) begin
|
||||
// default assumption: valid request
|
||||
m_radio_regs_ctrlport_lcl.resp.ack <= 1'b1;
|
||||
m_radio_regs_ctrlport_lcl.resp.status <= STS_OKAY;
|
||||
m_radio_regs_ctrlport_lcl.resp.data <= '0;
|
||||
|
||||
case (m_radio_regs_ctrlport_lcl.req.addr)
|
||||
BASE_ADDRESS + MISC_OUTPUTS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[ADRV9032_RESET]
|
||||
<= radio_adrv_reset;
|
||||
m_radio_regs_ctrlport_lcl.resp.data[ADRV9032_TEST_EN]
|
||||
<= radio_test_enable;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + MISC_INPUTS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[ADRV_INTERRUPT_0]
|
||||
<= radio_ch0_adrv_int;
|
||||
m_radio_regs_ctrlport_lcl.resp.data[ADRV_INTERRUPT_1]
|
||||
<= radio_ch1_adrv_int;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH0_LED_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[LED_TX_GREEN]
|
||||
<= ch0_led_atr_rb[LED_TX_GREEN];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[LED_TX_RED]
|
||||
<= ch0_led_atr_rb[LED_TX_RED];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[LED_RX_GREEN]
|
||||
<= ch0_led_atr_rb[LED_RX_GREEN];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH1_LED_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[LED_TX_GREEN]
|
||||
<= ch1_led_atr_rb[LED_TX_GREEN];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[LED_TX_RED]
|
||||
<= ch1_led_atr_rb[LED_TX_RED];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[LED_RX_GREEN]
|
||||
<= ch1_led_atr_rb[LED_RX_GREEN];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH0_FP_GPIO_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[FP_DRIVE_VALUES_MSB : FP_DRIVE_VALUES]
|
||||
<= ch0_fp_gpio_atr_rb[FP_DRIVE_VALUES_MSB : FP_DRIVE_VALUES];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH1_FP_GPIO_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[FP_DRIVE_VALUES_MSB : FP_DRIVE_VALUES]
|
||||
<= ch1_fp_gpio_atr_rb[FP_DRIVE_VALUES_MSB : FP_DRIVE_VALUES];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH0_ADRV_GPIO_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[TRX_CTRL_3 : TRX_CTRL_0]
|
||||
<= ch0_adrv_gpio_atr_rb[TRX_CTRL_3 : TRX_CTRL_0];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[ADRV_GPIO_3 : ADRV_GPIO_0]
|
||||
<= ch0_adrv_gpio_atr_rb[ADRV_GPIO_3 : ADRV_GPIO_0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH1_ADRV_GPIO_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[TRX_CTRL_3 : TRX_CTRL_0]
|
||||
<= ch1_adrv_gpio_atr_rb[TRX_CTRL_3 : TRX_CTRL_0];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[ADRV_GPIO_3 : ADRV_GPIO_0]
|
||||
<= ch1_adrv_gpio_atr_rb[ADRV_GPIO_3 : ADRV_GPIO_0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH0_PATH_CTRL_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[CH_ENABLE_TXRX_TDR]
|
||||
<= ch0_path_ctrl_rb[CH_ENABLE_TXRX_TDR];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[CH_BYPASS_RX]
|
||||
<= ch0_path_ctrl_rb[CH_BYPASS_RX];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + CH1_PATH_CTRL_STATUS: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data[CH_ENABLE_TXRX_TDR]
|
||||
<= ch1_path_ctrl_rb[CH_ENABLE_TXRX_TDR];
|
||||
m_radio_regs_ctrlport_lcl.resp.data[CH_BYPASS_RX]
|
||||
<= ch1_path_ctrl_rb[CH_BYPASS_RX];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
m_radio_regs_ctrlport_lcl.resp.data <= '0;
|
||||
if (address_in_range) begin
|
||||
m_radio_regs_ctrlport_lcl.resp.status <= STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
m_radio_regs_ctrlport_lcl.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
m_radio_regs_ctrlport_lcl.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ATR register conditioning.
|
||||
// The ATR registers requires a settings bus interface, which is translated
|
||||
// to in this section.
|
||||
// To achieve this, we will filter the ctrlport interface within the register
|
||||
// address space containing ATR writes. Read operations in this address space
|
||||
// only monitor status signals and can be serviced with ctrlport.
|
||||
ctrlport_if radio_atr_if (
|
||||
.clk(s_ctrlport.clk),
|
||||
.rst(s_ctrlport.rst)
|
||||
);
|
||||
|
||||
// Create a window for the ctrlport interface to the ATR registers.
|
||||
|
||||
//vhook_e ctrlport_if_window radio_atr_reg_window
|
||||
//vhook_a BASE_ADDRESS BASE_ADDRESS+CH0_LED_ATR
|
||||
//vhook_a WINDOW_SIZE 'h80
|
||||
//vhook_a s_ctrlport m_radio_sb_ctrlport
|
||||
//vhook_a m_ctrlport radio_atr_if
|
||||
ctrlport_if_window #(
|
||||
.BASE_ADDRESS(BASE_ADDRESS+CH0_LED_ATR), //int:=0
|
||||
.WINDOW_SIZE ('h80) //int:=32
|
||||
) radio_atr_reg_window (
|
||||
.s_ctrlport(m_radio_sb_ctrlport), // ctrlport_if.slave
|
||||
.m_ctrlport(radio_atr_if) // ctrlport_if.master
|
||||
);
|
||||
|
||||
wire radio_sb_stb = radio_atr_if.req.wr;
|
||||
wire [7:0] radio_sb_addr = radio_atr_if.req.addr[7:0];
|
||||
wire [31:0] radio_sb_data = radio_atr_if.req.data;
|
||||
|
||||
// Reads are handled by the status registers
|
||||
assign radio_atr_if.resp.data = '0;
|
||||
assign radio_atr_if.resp.status = STS_OKAY;
|
||||
|
||||
// ATR Register Implementation
|
||||
//----------------------------------------------------------------
|
||||
|
||||
// CH0 LED ATR
|
||||
logic [7:0] ch0_led_atr_out;
|
||||
|
||||
//vhook_e gpio_atr ch0_led_atr_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH0_LED_ATR
|
||||
//vhook_a WIDTH 8
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[0]
|
||||
//vhook_a tx tx_running[0]
|
||||
//vhook_a gpio_in '0
|
||||
//vhook_a gpio_out ch0_led_atr_out
|
||||
//vhook_a gpio_ddr {/*unused, assumed output only*/}
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch0_led_atr_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH0_LED_ATR), //integer:=0
|
||||
.WIDTH (8), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch0_led_atr_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[0]), //input wire
|
||||
.tx (tx_running[0]), //input wire
|
||||
.gpio_in ('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_out (ch0_led_atr_out), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr ({/*unused, assumed output only*/}), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch0_led_atr_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
assign radio_led_tx_green[0] = ch0_led_atr_out[LED_TX_GREEN];
|
||||
assign radio_led_tx_red[0] = ch0_led_atr_out[LED_TX_RED];
|
||||
assign radio_led_rx_green[0] = ch0_led_atr_out[LED_RX_GREEN];
|
||||
|
||||
//CH1 LED ATR
|
||||
logic [7:0] ch1_led_atr_out;
|
||||
|
||||
//vhook_e gpio_atr ch1_led_atr_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH1_LED_ATR
|
||||
//vhook_a WIDTH 8
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[1]
|
||||
//vhook_a tx tx_running[1]
|
||||
//vhook_a gpio_in '0
|
||||
//vhook_a gpio_out ch1_led_atr_out
|
||||
//vhook_a gpio_ddr {/*unused, assumed output only*/}
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch1_led_atr_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH1_LED_ATR), //integer:=0
|
||||
.WIDTH (8), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch1_led_atr_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[1]), //input wire
|
||||
.tx (tx_running[1]), //input wire
|
||||
.gpio_in ('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_out (ch1_led_atr_out), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr ({/*unused, assumed output only*/}), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch1_led_atr_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
assign radio_led_tx_green[1] = ch1_led_atr_out[LED_TX_GREEN];
|
||||
assign radio_led_tx_red[1] = ch1_led_atr_out[LED_TX_RED];
|
||||
assign radio_led_rx_green[1] = ch1_led_atr_out[LED_RX_GREEN];
|
||||
|
||||
// CH0 FP GPIO ATR
|
||||
|
||||
//vhook_e gpio_atr ch0_fp_gpio_atr_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH0_FP_GPIO_ATR
|
||||
//vhook_a WIDTH 10
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[0]
|
||||
//vhook_a tx tx_running[0]
|
||||
//vhook_a gpio_in radio_fp_gpio_in
|
||||
//vhook_a gpio_out radio_ch0_fp_gpio_out
|
||||
//vhook_a gpio_ddr radio_ch0_fp_gpio_dir
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch0_fp_gpio_atr_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH0_FP_GPIO_ATR), //integer:=0
|
||||
.WIDTH (10), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch0_fp_gpio_atr_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[0]), //input wire
|
||||
.tx (tx_running[0]), //input wire
|
||||
.gpio_in (radio_fp_gpio_in), //input wire[(WIDTH-1):0]
|
||||
.gpio_out (radio_ch0_fp_gpio_out), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr (radio_ch0_fp_gpio_dir), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch0_fp_gpio_atr_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
// CH1 FP GPIO ATR
|
||||
|
||||
//vhook_e gpio_atr ch1_fp_gpio_atr_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH1_FP_GPIO_ATR
|
||||
//vhook_a WIDTH 10
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[1]
|
||||
//vhook_a tx tx_running[1]
|
||||
//vhook_a gpio_in radio_fp_gpio_in
|
||||
//vhook_a gpio_out radio_ch1_fp_gpio_out
|
||||
//vhook_a gpio_ddr radio_ch1_fp_gpio_dir
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch1_fp_gpio_atr_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH1_FP_GPIO_ATR), //integer:=0
|
||||
.WIDTH (10), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch1_fp_gpio_atr_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[1]), //input wire
|
||||
.tx (tx_running[1]), //input wire
|
||||
.gpio_in (radio_fp_gpio_in), //input wire[(WIDTH-1):0]
|
||||
.gpio_out (radio_ch1_fp_gpio_out), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr (radio_ch1_fp_gpio_dir), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch1_fp_gpio_atr_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
//CH0 ADRV GPIO ATR
|
||||
logic [7:0] ch0_adrv_gpio_atr_ddr;
|
||||
|
||||
//vhook_e gpio_atr ch0_adrv_gpio_atr_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH0_ADRV_GPIO_ATR
|
||||
//vhook_a WIDTH 8
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[0]
|
||||
//vhook_a tx tx_running[0]
|
||||
//vhook_a gpio_in {radio_ch0_adrv_gpio_in[3:0], ch0_adrv_gpio_atr_rb[3:0]}
|
||||
//vhook_a gpio_out {radio_ch0_adrv_gpio_out[3:0], radio_ch0_adrv_trx_out[3:0]}
|
||||
//vhook_a gpio_ddr ch0_adrv_gpio_atr_ddr
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch0_adrv_gpio_atr_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH0_ADRV_GPIO_ATR), //integer:=0
|
||||
.WIDTH (8), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch0_adrv_gpio_atr_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[0]), //input wire
|
||||
.tx (tx_running[0]), //input wire
|
||||
.gpio_in ({radio_ch0_adrv_gpio_in[3:0], ch0_adrv_gpio_atr_rb[3:0]}), //input wire[(WIDTH-1):0]
|
||||
.gpio_out ({radio_ch0_adrv_gpio_out[3:0], radio_ch0_adrv_trx_out[3:0]}), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr (ch0_adrv_gpio_atr_ddr), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch0_adrv_gpio_atr_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
assign radio_ch0_adrv_gpio_dir = ch0_adrv_gpio_atr_ddr[ADRV_GPIO_3:ADRV_GPIO_0];
|
||||
|
||||
|
||||
//CH1 ADRV GPIO ATR
|
||||
logic [7:0] ch1_adrv_gpio_atr_ddr;
|
||||
|
||||
//vhook_e gpio_atr ch1_adrv_gpio_atr_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH1_ADRV_GPIO_ATR
|
||||
//vhook_a WIDTH 8
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[1]
|
||||
//vhook_a tx tx_running[1]
|
||||
//vhook_a gpio_in {radio_ch1_adrv_gpio_in[3:0], ch1_adrv_gpio_atr_rb[3:0]}
|
||||
//vhook_a gpio_out {radio_ch1_adrv_gpio_out[3:0], radio_ch1_adrv_trx_out[3:0]}
|
||||
//vhook_a gpio_ddr ch1_adrv_gpio_atr_ddr
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch1_adrv_gpio_atr_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH1_ADRV_GPIO_ATR), //integer:=0
|
||||
.WIDTH (8), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch1_adrv_gpio_atr_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[1]), //input wire
|
||||
.tx (tx_running[1]), //input wire
|
||||
.gpio_in ({radio_ch1_adrv_gpio_in[3:0], ch1_adrv_gpio_atr_rb[3:0]}), //input wire[(WIDTH-1):0]
|
||||
.gpio_out ({radio_ch1_adrv_gpio_out[3:0], radio_ch1_adrv_trx_out[3:0]}), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr (ch1_adrv_gpio_atr_ddr), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch1_adrv_gpio_atr_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
assign radio_ch1_adrv_gpio_dir = ch1_adrv_gpio_atr_ddr[ADRV_GPIO_3:ADRV_GPIO_0];
|
||||
|
||||
|
||||
//CH0 Path Control ATR
|
||||
|
||||
//vhook_e gpio_atr ch0_path_ctrl_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH0_PATH_CTRL_ATR
|
||||
//vhook_a WIDTH 2
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[0]
|
||||
//vhook_a tx tx_running[0]
|
||||
//vhook_a gpio_in '0
|
||||
//vhook_a gpio_out {radio_rx_bypass[0], radio_enable_tdr[0]}
|
||||
//vhook_a gpio_ddr {/*unused, assumed output only*/}
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch0_path_ctrl_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH0_PATH_CTRL_ATR), //integer:=0
|
||||
.WIDTH (2), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch0_path_ctrl_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[0]), //input wire
|
||||
.tx (tx_running[0]), //input wire
|
||||
.gpio_in ('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_out ({radio_rx_bypass[0], radio_enable_tdr[0]}), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr ({/*unused, assumed output only*/}), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch0_path_ctrl_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
//CH1 Path Control ATR
|
||||
|
||||
//vhook_e gpio_atr ch1_path_ctrl_i
|
||||
//vhook_a BASE BASE_ADDRESS+CH1_PATH_CTRL_ATR
|
||||
//vhook_a WIDTH 2
|
||||
//vhook_a FAB_CTRL_EN '0
|
||||
//vhook_a DEFAULT_DDR '1
|
||||
//vhook_a DEFAULT_IDLE '0
|
||||
//vhook_a clk s_ctrlport.clk
|
||||
//vhook_a reset s_ctrlport.rst
|
||||
//vhook_a set_stb radio_sb_stb
|
||||
//vhook_a set_addr radio_sb_addr
|
||||
//vhook_a set_data radio_sb_data
|
||||
//vhook_a rx rx_running[1]
|
||||
//vhook_a tx tx_running[1]
|
||||
//vhook_a gpio_in '0
|
||||
//vhook_a gpio_out {radio_rx_bypass[1], radio_enable_tdr[1]}
|
||||
//vhook_a gpio_ddr {/*unused, assumed output only*/}
|
||||
//vhook_a gpio_out_fab '0
|
||||
//vhook_a gpio_sw_rb ch1_path_ctrl_rb
|
||||
gpio_atr #(
|
||||
.BASE (BASE_ADDRESS+CH1_PATH_CTRL_ATR), //integer:=0
|
||||
.WIDTH (2), //integer:=32
|
||||
.FAB_CTRL_EN ('0), //integer:=0
|
||||
.DEFAULT_DDR ('1), //integer:=0
|
||||
.DEFAULT_IDLE('0) //integer:=0
|
||||
) ch1_path_ctrl_i (
|
||||
.clk (s_ctrlport.clk), //input wire
|
||||
.reset (s_ctrlport.rst), //input wire
|
||||
.set_stb (radio_sb_stb), //input wire
|
||||
.set_addr (radio_sb_addr), //input wire[7:0]
|
||||
.set_data (radio_sb_data), //input wire[31:0]
|
||||
.rx (rx_running[1]), //input wire
|
||||
.tx (tx_running[1]), //input wire
|
||||
.gpio_in ('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_out ({radio_rx_bypass[1], radio_enable_tdr[1]}), //output reg[(WIDTH-1):0]
|
||||
.gpio_ddr ({/*unused, assumed output only*/}), //output reg[(WIDTH-1):0]
|
||||
.gpio_out_fab('0), //input wire[(WIDTH-1):0]
|
||||
.gpio_sw_rb (ch1_path_ctrl_rb) //output reg[(WIDTH-1):0]
|
||||
);
|
||||
|
||||
|
||||
endmodule : radio_control_regs
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//
|
||||
//<regmap name="RADIO_CONTROL_REGMAP" readablestrobes="false" generateverilog="true" generatesv="false" ettusguidelines="true">
|
||||
// <group name="RADIO_CONTROL_REGS">
|
||||
// <register name="MISC_OUTPUTS" size="32" offset="0x0" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// This register contains the miscellaneous control for the analog path.
|
||||
// </info>
|
||||
// <bitfield name="ADRV9032_RESET" range="0">
|
||||
// <info>
|
||||
// Controls reset line to ADRV9032 chip.
|
||||
// 0 = reset, 1 = normal operation
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADRV9032_TEST_EN" range="1">
|
||||
// <info>
|
||||
// Controls test mode for ADRV9032 chip.
|
||||
// 0 = normal operation, 1 = test mode
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="MISC_INPUTS" size="32" offset="0x4" attributes="Readable">
|
||||
// <info>
|
||||
// Status register for miscellaneous inputs.
|
||||
// </info>
|
||||
// <bitfield name="ADRV_INTERRUPT_0" range="0">
|
||||
// <info>
|
||||
// Status of ADRV9032 interrupt line 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADRV_INTERRUPT_1" range="1">
|
||||
// <info>
|
||||
// Status of ADRV9032 interrupt line 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <regtype name="CH_LED_ATR" size="32">
|
||||
// <info>
|
||||
// Controls one channels LED values given the channel's ATR state. This is the base offset of
|
||||
// 6 different registers:
|
||||
// BASE+0 DEFAULT_IDLE
|
||||
// BASE+1 RX_ACTIVE
|
||||
// BASE+2 TX_ACTIVE
|
||||
// BASE+3 FDX
|
||||
// BASE+4 DDR
|
||||
// BASE+5 ATR_DISABLED
|
||||
// </info>
|
||||
// <bitfield name="LED_TX_GREEN" range="0">
|
||||
// <info>
|
||||
// Controls the TX green LED state.
|
||||
// 0 = off, 1 = on
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LED_TX_RED" range="1">
|
||||
// <info>
|
||||
// Controls the TX red LED state.
|
||||
// 0 = off, 1 = on
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LED_RX_GREEN" range="4">
|
||||
// <info>
|
||||
// Controls the RX green LED state.
|
||||
// 0 = off, 1 = on
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
// <register name="CH0_LED_ATR" typename="CH_LED_ATR" offset="0x10" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the LEDs state for channel 0 given the channel's ATR state.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH0_LED_STATUS" typename="CH_LED_ATR" offset="0x18" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the LEDs state for channel 0.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_LED_ATR" typename="CH_LED_ATR" offset="0x20" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the LEDs state for channel 1 given the channel's ATR state.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_LED_STATUS" typename="CH_LED_ATR" offset="0x28" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the LEDs state for channel 1.
|
||||
// </info>
|
||||
// </register>
|
||||
// <regtype name="CH_FP_GPIO_ATR" size="32">
|
||||
// <info>
|
||||
// Controls one channel's HDMI GPIO drive values based on the channel's ATR state.
|
||||
// This is the base offset of 6 different registers:
|
||||
// BASE+0 DEFAULT_IDLE
|
||||
// BASE+1 RX_ACTIVE
|
||||
// BASE+2 TX_ACTIVE
|
||||
// BASE+3 FDX
|
||||
// BASE+4 DDR
|
||||
// BASE+5 ATR_DISABLED
|
||||
// </info>
|
||||
// <bitfield name="FP_DRIVE_VALUES" range="9..0">
|
||||
// <info>
|
||||
// Controls the HDMI GPIO drive values for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
// <register name="CH0_FP_GPIO_ATR" typename="CH_FP_GPIO_ATR" offset="0x30" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the HDMI GPIO drive values for channel 0 based on the channel's ATR state
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH0_FP_GPIO_STATUS" typename="CH_FP_GPIO_ATR" offset="0x38" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the HDMI GPIO drive values for channel 0.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_FP_GPIO_ATR" typename="CH_FP_GPIO_ATR" offset="0x40" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the HDMI GPIO drive values for channel 1 based on the channel's ATR state
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_FP_GPIO_STATUS" typename="CH_FP_GPIO_ATR" offset="0x48" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the HDMI GPIO drive values for channel 1.
|
||||
// </info>
|
||||
// </register>
|
||||
// <regtype name="CH_ADRV_GPIO_ATR" size="32">
|
||||
// <info>
|
||||
// Controls one channel's ADRV TRX drive values based on the channel's ATR state.
|
||||
// This is the base offset of 6 different registers:
|
||||
// BASE+0 DEFAULT_IDLE
|
||||
// BASE+1 RX_ACTIVE
|
||||
// BASE+2 TX_ACTIVE
|
||||
// BASE+3 FDX
|
||||
// BASE+4 DDR
|
||||
// BASE+5 ATR_DISABLED
|
||||
// </info>
|
||||
// <bitfield name="TRX_CTRL_0" range="0">
|
||||
// <info>
|
||||
// Controls first ADRV TRX line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TRX_CTRL_1" range="1">
|
||||
// <info>
|
||||
// Controls second ADRV TRX line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TRX_CTRL_2" range="2">
|
||||
// <info>
|
||||
// Controls third ADRV TRX line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TRX_CTRL_3" range="3">
|
||||
// <info>
|
||||
// Controls fourth ADRV TRX line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADRV_GPIO_0" range="4">
|
||||
// <info>
|
||||
// Controls first ADRV GPIO line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADRV_GPIO_1" range="5">
|
||||
// <info>
|
||||
// Controls second ADRV GPIO line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADRV_GPIO_2" range="6">
|
||||
// <info>
|
||||
// Controls third ADRV GPIO line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADRV_GPIO_3" range="7">
|
||||
// <info>
|
||||
// Controls fourth ADRV GPIO line for the channel.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
// <register name="CH0_ADRV_GPIO_ATR" typename="CH_ADRV_GPIO_ATR" offset="0x50" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the ADRV TRX GPIO drive values for channel 0 based on the channel
|
||||
// ATR state.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH0_ADRV_GPIO_STATUS" typename="CH_ADRV_GPIO_ATR" offset="0x58" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the ADRV TRX GPIO drive values for channel 0.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_ADRV_GPIO_ATR" typename="CH_ADRV_GPIO_ATR" offset="0x60" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the ADRV TRX GPIO drive values for channel 1 based on the channel
|
||||
// ATR state.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_ADRV_GPIO_STATUS" typename="CH_ADRV_GPIO_ATR" offset="0x68" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the ADRV TRX GPIO drive values for channel 1.
|
||||
// </info>
|
||||
// </register>
|
||||
// <regtype name="CH_PATH_CTRL_ATR" size="32">
|
||||
// <info>
|
||||
// Controls one channel's path control signals.
|
||||
// This is the base offset of 6 different registers:
|
||||
// BASE+0 DEFAULT_IDLE
|
||||
// BASE+1 RX_ACTIVE
|
||||
// BASE+2 TX_ACTIVE
|
||||
// BASE+3 FDX
|
||||
// BASE+4 DDR
|
||||
// BASE+5 ATR_DISABLED
|
||||
// </info>
|
||||
// <bitfield name="CH_ENABLE_TXRX_TDR" range="0">
|
||||
// <info>
|
||||
// Controls FE TDR switch.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CH_BYPASS_RX" range="1">
|
||||
// <info>
|
||||
// Controls RX bypass switch.
|
||||
// 1 = bypass, 0 = RX enabled
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
// <register name="CH0_PATH_CTRL_ATR" typename="CH_PATH_CTRL_ATR" offset="0x70" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the path control signals for channel 0 based on the channel's ATR state.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH0_PATH_CTRL_STATUS" typename="CH_PATH_CTRL_ATR" offset="0x78" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the path control signals for channel 0.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_PATH_CTRL_ATR" typename="CH_PATH_CTRL_ATR" offset="0x80" attributes="Writable">
|
||||
// <info>
|
||||
// Controls the path control signals for channel 1 based on the channel's ATR state.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CH1_PATH_CTRL_STATUS" typename="CH_PATH_CTRL_ATR" offset="0x88" attributes="Readable">
|
||||
// <info>
|
||||
// Reads the path control signals for channel 1.
|
||||
// </info>
|
||||
// </register>
|
||||
// </group>
|
||||
// </regmap>
|
||||
//
|
||||
//XmlParse xml_off
|
||||
8
fpga/usrp3/top/b300/dev_config.json
Normal file
8
fpga/usrp3/top/b300/dev_config.json
Normal file
@ -0,0 +1,8 @@
|
||||
{
|
||||
"warning": { "ignore": ["."]},
|
||||
"critical warning": {
|
||||
"ignore": [
|
||||
"tempmon.v' already exists"
|
||||
]
|
||||
}
|
||||
}
|
||||
7150
fpga/usrp3/top/b300/doc/B310_FPGA.htm
Normal file
7150
fpga/usrp3/top/b300/doc/B310_FPGA.htm
Normal file
File diff suppressed because it is too large
Load Diff
46
fpga/usrp3/top/b300/ip/Makefile.inc
Normal file
46
fpga/usrp3/top/b300/ip/Makefile.inc
Normal file
@ -0,0 +1,46 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
|
||||
include $(IP_DIR)/bus_clk_gen/Makefile.inc
|
||||
include $(IP_DIR)/ref_clk_pll/Makefile.inc
|
||||
include $(IP_DIR)/radio_clk_gen/Makefile.inc
|
||||
include $(IP_DIR)/axi_intercon_2x64_256_bd/Makefile.inc
|
||||
include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc
|
||||
include $(IP_DIR)/ddr3_32bit/Makefile.inc
|
||||
include $(IP_DIR)/fifo_short_2clk/Makefile.inc
|
||||
include $(IP_DIR)/fifo_32bit_4k/Makefile.inc
|
||||
|
||||
IP_XCI_SRCS = \
|
||||
$(IP_BUS_CLK_GEN_SRCS) \
|
||||
$(IP_REF_CLK_PLL_SRCS) \
|
||||
$(IP_RADIO_CLK_GEN_SRCS) \
|
||||
$(IP_FIFO_4K_2CLK_SRCS) \
|
||||
$(IP_FIFO_SHORT_2CLK_SRCS) \
|
||||
$(IP_DDR3_32BIT_SRCS) \
|
||||
$(IP_FIFO_32BIT_4K_SRCS)
|
||||
|
||||
BD_SRCS = \
|
||||
$(IP_AXI_INTERCON_2X64_256_BD_SRCS) \
|
||||
$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \
|
||||
|
||||
IP_SYNTH_OUTPUTS = \
|
||||
$(IP_BUS_CLK_GEN_OUTS) \
|
||||
$(IP_REF_CLK_PLL_OUTS) \
|
||||
$(IP_RADIO_CLK_GEN_OUTS) \
|
||||
$(IP_FIFO_4K_2CLK_OUTS) \
|
||||
$(IP_FIFO_SHORT_2CLK_OUTS) \
|
||||
$(IP_DDR3_32BIT_OUTS) \
|
||||
$(IP_FIFO_32BIT_4K_OUTS)
|
||||
|
||||
BD_OUTPUTS = \
|
||||
$(IP_AXI_INTERCON_2X64_256_BD_OUTS) \
|
||||
$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \
|
||||
|
||||
ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS)
|
||||
|
||||
.PHONY: ip
|
||||
|
||||
36
fpga/usrp3/top/b300/ip/axi_intercon_2x64_256_bd/Makefile.inc
Normal file
36
fpga/usrp3/top/b300/ip/axi_intercon_2x64_256_bd/Makefile.inc
Normal file
@ -0,0 +1,36 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_AXI_INTERCON_2X64_256_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_intercon_2x64_256_bd/, \
|
||||
axi_intercon_2x64_256_bd.tcl \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCON_2X64_256_HDL_SRCS =
|
||||
|
||||
IP_AXI_INTERCON_2X64_256_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \
|
||||
axi_intercon_2x64_256_bd.tcl \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCON_2X64_256_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \
|
||||
axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd \
|
||||
)
|
||||
|
||||
BD_AXI_INTERCON_2X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \
|
||||
axi_intercon_2x64_256_bd.bd.out \
|
||||
axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_ooc.xdc \
|
||||
axi_intercon_2x64_256_bd/synth/axi_intercon_2x64_256_bd.v \
|
||||
)
|
||||
|
||||
EMPTY_IP_SRCS =
|
||||
|
||||
.INTERMEDIATE: IP_AXI_INTERCON_2X64_256_BD_TRGT
|
||||
$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(BD_AXI_INTERCON_2X64_256_BD_OUTS) $(IP_AXI_INTERCON_2X64_256_BDTCL_SRCS): IP_AXI_INTERCON_2X64_256_BD_TRGT
|
||||
@:
|
||||
|
||||
IP_AXI_INTERCON_2X64_256_BD_TRGT: $(IP_AXI_INTERCON_2X64_256_ORIG_SRCS)
|
||||
$(call BUILD_VIVADO_BDTCL,axi_intercon_2x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_AXI_INTERCON_2X64_256_HDL_SRCS),)
|
||||
@ -0,0 +1,418 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: axi_intercon_2x64_256_bd
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source axi_intercon_2x64_256_bd_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7k325tfbg676-1
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name axi_intercon_2x64_256_bd
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_register_slice:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:axi_crossbar:2.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
] $M00_AXI
|
||||
|
||||
set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
CONFIG.HAS_LOCK {1} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {1} \
|
||||
CONFIG.HAS_REGION {1} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.MAX_BURST_LENGTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {1} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $S00_AXI
|
||||
|
||||
set S01_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
CONFIG.HAS_LOCK {1} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {1} \
|
||||
CONFIG.HAS_REGION {1} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.MAX_BURST_LENGTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {1} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $S01_AXI
|
||||
|
||||
|
||||
# Create ports
|
||||
set M00_AXI_ACLK [ create_bd_port -dir I -type clk M00_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {M00_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_2x64_256_bd_M00_ACLK} \
|
||||
] $M00_AXI_ACLK
|
||||
set M00_AXI_ARESETN [ create_bd_port -dir I -type rst M00_AXI_ARESETN ]
|
||||
set S00_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 1000000000 S00_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {S00_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_2x64_256_bd_S00_ACLK} \
|
||||
] $S00_AXI_ACLK
|
||||
set S00_AXI_ARESETN [ create_bd_port -dir I -type rst S00_AXI_ARESETN ]
|
||||
set S01_AXI_ACLK [ create_bd_port -dir I -type clk S01_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {S01_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_2x64_256_bd_S01_ACLK} \
|
||||
] $S01_AXI_ACLK
|
||||
set S01_AXI_ARESETN [ create_bd_port -dir I -type rst S01_AXI_ARESETN ]
|
||||
|
||||
# Create instance: m00_rs, and set properties
|
||||
set m00_rs [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 m00_rs ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $m00_rs
|
||||
|
||||
# Create instance: s00_rs_0, and set properties
|
||||
set s00_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s00_rs_0
|
||||
|
||||
# Create instance: s00_rs_1, and set properties
|
||||
set s00_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s00_rs_1
|
||||
|
||||
# Create instance: s00_width_conv, and set properties
|
||||
set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s00_width_conv
|
||||
|
||||
# Create instance: s01_rs_0, and set properties
|
||||
set s01_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s01_rs_0
|
||||
|
||||
# Create instance: s01_rs_1, and set properties
|
||||
set s01_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s01_rs_1
|
||||
|
||||
# Create instance: s01_width_conv, and set properties
|
||||
set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s01_width_conv
|
||||
|
||||
# Create instance: xbar, and set properties
|
||||
set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.NUM_MI {1} \
|
||||
CONFIG.NUM_SI {2} \
|
||||
CONFIG.S01_BASE_ID {0x00000001} \
|
||||
CONFIG.S02_BASE_ID {0x00000002} \
|
||||
CONFIG.S03_BASE_ID {0x00000003} \
|
||||
CONFIG.S04_BASE_ID {0x00000004} \
|
||||
CONFIG.S05_BASE_ID {0x00000005} \
|
||||
CONFIG.S06_BASE_ID {0x00000006} \
|
||||
CONFIG.S07_BASE_ID {0x00000007} \
|
||||
CONFIG.S08_BASE_ID {0x00000008} \
|
||||
CONFIG.S09_BASE_ID {0x00000009} \
|
||||
CONFIG.S10_BASE_ID {0x0000000a} \
|
||||
CONFIG.S11_BASE_ID {0x0000000b} \
|
||||
CONFIG.S12_BASE_ID {0x0000000c} \
|
||||
CONFIG.S13_BASE_ID {0x0000000d} \
|
||||
CONFIG.S14_BASE_ID {0x0000000e} \
|
||||
CONFIG.S15_BASE_ID {0x0000000f} \
|
||||
CONFIG.STRATEGY {2} \
|
||||
] $xbar
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_ports S01_AXI] [get_bd_intf_pins s01_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net m00_rs_M_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins m00_rs/M_AXI]
|
||||
connect_bd_intf_net -intf_net s00_rs_1_M_AXI [get_bd_intf_pins s00_rs_1/M_AXI] [get_bd_intf_pins xbar/S00_AXI]
|
||||
connect_bd_intf_net -intf_net s00_rs_M_AXI [get_bd_intf_pins s00_rs_0/M_AXI] [get_bd_intf_pins s00_width_conv/S_AXI]
|
||||
connect_bd_intf_net -intf_net s00_width_conv_M_AXI [get_bd_intf_pins s00_rs_1/S_AXI] [get_bd_intf_pins s00_width_conv/M_AXI]
|
||||
connect_bd_intf_net -intf_net s01_rs_1_M_AXI [get_bd_intf_pins s01_rs_1/M_AXI] [get_bd_intf_pins xbar/S01_AXI]
|
||||
connect_bd_intf_net -intf_net s01_rs_M_AXI [get_bd_intf_pins s01_rs_0/M_AXI] [get_bd_intf_pins s01_width_conv/S_AXI]
|
||||
connect_bd_intf_net -intf_net s01_width_conv_M_AXI [get_bd_intf_pins s01_rs_1/S_AXI] [get_bd_intf_pins s01_width_conv/M_AXI]
|
||||
connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_pins m00_rs/S_AXI] [get_bd_intf_pins xbar/M00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins m00_rs/aclk] [get_bd_pins s00_rs_1/aclk] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_rs_1/aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk]
|
||||
connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins m00_rs/aresetn] [get_bd_pins s00_rs_1/aresetn] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_rs_1/aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn]
|
||||
connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_rs_0/aclk] [get_bd_pins s00_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_rs_0/aresetn] [get_bd_pins s00_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_rs_0/aclk] [get_bd_pins s01_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_rs_0/aresetn] [get_bd_pins s01_width_conv/s_axi_aresetn]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
36
fpga/usrp3/top/b300/ip/axi_intercon_4x64_256_bd/Makefile.inc
Normal file
36
fpga/usrp3/top/b300/ip/axi_intercon_4x64_256_bd/Makefile.inc
Normal file
@ -0,0 +1,36 @@
|
||||
#
|
||||
# Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_AXI_INTERCON_4X64_256_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_intercon_4x64_256_bd/, \
|
||||
axi_intercon_4x64_256_bd.tcl \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCON_4X64_256_HDL_SRCS =
|
||||
|
||||
IP_AXI_INTERCON_4X64_256_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \
|
||||
axi_intercon_4x64_256_bd.tcl \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCON_4X64_256_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \
|
||||
axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \
|
||||
)
|
||||
|
||||
BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \
|
||||
axi_intercon_4x64_256_bd.bd.out \
|
||||
axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_ooc.xdc \
|
||||
axi_intercon_4x64_256_bd/synth/axi_intercon_4x64_256_bd.v \
|
||||
)
|
||||
|
||||
EMPTY_IP_SRCS =
|
||||
|
||||
.INTERMEDIATE: IP_AXI_INTERCON_4X64_256_BD_TRGT
|
||||
$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(BD_AXI_INTERCON_4X64_256_BD_OUTS) $(IP_AXI_INTERCON_4X64_256_BDTCL_SRCS): IP_AXI_INTERCON_4X64_256_BD_TRGT
|
||||
@:
|
||||
|
||||
IP_AXI_INTERCON_4X64_256_BD_TRGT: $(IP_AXI_INTERCON_4X64_256_ORIG_SRCS)
|
||||
$(call BUILD_VIVADO_BDTCL,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_AXI_INTERCON_4X64_256_HDL_SRCS),)
|
||||
@ -0,0 +1,569 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: axi_intercon_4x64_256_bd
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source axi_intercon_4x64_256_bd_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7k325tfbg676-1
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name axi_intercon_4x64_256_bd
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_register_slice:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:axi_crossbar:2.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
] $M00_AXI
|
||||
|
||||
set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
CONFIG.HAS_LOCK {1} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {1} \
|
||||
CONFIG.HAS_REGION {1} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.MAX_BURST_LENGTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {1} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $S00_AXI
|
||||
|
||||
set S01_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
CONFIG.HAS_LOCK {1} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {1} \
|
||||
CONFIG.HAS_REGION {1} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.MAX_BURST_LENGTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {1} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $S01_AXI
|
||||
|
||||
set S02_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
CONFIG.HAS_LOCK {1} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {1} \
|
||||
CONFIG.HAS_REGION {1} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.MAX_BURST_LENGTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {1} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $S02_AXI
|
||||
|
||||
set S03_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S03_AXI ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
CONFIG.HAS_LOCK {1} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {1} \
|
||||
CONFIG.HAS_REGION {1} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.MAX_BURST_LENGTH {256} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {1} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $S03_AXI
|
||||
|
||||
|
||||
# Create ports
|
||||
set M00_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 1000000000 M00_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {M00_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_4x64_256_bd_M00_ACLK} \
|
||||
] $M00_AXI_ACLK
|
||||
set M00_AXI_ARESETN [ create_bd_port -dir I -type rst M00_AXI_ARESETN ]
|
||||
set S00_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 2000000000 S00_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {S00_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_4x64_256_bd_S00_ACLK} \
|
||||
] $S00_AXI_ACLK
|
||||
set S00_AXI_ARESETN [ create_bd_port -dir I -type rst S00_AXI_ARESETN ]
|
||||
set S01_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 2000000000 S01_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {S01_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_4x64_256_bd_S01_ACLK} \
|
||||
] $S01_AXI_ACLK
|
||||
set S01_AXI_ARESETN [ create_bd_port -dir I -type rst S01_AXI_ARESETN ]
|
||||
set S02_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 2000000000 S02_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {S02_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_4x64_256_bd_S02_ACLK} \
|
||||
] $S02_AXI_ACLK
|
||||
set S02_AXI_ARESETN [ create_bd_port -dir I -type rst S02_AXI_ARESETN ]
|
||||
set S03_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 2000000000 S03_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {S03_AXI_ARESETN} \
|
||||
CONFIG.CLK_DOMAIN {axi_intercon_4x64_256_bd_S03_ACLK} \
|
||||
] $S03_AXI_ACLK
|
||||
set S03_AXI_ARESETN [ create_bd_port -dir I -type rst S03_AXI_ARESETN ]
|
||||
|
||||
# Create instance: m00_rs, and set properties
|
||||
set m00_rs [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 m00_rs ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $m00_rs
|
||||
|
||||
# Create instance: s00_rs_0, and set properties
|
||||
set s00_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s00_rs_0
|
||||
|
||||
# Create instance: s00_rs_1, and set properties
|
||||
set s00_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s00_rs_1
|
||||
|
||||
# Create instance: s00_width_conv, and set properties
|
||||
set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s00_width_conv
|
||||
|
||||
# Create instance: s01_rs_0, and set properties
|
||||
set s01_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s01_rs_0
|
||||
|
||||
# Create instance: s01_rs_1, and set properties
|
||||
set s01_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s01_rs_1
|
||||
|
||||
# Create instance: s01_width_conv, and set properties
|
||||
set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s01_width_conv
|
||||
|
||||
# Create instance: s02_rs_0, and set properties
|
||||
set s02_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s02_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s02_rs_0
|
||||
|
||||
# Create instance: s02_rs_1, and set properties
|
||||
set s02_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s02_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s02_rs_1
|
||||
|
||||
# Create instance: s02_width_conv, and set properties
|
||||
set s02_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s02_width_conv ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s02_width_conv
|
||||
|
||||
# Create instance: s03_rs_0, and set properties
|
||||
set s03_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s03_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s03_rs_0
|
||||
|
||||
# Create instance: s03_rs_1, and set properties
|
||||
set s03_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s03_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s03_rs_1
|
||||
|
||||
# Create instance: s03_width_conv, and set properties
|
||||
set s03_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s03_width_conv ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s03_width_conv
|
||||
|
||||
# Create instance: xbar, and set properties
|
||||
set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.ID_WIDTH {2} \
|
||||
CONFIG.NUM_MI {1} \
|
||||
CONFIG.NUM_SI {4} \
|
||||
CONFIG.S01_BASE_ID {0x00000001} \
|
||||
CONFIG.S02_BASE_ID {0x00000002} \
|
||||
CONFIG.S03_BASE_ID {0x00000003} \
|
||||
CONFIG.S04_BASE_ID {0x00000004} \
|
||||
CONFIG.S05_BASE_ID {0x00000005} \
|
||||
CONFIG.S06_BASE_ID {0x00000006} \
|
||||
CONFIG.S07_BASE_ID {0x00000007} \
|
||||
CONFIG.S08_BASE_ID {0x00000008} \
|
||||
CONFIG.S09_BASE_ID {0x00000009} \
|
||||
CONFIG.S10_BASE_ID {0x0000000a} \
|
||||
CONFIG.S11_BASE_ID {0x0000000b} \
|
||||
CONFIG.S12_BASE_ID {0x0000000c} \
|
||||
CONFIG.S13_BASE_ID {0x0000000d} \
|
||||
CONFIG.S14_BASE_ID {0x0000000e} \
|
||||
CONFIG.S15_BASE_ID {0x0000000f} \
|
||||
CONFIG.STRATEGY {2} \
|
||||
] $xbar
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_ports S01_AXI] [get_bd_intf_pins s01_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S02_AXI_1 [get_bd_intf_ports S02_AXI] [get_bd_intf_pins s02_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S03_AXI_1 [get_bd_intf_ports S03_AXI] [get_bd_intf_pins s03_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net m00_rs_M_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins m00_rs/M_AXI]
|
||||
connect_bd_intf_net -intf_net s00_rs_1_M_AXI [get_bd_intf_pins s00_rs_1/M_AXI] [get_bd_intf_pins xbar/S00_AXI]
|
||||
connect_bd_intf_net -intf_net s00_rs_M_AXI [get_bd_intf_pins s00_rs_0/M_AXI] [get_bd_intf_pins s00_width_conv/S_AXI]
|
||||
connect_bd_intf_net -intf_net s00_width_conv_M_AXI [get_bd_intf_pins s00_rs_1/S_AXI] [get_bd_intf_pins s00_width_conv/M_AXI]
|
||||
connect_bd_intf_net -intf_net s01_rs_1_M_AXI [get_bd_intf_pins s01_rs_1/M_AXI] [get_bd_intf_pins xbar/S01_AXI]
|
||||
connect_bd_intf_net -intf_net s01_rs_M_AXI [get_bd_intf_pins s01_rs_0/M_AXI] [get_bd_intf_pins s01_width_conv/S_AXI]
|
||||
connect_bd_intf_net -intf_net s01_width_conv_M_AXI [get_bd_intf_pins s01_rs_1/S_AXI] [get_bd_intf_pins s01_width_conv/M_AXI]
|
||||
connect_bd_intf_net -intf_net s02_rs_1_M_AXI [get_bd_intf_pins s02_rs_1/M_AXI] [get_bd_intf_pins xbar/S02_AXI]
|
||||
connect_bd_intf_net -intf_net s02_rs_M_AXI [get_bd_intf_pins s02_rs_0/M_AXI] [get_bd_intf_pins s02_width_conv/S_AXI]
|
||||
connect_bd_intf_net -intf_net s02_width_conv_M_AXI [get_bd_intf_pins s02_rs_1/S_AXI] [get_bd_intf_pins s02_width_conv/M_AXI]
|
||||
connect_bd_intf_net -intf_net s03_rs_1_M_AXI [get_bd_intf_pins s03_rs_1/M_AXI] [get_bd_intf_pins xbar/S03_AXI]
|
||||
connect_bd_intf_net -intf_net s03_rs_M_AXI [get_bd_intf_pins s03_rs_0/M_AXI] [get_bd_intf_pins s03_width_conv/S_AXI]
|
||||
connect_bd_intf_net -intf_net s03_width_conv_M_AXI [get_bd_intf_pins s03_rs_1/S_AXI] [get_bd_intf_pins s03_width_conv/M_AXI]
|
||||
connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_pins m00_rs/S_AXI] [get_bd_intf_pins xbar/M00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins m00_rs/aclk] [get_bd_pins s00_rs_1/aclk] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_rs_1/aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins s02_rs_1/aclk] [get_bd_pins s02_width_conv/m_axi_aclk] [get_bd_pins s03_rs_1/aclk] [get_bd_pins s03_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk]
|
||||
connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins m00_rs/aresetn] [get_bd_pins s00_rs_1/aresetn] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_rs_1/aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins s02_rs_1/aresetn] [get_bd_pins s02_width_conv/m_axi_aresetn] [get_bd_pins s03_rs_1/aresetn] [get_bd_pins s03_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn]
|
||||
connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_rs_0/aclk] [get_bd_pins s00_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_rs_0/aresetn] [get_bd_pins s00_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_rs_0/aclk] [get_bd_pins s01_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_rs_0/aresetn] [get_bd_pins s01_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S02_AXI_ACLK_1 [get_bd_ports S02_AXI_ACLK] [get_bd_pins s02_rs_0/aclk] [get_bd_pins s02_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S02_AXI_ARESETN_1 [get_bd_ports S02_AXI_ARESETN] [get_bd_pins s02_rs_0/aresetn] [get_bd_pins s02_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S03_AXI_ACLK_1 [get_bd_ports S03_AXI_ACLK] [get_bd_pins s03_rs_0/aclk] [get_bd_pins s03_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S03_AXI_ARESETN_1 [get_bd_ports S03_AXI_ARESETN] [get_bd_pins s03_rs_0/aresetn] [get_bd_pins s03_width_conv/s_axi_aresetn]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S02_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S03_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
21
fpga/usrp3/top/b300/ip/bus_clk_gen/Makefile.inc
Normal file
21
fpga/usrp3/top/b300/ip/bus_clk_gen/Makefile.inc
Normal file
@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_BUS_CLK_GEN_SRCS = $(IP_BUILD_DIR)/bus_clk_gen/bus_clk_gen.xci
|
||||
|
||||
IP_BUS_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/bus_clk_gen/, \
|
||||
bus_clk_gen.xci.out \
|
||||
bus_clk_gen.v \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_BUS_CLK_GEN_TRGT
|
||||
$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS): IP_BUS_CLK_GEN_TRGT
|
||||
@:
|
||||
|
||||
IP_BUS_CLK_GEN_TRGT: $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci
|
||||
$(call BUILD_VIVADO_IP,bus_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
761
fpga/usrp3/top/b300/ip/bus_clk_gen/bus_clk_gen.xci
Normal file
761
fpga/usrp3/top/b300/ip/bus_clk_gen/bus_clk_gen.xci
Normal file
@ -0,0 +1,761 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bus_clk_gen</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">150.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">40.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">150.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">150</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">200.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">40.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">200.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">200</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">3.75</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.75</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">80.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_____________125____________0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">24.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">8.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1__150.00000______0.000______50.0______291.314____335.459</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">clk_out2__40.00000______0.000______50.0______376.602____335.459</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">clk_out3__200.00000______0.000______50.0______275.885____335.459</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1200.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">bus_clk_gen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">291.314</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">335.459</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">150</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">376.602</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">335.459</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">275.885</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">335.459</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">200</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bus_clk_gen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">24.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">8.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">4.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1_AR76780</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk_in1":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out1":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out2":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out3":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"locked":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"reset":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"clock_CLK_IN1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"use
|
||||
r","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"BOARD.ASSOCIATED_PARAM":[{"value":"CLK_IN1_BOARD_INTERFACE","value_src":"default","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format"
|
||||
:"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_IN1":[{"physical_name":"clk_in1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_pe
|
||||
rmission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT1":[{"physical_name":"clk_out1","physical_left":"0","physical_right":"0","logical_left":"0","logical_ri
|
||||
ght":"0","port_maps_used":"none"}]}},"clock_CLK_OUT2":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permissio
|
||||
n":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT2":[{"physical_name":"clk_out2","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT3":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"
|
||||
value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_
|
||||
type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT3":[{"physical_name":"clk_out3","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"RESET_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps
|
||||
":{"RST":[{"physical_name":"reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
32
fpga/usrp3/top/b300/ip/ddr3_32bit/Makefile.inc
Normal file
32
fpga/usrp3/top/b300/ip/ddr3_32bit/Makefile.inc
Normal file
@ -0,0 +1,32 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
# Including mig_7series_v4_2_tempmon.v will cause a critical warning, but leaving
|
||||
# it out will cause the build to fail.
|
||||
IP_DDR3_32BIT_SRCS = \
|
||||
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \
|
||||
|
||||
IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \
|
||||
ddr3_32bit.xci.out \
|
||||
ddr3_32bit/user_design/rtl/ddr3_32bit.v \
|
||||
ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \
|
||||
)
|
||||
|
||||
IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \
|
||||
ddr3_32bit/example_design/sim/ddr3_model.sv \
|
||||
ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_DDR3_32BIT_TRGT
|
||||
$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS): IP_DDR3_32BIT_TRGT
|
||||
@:
|
||||
|
||||
IP_DDR3_32BIT_TRGT: $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj
|
||||
cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds
|
||||
$(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj
|
||||
2920
fpga/usrp3/top/b300/ip/ddr3_32bit/ddr3_32bit.xci
Normal file
2920
fpga/usrp3/top/b300/ip/ddr3_32bit/ddr3_32bit.xci
Normal file
File diff suppressed because it is too large
Load Diff
186
fpga/usrp3/top/b300/ip/ddr3_32bit/mig_xc7k325tfbg676-1.prj
Normal file
186
fpga/usrp3/top/b300/ip/ddr3_32bit/mig_xc7k325tfbg676-1.prj
Normal file
@ -0,0 +1,186 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
|
||||
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
|
||||
<ModuleName>ddr3_32bit</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
|
||||
<XADC_En>Disabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7k325t-fbg676/-1</TargetFPGA>
|
||||
|
||||
<Version>4.2</Version>
|
||||
|
||||
<SystemClock>Single-Ended</SystemClock>
|
||||
|
||||
<ReferenceClock>No Buffer</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>0</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>0</dci_cascade>
|
||||
|
||||
<FPGADevice>
|
||||
<selected>7k/xc7k160t-fbg676</selected>
|
||||
<selected>7k/xc7k410t-fbg676</selected>
|
||||
</FPGADevice>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
|
||||
<TimePeriod>2500</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>100</InputClkFreq>
|
||||
<UIExtraClocks>1</UIExtraClocks>
|
||||
<MMCM_VCO>800</MMCM_VCO>
|
||||
<MMCMClkOut0> 4.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>4</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>32</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>TRUE</CustomPart>
|
||||
<NewPartName>MT41K256M16XX-125-HighTemp</NewPartName>
|
||||
<RowAddress>15</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V9" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA7" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y8" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V7" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W11" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AC13" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y7" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y10" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AF12" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA8" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB12" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V8" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AD13" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AD9" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y11" SLEW="FAST" VCCAUX_IO="" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AE12" SLEW="FAST" VCCAUX_IO="" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W8" SLEW="FAST" VCCAUX_IO="" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA9" SLEW="FAST" VCCAUX_IO="" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V11" SLEW="FAST" VCCAUX_IO="" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="W9" SLEW="FAST" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="W10" SLEW="FAST" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AE7" SLEW="FAST" VCCAUX_IO="" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AC12" SLEW="FAST" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AD4" SLEW="FAST" VCCAUX_IO="" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AC4" SLEW="FAST" VCCAUX_IO="" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dm[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dm[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AD1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AC3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AB6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="Y6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AA4" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="Y5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AB4" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AB2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[16]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="Y2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[17]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="Y1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[18]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="Y3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[19]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[20]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="V2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[21]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AA3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[22]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="V1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[23]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="V4" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[24]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="U6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[25]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="V3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[26]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="V6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[27]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="U2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[28]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="U7" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[29]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="U1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[30]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="U5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[31]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AE2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="AC6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AF4" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AB5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_n[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="W5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_n[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AF5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AA5" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AB1" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_p[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="W6" SLEW="FAST" VCCAUX_IO="" name="ddr3_dqs_p[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AD8" SLEW="FAST" VCCAUX_IO="" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AC8" SLEW="FAST" VCCAUX_IO="" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS15" PADName="AA2" SLEW="FAST" VCCAUX_IO="" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB9" SLEW="FAST" VCCAUX_IO="" name="ddr3_we_n"/>
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin Bank="33" PADName="AB11(MRCC_P)" name="sys_clk_i"/>
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5" tfaw="40" tras="35" trcd="13.75" trefi="3.9" trfc="260" trp="13.75" trrd="7.5" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">6</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/4</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
|
||||
</Project>
|
||||
21
fpga/usrp3/top/b300/ip/fifo_32bit_4k/Makefile.inc
Normal file
21
fpga/usrp3/top/b300/ip/fifo_32bit_4k/Makefile.inc
Normal file
@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_FIFO_32BIT_4K_SRCS = $(IP_BUILD_DIR)/fifo_32bit_4k/fifo_32bit_4k.xci
|
||||
|
||||
IP_FIFO_32BIT_4K_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_32bit_4k/, \
|
||||
fifo_32bit_4k.xci.out \
|
||||
synth/fifo_32bit_4k.vhd \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_FIFO_32BIT_4K_TRGT
|
||||
$(IP_FIFO_32BIT_4K_SRCS) $(IP_FIFO_32BIT_4K_OUTS): IP_FIFO_32BIT_4K_TRGT
|
||||
@:
|
||||
|
||||
IP_FIFO_32BIT_4K_TRGT: $(IP_DIR)/fifo_32bit_4k/fifo_32bit_4k.xci
|
||||
$(call BUILD_VIVADO_IP,fifo_32bit_4k,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
577
fpga/usrp3/top/b300/ip/fifo_32bit_4k/fifo_32bit_4k.xci
Normal file
577
fpga/usrp3/top/b300/ip/fifo_32bit_4k/fifo_32bit_4k.xci
Normal file
@ -0,0 +1,577 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>fifo_32bit_4k</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">4094</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">4093</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_32bit_4k</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">4094</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">4093</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1_AR76780_AR35790</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"data_count":[{"direction":"out","physical_left":"11","physical_right":"0","is_vector":"true"}],"din":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"dout":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"srst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"FIFO_READ":{"vlnv":"xilinx.com:interface:fifo_read:1.0","abstraction_type":"xilinx.com:interface:fifo_read_rtl:1.0","mode":"slave","parameters":{}
|
||||
,"port_maps":{"ALMOST_EMPTY":[{"physical_name":"almost_empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"EMPTY":[{"physical_name":"empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RD_DATA":[{"physical_name":"dout","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"RD_EN":[{"physical_name":"rd_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"FIFO_WRITE":{"vlnv":"xilinx.com:interface:fifo_write:1.0","abstraction_type":"xilinx.com:interface:fifo_write_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_FULL":[{"physical_name":"almost_full","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"FULL":[{"physical_name":"full","physical_left":"0","physical_right":"0","logical_left":"0
|
||||
","logical_right":"0","port_maps_used":"none"}],"WR_DATA":[{"physical_name":"din","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"WR_EN":[{"physical_name":"wr_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"core_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true
|
||||
,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
21
fpga/usrp3/top/b300/ip/fifo_4k_2clk/Makefile.inc
Normal file
21
fpga/usrp3/top/b300/ip/fifo_4k_2clk/Makefile.inc
Normal file
@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
|
||||
|
||||
IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
|
||||
fifo_4k_2clk.xci.out \
|
||||
synth/fifo_4k_2clk.vhd \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT
|
||||
$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS): IP_FIFO_4K_2CLK_TRGT
|
||||
@:
|
||||
|
||||
IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
|
||||
$(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
589
fpga/usrp3/top/b300/ip/fifo_4k_2clk/fifo_4k_2clk.xci
Normal file
589
fpga/usrp3/top/b300/ip/fifo_4k_2clk/fifo_4k_2clk.xci
Normal file
@ -0,0 +1,589 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>fifo_4k_2clk</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">72</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">72</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">511</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_4k_2clk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Disable_Timing_Violations" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"din":[{"direction":"in","physical_left":"71","physical_right":"0","is_vector":"true"}],"dout":[{"direction":"out","physical_left":"71","physical_right":"0","is_vector":"true"}],"empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_data_count":[{"direction":"out","physical_left":"9","physical_right":"0","is_vector":"true"}],"rd_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_data_count":[{"direction":"out","physical_left":"9","physical_right":"0","is_vector":"true"}],"wr_en":[{"direction":"in","physical_left":"0","physical_ri
|
||||
ght":"0","is_vector":"false"}]},"interfaces":{"FIFO_READ":{"vlnv":"xilinx.com:interface:fifo_read:1.0","abstraction_type":"xilinx.com:interface:fifo_read_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_EMPTY":[{"physical_name":"almost_empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"EMPTY":[{"physical_name":"empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RD_DATA":[{"physical_name":"dout","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"RD_EN":[{"physical_name":"rd_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"FIFO_WRITE":{"vlnv":"xilinx.com:interface:fifo_write:1.0","abstraction_type":"xilinx.com:interface:fifo_write_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_FULL":[{"physical_name":"almost_full","ph
|
||||
ysical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"FULL":[{"physical_name":"full","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WR_DATA":[{"physical_name":"din","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"WR_EN":[{"physical_name":"wr_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"read_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_infer
|
||||
red":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name"
|
||||
:"rd_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"write_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FR
|
||||
EQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"wr_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
21
fpga/usrp3/top/b300/ip/fifo_short_2clk/Makefile.inc
Normal file
21
fpga/usrp3/top/b300/ip/fifo_short_2clk/Makefile.inc
Normal file
@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci
|
||||
|
||||
IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \
|
||||
fifo_short_2clk.xci.out \
|
||||
synth/fifo_short_2clk.vhd \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT
|
||||
$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS): IP_FIFO_SHORT_2CLK_TRGT
|
||||
@:
|
||||
|
||||
IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci
|
||||
$(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
591
fpga/usrp3/top/b300/ip/fifo_short_2clk/fifo_short_2clk.xci
Normal file
591
fpga/usrp3/top/b300/ip/fifo_short_2clk/fifo_short_2clk.xci
Normal file
@ -0,0 +1,591 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>fifo_short_2clk</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">2</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_short_2clk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.synchronization_stages" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"din":[{"direction":"in","physical_left":"71","physical_right":"0","is_vector":"true"}],"dout":[{"direction":"out","physical_left":"71","physical_right":"0","is_vector":"true"}],"empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_data_count":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"rd_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_data_count":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"wr_en":[{"direction":"in","physical_left":"0","physical_ri
|
||||
ght":"0","is_vector":"false"}]},"interfaces":{"FIFO_READ":{"vlnv":"xilinx.com:interface:fifo_read:1.0","abstraction_type":"xilinx.com:interface:fifo_read_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_EMPTY":[{"physical_name":"almost_empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"EMPTY":[{"physical_name":"empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RD_DATA":[{"physical_name":"dout","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"RD_EN":[{"physical_name":"rd_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"FIFO_WRITE":{"vlnv":"xilinx.com:interface:fifo_write:1.0","abstraction_type":"xilinx.com:interface:fifo_write_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_FULL":[{"physical_name":"almost_full","ph
|
||||
ysical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"FULL":[{"physical_name":"full","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WR_DATA":[{"physical_name":"din","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"WR_EN":[{"physical_name":"wr_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"read_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_infer
|
||||
red":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name"
|
||||
:"rd_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"write_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FR
|
||||
EQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"wr_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
21
fpga/usrp3/top/b300/ip/radio_clk_gen/Makefile.inc
Normal file
21
fpga/usrp3/top/b300/ip/radio_clk_gen/Makefile.inc
Normal file
@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_RADIO_CLK_GEN_SRCS = $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xci
|
||||
|
||||
IP_RADIO_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/radio_clk_gen/, \
|
||||
radio_clk_gen.xci.out \
|
||||
radio_clk_gen.v \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_RADIO_CLK_GEN_TRGT
|
||||
$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS): IP_RADIO_CLK_GEN_TRGT
|
||||
@:
|
||||
|
||||
IP_RADIO_CLK_GEN_TRGT: $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci
|
||||
$(call BUILD_VIVADO_IP,radio_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
770
fpga/usrp3/top/b300/ip/radio_clk_gen/radio_clk_gen.xci
Normal file
770
fpga/usrp3/top/b300/ip/radio_clk_gen/radio_clk_gen.xci
Normal file
@ -0,0 +1,770 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>radio_clk_gen</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">125.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">40.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">125.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">125.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">166.66667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">40.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">40.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">125.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">166.66667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">166.66667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">125.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">3.125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.75</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">1.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">42.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_____________125____________0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1__125.00000______0.000______50.0______119.348_____96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">clk_out2__40.00000______0.000______50.0______150.675_____96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">clk_out3__166.66667______0.000______50.0______113.052_____96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">clk_out4__125.00000______0.000______50.0______119.348_____96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Differential_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">radio_clk_gen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">119.348</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">125.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">150.675</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">40.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">113.052</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">166.66667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">119.348</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">radio_clk_gen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Differential_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1_AR76780_AR35790</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk_in1_n":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_in1_p":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out1":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out2":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out3":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out4":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"locked":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"reset":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"CLK_IN1_D":{"vlnv":"xilinx.com:interface:diff_clock:1.0","abstraction_type":"xilinx.com:interface:diff_clock_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"CLK_IN1_BOARD_INTERFACE","val
|
||||
ue_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CAN_DEBUG":[{"value":"false","value_src":"default","value_permission":"user","resolve_type":"generated","format":"bool","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_N":[{"physical_name":"clk_in1_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CLK_P":[{"physical_name":"clk_in1_p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":
|
||||
"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_ty
|
||||
pe":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT1":[{"physical_name":"clk_out1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT2":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src
|
||||
":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT2":[{"physical_name":"clk_out2","physical_left":"0","physical_right":"0","logical_
|
||||
left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT3":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"defa
|
||||
ult","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT3":[{"physical_name":"clk_out3","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT4":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"
|
||||
ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permiss
|
||||
ion":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT4":[{"physical_name":"clk_out4","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"RESET_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_objec
|
||||
t":true}]},"port_maps":{"RST":[{"physical_name":"reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
21
fpga/usrp3/top/b300/ip/ref_clk_pll/Makefile.inc
Normal file
21
fpga/usrp3/top/b300/ip/ref_clk_pll/Makefile.inc
Normal file
@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_REF_CLK_PLL_SRCS = $(IP_BUILD_DIR)/ref_clk_pll/ref_clk_pll.xci
|
||||
|
||||
IP_REF_CLK_PLL_OUTS = $(addprefix $(IP_BUILD_DIR)/ref_clk_pll/, \
|
||||
ref_clk_pll.xci.out \
|
||||
ref_clk_pll.v \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_REF_CLK_PLL_TRGT
|
||||
$(IP_REF_CLK_PLL_SRCS) $(IP_REF_CLK_PLL_OUTS): IP_REF_CLK_PLL_TRGT
|
||||
@:
|
||||
|
||||
IP_REF_CLK_PLL_TRGT: $(IP_DIR)/ref_clk_pll/ref_clk_pll.xci
|
||||
$(call BUILD_VIVADO_IP,ref_clk_pll,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
744
fpga/usrp3/top/b300/ip/ref_clk_pll/ref_clk_pll.xci
Normal file
744
fpga/usrp3/top/b300/ip/ref_clk_pll/ref_clk_pll.xci
Normal file
@ -0,0 +1,744 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>ref_clk_pll</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">125.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">125.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">125.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">166.66667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.14285714285714285</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.14285714285714285</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.14285714285714285</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.14285714285714285</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.14285714285714285</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.14285714285714285</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">42.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_____________125____________0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">7.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">7.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1__125.00000______0.000______50.0______125.031____104.065</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ref_clk_pll</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">125.031</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">104.065</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">125.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">150.675</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">113.052</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">96.948</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">166.66667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ref_clk_pll</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1_AR76780_AR35790</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_SEL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk_in1":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"clk_out1":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"locked":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"reset":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"clock_CLK_IN1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"BOARD.ASSOCIATED_PARAM":[{"value":"CLK_IN1_BOARD_INTERFACE","value_src":"d
|
||||
efault","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","forma
|
||||
t":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_IN1":[{"physical_name":"clk_in1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock_CLK_OUT1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_
|
||||
permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_OUT1":[{"physical_name":"clk_out1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM
|
||||
":[{"value":"RESET_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
fpga/usrp3/top/b300/netlists/b310_g2x4_host_interface.edf
Normal file
BIN
fpga/usrp3/top/b300/netlists/b310_g2x4_host_interface.edf
Normal file
Binary file not shown.
73
fpga/usrp3/top/b300/netlists/b310_g2x4_host_interface.vhd
Normal file
73
fpga/usrp3/top/b300/netlists/b310_g2x4_host_interface.vhd
Normal file
@ -0,0 +1,73 @@
|
||||
--
|
||||
-- Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
--
|
||||
-- SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
--
|
||||
-- Module: b310_g2x4_host_interface
|
||||
--
|
||||
-- Description:
|
||||
-- Allows connection from B310 to the host system over PCIe.
|
||||
-- This module also implements DMA FIFOs for data transfer.
|
||||
-- Finally, this module provides register access for specific
|
||||
-- address windows within the BAR space.
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity b310_g2x4_host_interface is
|
||||
port (
|
||||
pcie_rx_p : in std_logic_vector(3 downto 0);
|
||||
pcie_rx_n : in std_logic_vector(3 downto 0);
|
||||
pcie_tx_p : out std_logic_vector(3 downto 0);
|
||||
pcie_tx_n : out std_logic_vector(3 downto 0);
|
||||
pcie_ref_clk_p : in std_logic;
|
||||
pcie_ref_clk_n : in std_logic;
|
||||
clk_40mhz : in std_logic;
|
||||
bus_clk : in std_logic;
|
||||
dma_clk : out std_logic;
|
||||
pcie_arst : in std_logic;
|
||||
bus_arst : out boolean;
|
||||
host_dma_rx_tdata : in std_logic_vector(639 downto 0);
|
||||
host_dma_rx_tready : out std_logic_vector(4 downto 0);
|
||||
host_dma_rx_tvalid : in std_logic_vector(4 downto 0);
|
||||
host_dma_tx_tdata : out std_logic_vector(639 downto 0);
|
||||
host_dma_tx_tready : in std_logic_vector(4 downto 0);
|
||||
host_dma_tx_tvalid : out std_logic_vector(4 downto 0);
|
||||
pcie_usr_ctrlport_req_wr : out std_logic;
|
||||
pcie_usr_ctrlport_req_rd : out std_logic;
|
||||
pcie_usr_ctrlport_req_addr : out std_logic_vector(19 downto 0);
|
||||
pcie_usr_ctrlport_req_port_id : out std_logic_vector(9 downto 0);
|
||||
pcie_usr_ctrlport_req_rem_epid : out std_logic_vector(15 downto 0);
|
||||
pcie_usr_ctrlport_req_rem_portid : out std_logic_vector(9 downto 0);
|
||||
pcie_usr_ctrlport_req_data : out std_logic_vector(31 downto 0);
|
||||
pcie_usr_ctrlport_req_byte_en : out std_logic_vector(3 downto 0);
|
||||
pcie_usr_ctrlport_req_has_time : out std_logic;
|
||||
pcie_usr_ctrlport_req_time : out std_logic_vector(63 downto 0);
|
||||
pcie_usr_ctrlport_resp_ack : in std_logic;
|
||||
pcie_usr_ctrlport_resp_status : in std_logic_vector(1 downto 0);
|
||||
pcie_usr_ctrlport_resp_data : in std_logic_vector(31 downto 0);
|
||||
cpld_int_report_in : out std_logic_vector(50 downto 0);
|
||||
cpld_int_report_out : in std_logic_vector(33 downto 0);
|
||||
core_ctrlport_req_wr : out std_logic;
|
||||
core_ctrlport_req_rd : out std_logic;
|
||||
core_ctrlport_req_addr : out std_logic_vector(19 downto 0);
|
||||
core_ctrlport_req_port_id : out std_logic_vector(9 downto 0);
|
||||
core_ctrlport_req_rem_epid : out std_logic_vector(15 downto 0);
|
||||
core_ctrlport_req_rem_portid : out std_logic_vector(9 downto 0);
|
||||
core_ctrlport_req_data : out std_logic_vector(31 downto 0);
|
||||
core_ctrlport_req_byte_en : out std_logic_vector(3 downto 0);
|
||||
core_ctrlport_req_has_time : out std_logic;
|
||||
core_ctrlport_req_time : out std_logic_vector(63 downto 0);
|
||||
core_ctrlport_resp_ack : in std_logic;
|
||||
core_ctrlport_resp_status : in std_logic_vector(1 downto 0);
|
||||
core_ctrlport_resp_data : in std_logic_vector(31 downto 0);
|
||||
auth_sda_in : in std_logic;
|
||||
auth_sda_out : out std_logic
|
||||
);
|
||||
end entity b310_g2x4_host_interface;
|
||||
|
||||
architecture RTL of b310_g2x4_host_interface is
|
||||
begin
|
||||
end architecture RTL;
|
||||
BIN
fpga/usrp3/top/b300/netlists/b310_jesd204b.edf
Normal file
BIN
fpga/usrp3/top/b300/netlists/b310_jesd204b.edf
Normal file
Binary file not shown.
64
fpga/usrp3/top/b300/netlists/b310_jesd204b.vhd
Normal file
64
fpga/usrp3/top/b300/netlists/b310_jesd204b.vhd
Normal file
@ -0,0 +1,64 @@
|
||||
--
|
||||
-- Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
--
|
||||
-- SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
--
|
||||
-- Module: b310_jesd204b
|
||||
--
|
||||
-- Description:
|
||||
-- This module implements the JESD204B interface for the B310.
|
||||
-- This includes the implementation of the physical layer of
|
||||
-- the interface via MGT control, as well as the link layer
|
||||
-- as specified by the JESD204B standard.
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity b310_jesd204b is
|
||||
port (
|
||||
bclk_rst : in std_logic;
|
||||
bus_clk : in std_logic;
|
||||
clk_40mhz : in std_logic;
|
||||
sample_clk_1x : in std_logic;
|
||||
sample_clk_2x : in std_logic;
|
||||
bclk_fpga_clocks_stable : in std_logic;
|
||||
jesd_ref_clk_p : in std_logic;
|
||||
jesd_ref_clk_n : in std_logic;
|
||||
bclk_jesd_ref_clk_present : out std_logic;
|
||||
lmk_sync : out std_logic;
|
||||
bclk_ctrlport_req_wr : in std_logic;
|
||||
bclk_ctrlport_req_rd : in std_logic;
|
||||
bclk_ctrlport_req_addr : in std_logic_vector(19 downto 0);
|
||||
bclk_ctrlport_req_port_id : in std_logic_vector(9 downto 0);
|
||||
bclk_ctrlport_req_rem_epid : in std_logic_vector(15 downto 0);
|
||||
bclk_ctrlport_req_rem_portid : in std_logic_vector(9 downto 0);
|
||||
bclk_ctrlport_req_data : in std_logic_vector(31 downto 0);
|
||||
bclk_ctrlport_req_byte_en : in std_logic_vector(3 downto 0);
|
||||
bclk_ctrlport_req_has_time : in std_logic;
|
||||
bclk_ctrlport_req_time : in std_logic_vector(63 downto 0);
|
||||
bclk_ctrlport_resp_ack : out std_logic;
|
||||
bclk_ctrlport_resp_status : out std_logic_vector(1 downto 0);
|
||||
bclk_ctrlport_resp_data : out std_logic_vector(31 downto 0);
|
||||
capture_sysref_clk : in std_logic;
|
||||
sysref_in_p : in std_logic;
|
||||
sysref_in_n : in std_logic;
|
||||
sclk_sysref_out : out std_logic;
|
||||
adc_rx_p : in std_logic_vector(1 downto 0);
|
||||
adc_rx_n : in std_logic_vector(1 downto 0);
|
||||
adc_sync_out_n : out std_logic;
|
||||
dac_tx_p : out std_logic_vector(1 downto 0);
|
||||
dac_tx_n : out std_logic_vector(1 downto 0);
|
||||
dac_sync_in_n : in std_logic;
|
||||
sclk_adc_data_flatter : out std_logic_vector(63 downto 0);
|
||||
sclk_dac_data_flatter : in std_logic_vector(63 downto 0);
|
||||
sclk_adc_data_valid : out std_logic;
|
||||
sclk_dac_ready_for_input : out std_logic;
|
||||
dac_sync_out : out std_logic;
|
||||
adc_sync_out : out std_logic
|
||||
);
|
||||
end entity b310_jesd204b;
|
||||
|
||||
architecture RTL of b310_jesd204b is
|
||||
begin
|
||||
end architecture RTL;
|
||||
BIN
fpga/usrp3/top/b300/netlists/cpld_interface_wrapper.edf
Normal file
BIN
fpga/usrp3/top/b300/netlists/cpld_interface_wrapper.edf
Normal file
Binary file not shown.
34
fpga/usrp3/top/b300/netlists/cpld_interface_wrapper.vhd
Normal file
34
fpga/usrp3/top/b300/netlists/cpld_interface_wrapper.vhd
Normal file
@ -0,0 +1,34 @@
|
||||
--
|
||||
-- Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
--
|
||||
-- SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
--
|
||||
-- Module: cpld_interface_wrapper
|
||||
--
|
||||
-- Description:
|
||||
-- This module serves as a wrapper for the CPLD interface, providing
|
||||
-- the necessary ports and connections for communication between the FPGA
|
||||
-- and the CPLD. It includes ports for reset, clock, and data signals.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity cpld_interface_wrapper is
|
||||
port (
|
||||
a_reset : in std_logic
|
||||
; bus_clk : in std_logic
|
||||
; b_reg_port_in : in std_logic_vector(50 downto 0)
|
||||
; b_reg_port_out : out std_logic_vector(33 downto 0)
|
||||
; a_cpld_ext_reset_n : out std_logic
|
||||
; fpga_to_cpld_clk : out std_logic
|
||||
; f_fpga_to_cpld_clk_en : out std_logic
|
||||
; f_fpga_to_cpld_data : out std_logic_vector(7 downto 0)
|
||||
; cpld_to_fpga_clk : in std_logic
|
||||
; c_cpld_to_fpga_data : in std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity cpld_interface_wrapper;
|
||||
|
||||
architecture rtl of cpld_interface_wrapper is
|
||||
begin
|
||||
end architecture rtl;
|
||||
64
fpga/usrp3/top/b300/regmap/b310_bar0_regmap_utils.vh
Normal file
64
fpga/usrp3/top/b300/regmap/b310_bar0_regmap_utils.vh
Normal file
@ -0,0 +1,64 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: b310_bar0_regmap_utils.vh
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
//
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// BASIC_REGS_WINDOW : 0x0 (b310_core.sv)
|
||||
// CORE_REGS_WINDOW : 0x20 (b310_core.sv)
|
||||
// MBOARD_I2C_WINDOW : 0x70 (b310_core.sv)
|
||||
// CLOCKING_SPI_WINDOW : 0xA0 (b310_core.sv)
|
||||
// THUNDERBOLT_I2C_WINDOW : 0xC0 (b310_core.sv)
|
||||
// TIMEKEEPER_WINDOW : 0x100 (b310_core.sv)
|
||||
// GPS_UART_WINDOW : 0x130 (b310_core.sv)
|
||||
// CPLD_JTAG_WINDOW : 0x150 (b310_core.sv)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group CORE_CONTROL_REGS
|
||||
//===============================================================================
|
||||
|
||||
// BASIC_REGS_WINDOW Window (from b310_core.sv)
|
||||
localparam BASIC_REGS_WINDOW = 'h0; // Window Offset
|
||||
localparam BASIC_REGS_WINDOW_SIZE = 'h20; // size in bytes
|
||||
|
||||
// CORE_REGS_WINDOW Window (from b310_core.sv)
|
||||
localparam CORE_REGS_WINDOW = 'h20; // Window Offset
|
||||
localparam CORE_REGS_WINDOW_SIZE = 'h50; // size in bytes
|
||||
|
||||
// MBOARD_I2C_WINDOW Window (from b310_core.sv)
|
||||
localparam MBOARD_I2C_WINDOW = 'h70; // Window Offset
|
||||
localparam MBOARD_I2C_WINDOW_SIZE = 'h20; // size in bytes
|
||||
|
||||
// CLOCKING_SPI_WINDOW Window (from b310_core.sv)
|
||||
localparam CLOCKING_SPI_WINDOW = 'hA0; // Window Offset
|
||||
localparam CLOCKING_SPI_WINDOW_SIZE = 'h20; // size in bytes
|
||||
|
||||
// THUNDERBOLT_I2C_WINDOW Window (from b310_core.sv)
|
||||
localparam THUNDERBOLT_I2C_WINDOW = 'hC0; // Window Offset
|
||||
localparam THUNDERBOLT_I2C_WINDOW_SIZE = 'h20; // size in bytes
|
||||
|
||||
// TIMEKEEPER_WINDOW Window (from b310_core.sv)
|
||||
localparam TIMEKEEPER_WINDOW = 'h100; // Window Offset
|
||||
localparam TIMEKEEPER_WINDOW_SIZE = 'h30; // size in bytes
|
||||
|
||||
// GPS_UART_WINDOW Window (from b310_core.sv)
|
||||
localparam GPS_UART_WINDOW = 'h130; // Window Offset
|
||||
localparam GPS_UART_WINDOW_SIZE = 'h14; // size in bytes
|
||||
|
||||
// CPLD_JTAG_WINDOW Window (from b310_core.sv)
|
||||
localparam CPLD_JTAG_WINDOW = 'h150; // Window Offset
|
||||
localparam CPLD_JTAG_WINDOW_SIZE = 'h20; // size in bytes
|
||||
39
fpga/usrp3/top/b300/regmap/b310_radio_regmap_utils.vh
Normal file
39
fpga/usrp3/top/b300/regmap/b310_radio_regmap_utils.vh
Normal file
@ -0,0 +1,39 @@
|
||||
//
|
||||
// Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: b310_radio_regmap_utils.vh
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
//
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// RADIO0_CONTROL_WINDOW : 0x0 (b310_core.sv)
|
||||
// RADIO_SPI_WINDOW : 0x100 (b310_core.sv)
|
||||
// JESD_CTRL_WINDOW : 0x1000 (b310_core.sv)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group RADIO_CONTROL_REGS
|
||||
//===============================================================================
|
||||
|
||||
// RADIO0_CONTROL_WINDOW Window (from b310_core.sv)
|
||||
localparam RADIO0_CONTROL_WINDOW = 'h0; // Window Offset
|
||||
localparam RADIO0_CONTROL_WINDOW_SIZE = 'h100; // size in bytes
|
||||
|
||||
// RADIO_SPI_WINDOW Window (from b310_core.sv)
|
||||
localparam RADIO_SPI_WINDOW = 'h100; // Window Offset
|
||||
localparam RADIO_SPI_WINDOW_SIZE = 'h100; // size in bytes
|
||||
|
||||
// JESD_CTRL_WINDOW Window (from b310_core.sv)
|
||||
localparam JESD_CTRL_WINDOW = 'h1000; // Window Offset
|
||||
localparam JESD_CTRL_WINDOW_SIZE = 'h1000; // size in bytes
|
||||
113
fpga/usrp3/top/b300/regmap/basic_regs_regmap_utils.vh
Normal file
113
fpga/usrp3/top/b300/regmap/basic_regs_regmap_utils.vh
Normal file
@ -0,0 +1,113 @@
|
||||
//
|
||||
// Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: basic_regs_regmap_utils.vh
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
//
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// CORE_SIGNATURE : 0x0 (basic_regs.sv)
|
||||
// CORE_REVISION : 0x4 (basic_regs.sv)
|
||||
// CORE_OLDEST_REVISION : 0x8 (basic_regs.sv)
|
||||
// VERSION_LAST_MODIFIED : 0xC (basic_regs.sv)
|
||||
// CORE_SCRATCH : 0x10 (basic_regs.sv)
|
||||
// GIT_HASH_REGISTER : 0x14 (basic_regs.sv)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group BASIC_REGS_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// Enumerated type FPGA_VERSION
|
||||
localparam FPGA_VERSION_SIZE = 8;
|
||||
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
|
||||
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
|
||||
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
|
||||
localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
|
||||
localparam FPGA_CURRENT_VERSION_MAJOR = 'h2; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
|
||||
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h2; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
|
||||
localparam BOARD_ID_VALUE = 'hB310; // FPGA_VERSION:BOARD_ID_VALUE
|
||||
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h26061611; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
|
||||
|
||||
// CORE_SIGNATURE Register (from basic_regs.sv)
|
||||
localparam CORE_SIGNATURE = 'h0; // Register Offset
|
||||
localparam CORE_SIGNATURE_SIZE = 32; // register width in bits
|
||||
localparam CORE_SIGNATURE_MASK = 32'hFFFF;
|
||||
localparam BOARD_ID_SIZE = 16; //CORE_SIGNATURE:BOARD_ID
|
||||
localparam BOARD_ID_MSB = 15; //CORE_SIGNATURE:BOARD_ID
|
||||
localparam BOARD_ID = 0; //CORE_SIGNATURE:BOARD_ID
|
||||
|
||||
// CORE_REVISION Register (from basic_regs.sv)
|
||||
localparam CORE_REVISION = 'h4; // Register Offset
|
||||
localparam CORE_REVISION_SIZE = 32; // register width in bits
|
||||
localparam CORE_REVISION_MASK = 32'hFFFFFFFF;
|
||||
localparam CURRENT_REV_BUILD_SIZE = 16; //CORE_REVISION:CURRENT_REV_BUILD
|
||||
localparam CURRENT_REV_BUILD_MSB = 15; //CORE_REVISION:CURRENT_REV_BUILD
|
||||
localparam CURRENT_REV_BUILD = 0; //CORE_REVISION:CURRENT_REV_BUILD
|
||||
localparam CURRENT_REV_MINOR_SIZE = 8; //CORE_REVISION:CURRENT_REV_MINOR
|
||||
localparam CURRENT_REV_MINOR_MSB = 23; //CORE_REVISION:CURRENT_REV_MINOR
|
||||
localparam CURRENT_REV_MINOR = 16; //CORE_REVISION:CURRENT_REV_MINOR
|
||||
localparam CURRENT_REV_MAJOR_SIZE = 8; //CORE_REVISION:CURRENT_REV_MAJOR
|
||||
localparam CURRENT_REV_MAJOR_MSB = 31; //CORE_REVISION:CURRENT_REV_MAJOR
|
||||
localparam CURRENT_REV_MAJOR = 24; //CORE_REVISION:CURRENT_REV_MAJOR
|
||||
|
||||
// CORE_OLDEST_REVISION Register (from basic_regs.sv)
|
||||
localparam CORE_OLDEST_REVISION = 'h8; // Register Offset
|
||||
localparam CORE_OLDEST_REVISION_SIZE = 32; // register width in bits
|
||||
localparam CORE_OLDEST_REVISION_MASK = 32'hFFFFFFFF;
|
||||
localparam OLDEST_REVISION_BUILD_SIZE = 16; //CORE_OLDEST_REVISION:OLDEST_REVISION_BUILD
|
||||
localparam OLDEST_REVISION_BUILD_MSB = 15; //CORE_OLDEST_REVISION:OLDEST_REVISION_BUILD
|
||||
localparam OLDEST_REVISION_BUILD = 0; //CORE_OLDEST_REVISION:OLDEST_REVISION_BUILD
|
||||
localparam OLDEST_REVISION_MINOR_SIZE = 8; //CORE_OLDEST_REVISION:OLDEST_REVISION_MINOR
|
||||
localparam OLDEST_REVISION_MINOR_MSB = 23; //CORE_OLDEST_REVISION:OLDEST_REVISION_MINOR
|
||||
localparam OLDEST_REVISION_MINOR = 16; //CORE_OLDEST_REVISION:OLDEST_REVISION_MINOR
|
||||
localparam OLDEST_REVISION_MAJOR_SIZE = 8; //CORE_OLDEST_REVISION:OLDEST_REVISION_MAJOR
|
||||
localparam OLDEST_REVISION_MAJOR_MSB = 31; //CORE_OLDEST_REVISION:OLDEST_REVISION_MAJOR
|
||||
localparam OLDEST_REVISION_MAJOR = 24; //CORE_OLDEST_REVISION:OLDEST_REVISION_MAJOR
|
||||
|
||||
// VERSION_LAST_MODIFIED Register (from basic_regs.sv)
|
||||
localparam VERSION_LAST_MODIFIED = 'hC; // Register Offset
|
||||
localparam VERSION_LAST_MODIFIED_SIZE = 32; // register width in bits
|
||||
localparam VERSION_LAST_MODIFIED_MASK = 32'hFFFFFFFF;
|
||||
localparam HH_SIZE = 8; //VERSION_LAST_MODIFIED:HH
|
||||
localparam HH_MSB = 7; //VERSION_LAST_MODIFIED:HH
|
||||
localparam HH = 0; //VERSION_LAST_MODIFIED:HH
|
||||
localparam DD_SIZE = 8; //VERSION_LAST_MODIFIED:DD
|
||||
localparam DD_MSB = 15; //VERSION_LAST_MODIFIED:DD
|
||||
localparam DD = 8; //VERSION_LAST_MODIFIED:DD
|
||||
localparam MM_SIZE = 8; //VERSION_LAST_MODIFIED:MM
|
||||
localparam MM_MSB = 23; //VERSION_LAST_MODIFIED:MM
|
||||
localparam MM = 16; //VERSION_LAST_MODIFIED:MM
|
||||
localparam YY_SIZE = 8; //VERSION_LAST_MODIFIED:YY
|
||||
localparam YY_MSB = 31; //VERSION_LAST_MODIFIED:YY
|
||||
localparam YY = 24; //VERSION_LAST_MODIFIED:YY
|
||||
|
||||
// CORE_SCRATCH Register (from basic_regs.sv)
|
||||
localparam CORE_SCRATCH = 'h10; // Register Offset
|
||||
localparam CORE_SCRATCH_SIZE = 32; // register width in bits
|
||||
localparam CORE_SCRATCH_MASK = 32'hFFFFFFFF;
|
||||
localparam SCRATCH_REG_SIZE = 32; //CORE_SCRATCH:SCRATCH_REG
|
||||
localparam SCRATCH_REG_MSB = 31; //CORE_SCRATCH:SCRATCH_REG
|
||||
localparam SCRATCH_REG = 0; //CORE_SCRATCH:SCRATCH_REG
|
||||
|
||||
// GIT_HASH_REGISTER Register (from basic_regs.sv)
|
||||
localparam GIT_HASH_REGISTER = 'h14; // Register Offset
|
||||
localparam GIT_HASH_REGISTER_SIZE = 32; // register width in bits
|
||||
localparam GIT_HASH_REGISTER_MASK = 32'hFFFFFFFF;
|
||||
localparam GIT_HASH_SIZE = 28; //GIT_HASH_REGISTER:GIT_HASH
|
||||
localparam GIT_HASH_MSB = 27; //GIT_HASH_REGISTER:GIT_HASH
|
||||
localparam GIT_HASH = 0; //GIT_HASH_REGISTER:GIT_HASH
|
||||
localparam GIT_CLEAN_SIZE = 4; //GIT_HASH_REGISTER:GIT_CLEAN
|
||||
localparam GIT_CLEAN_MSB = 31; //GIT_HASH_REGISTER:GIT_CLEAN
|
||||
localparam GIT_CLEAN = 28; //GIT_HASH_REGISTER:GIT_CLEAN
|
||||
299
fpga/usrp3/top/b300/regmap/core_regs_regmap_utils.vh
Normal file
299
fpga/usrp3/top/b300/regmap/core_regs_regmap_utils.vh
Normal file
@ -0,0 +1,299 @@
|
||||
//
|
||||
// Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: core_regs_regmap_utils.vh
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
//
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// FPGA_DEVICE_ID : 0x0 (core_regs.sv)
|
||||
// CORE_SW_RESETS : 0x4 (core_regs.sv)
|
||||
// CORE_CLOCK_CTRL : 0x8 (core_regs.sv)
|
||||
// CORE_CLOCK_STATUS : 0xC (core_regs.sv)
|
||||
// DEVICE_DNA_LOW : 0x10 (core_regs.sv)
|
||||
// DEVICE_DNA_HIGH : 0x14 (core_regs.sv)
|
||||
// CORE_COMPAT_NUM : 0x18 (core_regs.sv)
|
||||
// CORE_RFNOC_INFO : 0x1C (core_regs.sv)
|
||||
// RADIO_TIME_LOW : 0x20 (core_regs.sv)
|
||||
// RADIO_TIME_HIGH : 0x24 (core_regs.sv)
|
||||
// INT_PPS_DIVIDER : 0x28 (core_regs.sv)
|
||||
// CORE_NUM_TIMEKEEPERS : 0x2C (core_regs.sv)
|
||||
// CORE_BUILD_SEED : 0x30 (core_regs.sv)
|
||||
// FP_GPIO_SRC : 0x34 (core_regs.sv)
|
||||
// GPS_CTRL : 0x38 (core_regs.sv)
|
||||
// TEMP_MON : 0x3C (core_regs.sv)
|
||||
// LMK_SYNC_CTRL : 0x40 (core_regs.sv)
|
||||
// PPS_IN_CTRL : 0x44 (core_regs.sv)
|
||||
// TBOLT_CTRL : 0x48 (core_regs.sv)
|
||||
// POWER_CONTROL_STS : 0x4C (core_regs.sv)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group CORE_REGS_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// Enumerated type CLOCKING_SPI_SLAVES
|
||||
localparam CLOCKING_SPI_SLAVES_SIZE = 3;
|
||||
localparam CLOCKING_SPI_LMK04832_SS = 'h0; // CLOCKING_SPI_SLAVES:CLOCKING_SPI_LMK04832_SS
|
||||
localparam CLOCKING_SPI_TCXO_DAC_SS = 'h1; // CLOCKING_SPI_SLAVES:CLOCKING_SPI_TCXO_DAC_SS
|
||||
localparam CLOCKING_SPI_LMK053_SS = 'h2; // CLOCKING_SPI_SLAVES:CLOCKING_SPI_LMK053_SS
|
||||
|
||||
// Enumerated type CORE_COMPATIBILITY
|
||||
localparam CORE_COMPATIBILITY_SIZE = 2;
|
||||
localparam CORE_COMPAT_MINOR_VAL = 'h1; // CORE_COMPATIBILITY:CORE_COMPAT_MINOR_VAL
|
||||
localparam CORE_COMPAT_MAJOR_VAL = 'h2; // CORE_COMPATIBILITY:CORE_COMPAT_MAJOR_VAL
|
||||
|
||||
// FPGA_DEVICE_ID Register (from core_regs.sv)
|
||||
localparam FPGA_DEVICE_ID = 'h0; // Register Offset
|
||||
localparam FPGA_DEVICE_ID_SIZE = 32; // register width in bits
|
||||
localparam FPGA_DEVICE_ID_MASK = 32'hFFFF;
|
||||
localparam DEVICE_ID_SIZE = 16; //FPGA_DEVICE_ID:DEVICE_ID
|
||||
localparam DEVICE_ID_MSB = 15; //FPGA_DEVICE_ID:DEVICE_ID
|
||||
localparam DEVICE_ID = 0; //FPGA_DEVICE_ID:DEVICE_ID
|
||||
|
||||
// CORE_SW_RESETS Register (from core_regs.sv)
|
||||
localparam CORE_SW_RESETS = 'h4; // Register Offset
|
||||
localparam CORE_SW_RESETS_SIZE = 32; // register width in bits
|
||||
localparam CORE_SW_RESETS_MASK = 32'h1;
|
||||
localparam RADIO_CLK_GEN_RST_SIZE = 1; //CORE_SW_RESETS:RADIO_CLK_GEN_RST
|
||||
localparam RADIO_CLK_GEN_RST_MSB = 0; //CORE_SW_RESETS:RADIO_CLK_GEN_RST
|
||||
localparam RADIO_CLK_GEN_RST = 0; //CORE_SW_RESETS:RADIO_CLK_GEN_RST
|
||||
|
||||
// CORE_CLOCK_CTRL Register (from core_regs.sv)
|
||||
localparam CORE_CLOCK_CTRL = 'h8; // Register Offset
|
||||
localparam CORE_CLOCK_CTRL_SIZE = 32; // register width in bits
|
||||
localparam CORE_CLOCK_CTRL_MASK = 32'h13111;
|
||||
localparam REF_CLK_SOURCE_SIZE = 1; //CORE_CLOCK_CTRL:REF_CLK_SOURCE
|
||||
localparam REF_CLK_SOURCE_MSB = 0; //CORE_CLOCK_CTRL:REF_CLK_SOURCE
|
||||
localparam REF_CLK_SOURCE = 0; //CORE_CLOCK_CTRL:REF_CLK_SOURCE
|
||||
localparam LMK_SOURCE_SELECT_SIZE = 1; //CORE_CLOCK_CTRL:LMK_SOURCE_SELECT
|
||||
localparam LMK_SOURCE_SELECT_MSB = 4; //CORE_CLOCK_CTRL:LMK_SOURCE_SELECT
|
||||
localparam LMK_SOURCE_SELECT = 4; //CORE_CLOCK_CTRL:LMK_SOURCE_SELECT
|
||||
localparam TCXO_EN_SIZE = 1; //CORE_CLOCK_CTRL:TCXO_EN
|
||||
localparam TCXO_EN_MSB = 8; //CORE_CLOCK_CTRL:TCXO_EN
|
||||
localparam TCXO_EN = 8; //CORE_CLOCK_CTRL:TCXO_EN
|
||||
localparam LMK_RESET_SIZE = 1; //CORE_CLOCK_CTRL:LMK_RESET
|
||||
localparam LMK_RESET_MSB = 12; //CORE_CLOCK_CTRL:LMK_RESET
|
||||
localparam LMK_RESET = 12; //CORE_CLOCK_CTRL:LMK_RESET
|
||||
localparam LMK05318_PD_N_SIZE = 1; //CORE_CLOCK_CTRL:LMK05318_PD_N
|
||||
localparam LMK05318_PD_N_MSB = 13; //CORE_CLOCK_CTRL:LMK05318_PD_N
|
||||
localparam LMK05318_PD_N = 13; //CORE_CLOCK_CTRL:LMK05318_PD_N
|
||||
localparam USE_EXTERNAL_PPS_SIZE = 1; //CORE_CLOCK_CTRL:USE_EXTERNAL_PPS
|
||||
localparam USE_EXTERNAL_PPS_MSB = 16; //CORE_CLOCK_CTRL:USE_EXTERNAL_PPS
|
||||
localparam USE_EXTERNAL_PPS = 16; //CORE_CLOCK_CTRL:USE_EXTERNAL_PPS
|
||||
|
||||
// CORE_CLOCK_STATUS Register (from core_regs.sv)
|
||||
localparam CORE_CLOCK_STATUS = 'hC; // Register Offset
|
||||
localparam CORE_CLOCK_STATUS_SIZE = 32; // register width in bits
|
||||
localparam CORE_CLOCK_STATUS_MASK = 32'h100;
|
||||
localparam LMK_LOCK_STATUS_SIZE = 1; //CORE_CLOCK_STATUS:LMK_LOCK_STATUS
|
||||
localparam LMK_LOCK_STATUS_MSB = 8; //CORE_CLOCK_STATUS:LMK_LOCK_STATUS
|
||||
localparam LMK_LOCK_STATUS = 8; //CORE_CLOCK_STATUS:LMK_LOCK_STATUS
|
||||
|
||||
// DEVICE_DNA_LOW Register (from core_regs.sv)
|
||||
localparam DEVICE_DNA_LOW = 'h10; // Register Offset
|
||||
localparam DEVICE_DNA_LOW_SIZE = 32; // register width in bits
|
||||
localparam DEVICE_DNA_LOW_MASK = 32'hFFFFFFFF;
|
||||
localparam DEV_DNA_LO_SIZE = 32; //DEVICE_DNA_LOW:DEV_DNA_LO
|
||||
localparam DEV_DNA_LO_MSB = 31; //DEVICE_DNA_LOW:DEV_DNA_LO
|
||||
localparam DEV_DNA_LO = 0; //DEVICE_DNA_LOW:DEV_DNA_LO
|
||||
|
||||
// DEVICE_DNA_HIGH Register (from core_regs.sv)
|
||||
localparam DEVICE_DNA_HIGH = 'h14; // Register Offset
|
||||
localparam DEVICE_DNA_HIGH_SIZE = 32; // register width in bits
|
||||
localparam DEVICE_DNA_HIGH_MASK = 32'hFFFFFFFF;
|
||||
localparam DEV_DNA_HI_SIZE = 32; //DEVICE_DNA_HIGH:DEV_DNA_HI
|
||||
localparam DEV_DNA_HI_MSB = 31; //DEVICE_DNA_HIGH:DEV_DNA_HI
|
||||
localparam DEV_DNA_HI = 0; //DEVICE_DNA_HIGH:DEV_DNA_HI
|
||||
|
||||
// CORE_COMPAT_NUM Register (from core_regs.sv)
|
||||
localparam CORE_COMPAT_NUM = 'h18; // Register Offset
|
||||
localparam CORE_COMPAT_NUM_SIZE = 32; // register width in bits
|
||||
localparam CORE_COMPAT_NUM_MASK = 32'hFFFFFFFF;
|
||||
localparam CORE_MINOR_COMPAT_SIZE = 16; //CORE_COMPAT_NUM:CORE_MINOR_COMPAT
|
||||
localparam CORE_MINOR_COMPAT_MSB = 15; //CORE_COMPAT_NUM:CORE_MINOR_COMPAT
|
||||
localparam CORE_MINOR_COMPAT = 0; //CORE_COMPAT_NUM:CORE_MINOR_COMPAT
|
||||
localparam CORE_MAJOR_COMPAT_SIZE = 16; //CORE_COMPAT_NUM:CORE_MAJOR_COMPAT
|
||||
localparam CORE_MAJOR_COMPAT_MSB = 31; //CORE_COMPAT_NUM:CORE_MAJOR_COMPAT
|
||||
localparam CORE_MAJOR_COMPAT = 16; //CORE_COMPAT_NUM:CORE_MAJOR_COMPAT
|
||||
|
||||
// CORE_RFNOC_INFO Register (from core_regs.sv)
|
||||
localparam CORE_RFNOC_INFO = 'h1C; // Register Offset
|
||||
localparam CORE_RFNOC_INFO_SIZE = 32; // register width in bits
|
||||
localparam CORE_RFNOC_INFO_MASK = 32'hFFFFFFFF;
|
||||
localparam RFNOC_PROTO_VERSION_SIZE = 16; //CORE_RFNOC_INFO:RFNOC_PROTO_VERSION
|
||||
localparam RFNOC_PROTO_VERSION_MSB = 15; //CORE_RFNOC_INFO:RFNOC_PROTO_VERSION
|
||||
localparam RFNOC_PROTO_VERSION = 0; //CORE_RFNOC_INFO:RFNOC_PROTO_VERSION
|
||||
localparam RFNOC_CHDR_WIDTH_SIZE = 16; //CORE_RFNOC_INFO:RFNOC_CHDR_WIDTH
|
||||
localparam RFNOC_CHDR_WIDTH_MSB = 31; //CORE_RFNOC_INFO:RFNOC_CHDR_WIDTH
|
||||
localparam RFNOC_CHDR_WIDTH = 16; //CORE_RFNOC_INFO:RFNOC_CHDR_WIDTH
|
||||
|
||||
// RADIO_TIME_LOW Register (from core_regs.sv)
|
||||
localparam RADIO_TIME_LOW = 'h20; // Register Offset
|
||||
localparam RADIO_TIME_LOW_SIZE = 32; // register width in bits
|
||||
localparam RADIO_TIME_LOW_MASK = 32'h0;
|
||||
|
||||
// RADIO_TIME_HIGH Register (from core_regs.sv)
|
||||
localparam RADIO_TIME_HIGH = 'h24; // Register Offset
|
||||
localparam RADIO_TIME_HIGH_SIZE = 32; // register width in bits
|
||||
localparam RADIO_TIME_HIGH_MASK = 32'h0;
|
||||
|
||||
// INT_PPS_DIVIDER Register (from core_regs.sv)
|
||||
localparam INT_PPS_DIVIDER = 'h28; // Register Offset
|
||||
localparam INT_PPS_DIVIDER_SIZE = 32; // register width in bits
|
||||
localparam INT_PPS_DIVIDER_MASK = 32'hFFFFFFFF;
|
||||
localparam INT_PPS_DIV_SIZE = 32; //INT_PPS_DIVIDER:INT_PPS_DIV
|
||||
localparam INT_PPS_DIV_MSB = 31; //INT_PPS_DIVIDER:INT_PPS_DIV
|
||||
localparam INT_PPS_DIV = 0; //INT_PPS_DIVIDER:INT_PPS_DIV
|
||||
|
||||
// CORE_NUM_TIMEKEEPERS Register (from core_regs.sv)
|
||||
localparam CORE_NUM_TIMEKEEPERS = 'h2C; // Register Offset
|
||||
localparam CORE_NUM_TIMEKEEPERS_SIZE = 32; // register width in bits
|
||||
localparam CORE_NUM_TIMEKEEPERS_MASK = 32'hFFFFFFFF;
|
||||
localparam CORE_NUM_TIMEKEEPERS_VAL_SIZE = 32; //CORE_NUM_TIMEKEEPERS:CORE_NUM_TIMEKEEPERS_VAL
|
||||
localparam CORE_NUM_TIMEKEEPERS_VAL_MSB = 31; //CORE_NUM_TIMEKEEPERS:CORE_NUM_TIMEKEEPERS_VAL
|
||||
localparam CORE_NUM_TIMEKEEPERS_VAL = 0; //CORE_NUM_TIMEKEEPERS:CORE_NUM_TIMEKEEPERS_VAL
|
||||
|
||||
// CORE_BUILD_SEED Register (from core_regs.sv)
|
||||
localparam CORE_BUILD_SEED = 'h30; // Register Offset
|
||||
localparam CORE_BUILD_SEED_SIZE = 32; // register width in bits
|
||||
localparam CORE_BUILD_SEED_MASK = 32'hFFFFFFFF;
|
||||
localparam CORE_BUILD_SEED_VAL_SIZE = 32; //CORE_BUILD_SEED:CORE_BUILD_SEED_VAL
|
||||
localparam CORE_BUILD_SEED_VAL_MSB = 31; //CORE_BUILD_SEED:CORE_BUILD_SEED_VAL
|
||||
localparam CORE_BUILD_SEED_VAL = 0; //CORE_BUILD_SEED:CORE_BUILD_SEED_VAL
|
||||
|
||||
// FP_GPIO_SRC Register (from core_regs.sv)
|
||||
localparam FP_GPIO_SRC = 'h34; // Register Offset
|
||||
localparam FP_GPIO_SRC_SIZE = 32; // register width in bits
|
||||
localparam FP_GPIO_SRC_MASK = 32'hFFFFF;
|
||||
localparam FP_GPIO0_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO0_SRC
|
||||
localparam FP_GPIO0_SRC_MSB = 1; //FP_GPIO_SRC:FP_GPIO0_SRC
|
||||
localparam FP_GPIO0_SRC = 0; //FP_GPIO_SRC:FP_GPIO0_SRC
|
||||
localparam FP_GPIO1_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO1_SRC
|
||||
localparam FP_GPIO1_SRC_MSB = 3; //FP_GPIO_SRC:FP_GPIO1_SRC
|
||||
localparam FP_GPIO1_SRC = 2; //FP_GPIO_SRC:FP_GPIO1_SRC
|
||||
localparam FP_GPIO2_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO2_SRC
|
||||
localparam FP_GPIO2_SRC_MSB = 5; //FP_GPIO_SRC:FP_GPIO2_SRC
|
||||
localparam FP_GPIO2_SRC = 4; //FP_GPIO_SRC:FP_GPIO2_SRC
|
||||
localparam FP_GPIO3_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO3_SRC
|
||||
localparam FP_GPIO3_SRC_MSB = 7; //FP_GPIO_SRC:FP_GPIO3_SRC
|
||||
localparam FP_GPIO3_SRC = 6; //FP_GPIO_SRC:FP_GPIO3_SRC
|
||||
localparam FP_GPIO4_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO4_SRC
|
||||
localparam FP_GPIO4_SRC_MSB = 9; //FP_GPIO_SRC:FP_GPIO4_SRC
|
||||
localparam FP_GPIO4_SRC = 8; //FP_GPIO_SRC:FP_GPIO4_SRC
|
||||
localparam FP_GPIO5_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO5_SRC
|
||||
localparam FP_GPIO5_SRC_MSB = 11; //FP_GPIO_SRC:FP_GPIO5_SRC
|
||||
localparam FP_GPIO5_SRC = 10; //FP_GPIO_SRC:FP_GPIO5_SRC
|
||||
localparam FP_GPIO6_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO6_SRC
|
||||
localparam FP_GPIO6_SRC_MSB = 13; //FP_GPIO_SRC:FP_GPIO6_SRC
|
||||
localparam FP_GPIO6_SRC = 12; //FP_GPIO_SRC:FP_GPIO6_SRC
|
||||
localparam FP_GPIO7_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO7_SRC
|
||||
localparam FP_GPIO7_SRC_MSB = 15; //FP_GPIO_SRC:FP_GPIO7_SRC
|
||||
localparam FP_GPIO7_SRC = 14; //FP_GPIO_SRC:FP_GPIO7_SRC
|
||||
localparam FP_GPIO8_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO8_SRC
|
||||
localparam FP_GPIO8_SRC_MSB = 17; //FP_GPIO_SRC:FP_GPIO8_SRC
|
||||
localparam FP_GPIO8_SRC = 16; //FP_GPIO_SRC:FP_GPIO8_SRC
|
||||
localparam FP_GPIO9_SRC_SIZE = 2; //FP_GPIO_SRC:FP_GPIO9_SRC
|
||||
localparam FP_GPIO9_SRC_MSB = 19; //FP_GPIO_SRC:FP_GPIO9_SRC
|
||||
localparam FP_GPIO9_SRC = 18; //FP_GPIO_SRC:FP_GPIO9_SRC
|
||||
|
||||
// GPS_CTRL Register (from core_regs.sv)
|
||||
localparam GPS_CTRL = 'h38; // Register Offset
|
||||
localparam GPS_CTRL_SIZE = 32; // register width in bits
|
||||
localparam GPS_CTRL_MASK = 32'h113113;
|
||||
localparam REG_GPS_RESET_N_SIZE = 1; //GPS_CTRL:REG_GPS_RESET_N
|
||||
localparam REG_GPS_RESET_N_MSB = 0; //GPS_CTRL:REG_GPS_RESET_N
|
||||
localparam REG_GPS_RESET_N = 0; //GPS_CTRL:REG_GPS_RESET_N
|
||||
localparam REG_GPS_ANT_PWR_EN_SIZE = 1; //GPS_CTRL:REG_GPS_ANT_PWR_EN
|
||||
localparam REG_GPS_ANT_PWR_EN_MSB = 1; //GPS_CTRL:REG_GPS_ANT_PWR_EN
|
||||
localparam REG_GPS_ANT_PWR_EN = 1; //GPS_CTRL:REG_GPS_ANT_PWR_EN
|
||||
localparam GPS_PW_FAULT_SIZE = 1; //GPS_CTRL:GPS_PW_FAULT
|
||||
localparam GPS_PW_FAULT_MSB = 4; //GPS_CTRL:GPS_PW_FAULT
|
||||
localparam GPS_PW_FAULT = 4; //GPS_CTRL:GPS_PW_FAULT
|
||||
localparam GPS_LMK_PPS_MONITOR_SIZE = 1; //GPS_CTRL:GPS_LMK_PPS_MONITOR
|
||||
localparam GPS_LMK_PPS_MONITOR_MSB = 8; //GPS_CTRL:GPS_LMK_PPS_MONITOR
|
||||
localparam GPS_LMK_PPS_MONITOR = 8; //GPS_CTRL:GPS_LMK_PPS_MONITOR
|
||||
localparam GPS_LMK_STATUS_SIZE = 2; //GPS_CTRL:GPS_LMK_STATUS
|
||||
localparam GPS_LMK_STATUS_MSB = 13; //GPS_CTRL:GPS_LMK_STATUS
|
||||
localparam GPS_LMK_STATUS = 12; //GPS_CTRL:GPS_LMK_STATUS
|
||||
localparam GPS_LMK_GPIO_SIZE = 1; //GPS_CTRL:GPS_LMK_GPIO
|
||||
localparam GPS_LMK_GPIO_MSB = 16; //GPS_CTRL:GPS_LMK_GPIO
|
||||
localparam GPS_LMK_GPIO = 16; //GPS_CTRL:GPS_LMK_GPIO
|
||||
localparam GPS_BYPASS_LMK_SIZE = 1; //GPS_CTRL:GPS_BYPASS_LMK
|
||||
localparam GPS_BYPASS_LMK_MSB = 20; //GPS_CTRL:GPS_BYPASS_LMK
|
||||
localparam GPS_BYPASS_LMK = 20; //GPS_CTRL:GPS_BYPASS_LMK
|
||||
|
||||
// TEMP_MON Register (from core_regs.sv)
|
||||
localparam TEMP_MON = 'h3C; // Register Offset
|
||||
localparam TEMP_MON_SIZE = 32; // register width in bits
|
||||
localparam TEMP_MON_MASK = 32'hFFF;
|
||||
localparam DEVICE_TEMP_SIZE = 12; //TEMP_MON:DEVICE_TEMP
|
||||
localparam DEVICE_TEMP_MSB = 11; //TEMP_MON:DEVICE_TEMP
|
||||
localparam DEVICE_TEMP = 0; //TEMP_MON:DEVICE_TEMP
|
||||
|
||||
// LMK_SYNC_CTRL Register (from core_regs.sv)
|
||||
localparam LMK_SYNC_CTRL = 'h40; // Register Offset
|
||||
localparam LMK_SYNC_CTRL_SIZE = 32; // register width in bits
|
||||
localparam LMK_SYNC_CTRL_MASK = 32'hF7FFFFFF;
|
||||
localparam LMK_SYNC_DELAY_SIZE = 27; //LMK_SYNC_CTRL:LMK_SYNC_DELAY
|
||||
localparam LMK_SYNC_DELAY_MSB = 26; //LMK_SYNC_CTRL:LMK_SYNC_DELAY
|
||||
localparam LMK_SYNC_DELAY = 0; //LMK_SYNC_CTRL:LMK_SYNC_DELAY
|
||||
localparam LMK_SYNC_TRIGGER_SIZE = 1; //LMK_SYNC_CTRL:LMK_SYNC_TRIGGER
|
||||
localparam LMK_SYNC_TRIGGER_MSB = 28; //LMK_SYNC_CTRL:LMK_SYNC_TRIGGER
|
||||
localparam LMK_SYNC_TRIGGER = 28; //LMK_SYNC_CTRL:LMK_SYNC_TRIGGER
|
||||
localparam LMK_SYNC_DONE_SIZE = 1; //LMK_SYNC_CTRL:LMK_SYNC_DONE
|
||||
localparam LMK_SYNC_DONE_MSB = 29; //LMK_SYNC_CTRL:LMK_SYNC_DONE
|
||||
localparam LMK_SYNC_DONE = 29; //LMK_SYNC_CTRL:LMK_SYNC_DONE
|
||||
localparam LMK_SYNC_CLK_SEL_SIZE = 1; //LMK_SYNC_CTRL:LMK_SYNC_CLK_SEL
|
||||
localparam LMK_SYNC_CLK_SEL_MSB = 30; //LMK_SYNC_CTRL:LMK_SYNC_CLK_SEL
|
||||
localparam LMK_SYNC_CLK_SEL = 30; //LMK_SYNC_CTRL:LMK_SYNC_CLK_SEL
|
||||
localparam LMK_CLKIN0_SYNC_SEL_SIZE = 1; //LMK_SYNC_CTRL:LMK_CLKIN0_SYNC_SEL
|
||||
localparam LMK_CLKIN0_SYNC_SEL_MSB = 31; //LMK_SYNC_CTRL:LMK_CLKIN0_SYNC_SEL
|
||||
localparam LMK_CLKIN0_SYNC_SEL = 31; //LMK_SYNC_CTRL:LMK_CLKIN0_SYNC_SEL
|
||||
|
||||
// PPS_IN_CTRL Register (from core_regs.sv)
|
||||
localparam PPS_IN_CTRL = 'h44; // Register Offset
|
||||
localparam PPS_IN_CTRL_SIZE = 32; // register width in bits
|
||||
localparam PPS_IN_CTRL_MASK = 32'h3FF;
|
||||
localparam PPS_IN_TO_RCLK_DELAY_SIZE = 10; //PPS_IN_CTRL:PPS_IN_TO_RCLK_DELAY
|
||||
localparam PPS_IN_TO_RCLK_DELAY_MSB = 9; //PPS_IN_CTRL:PPS_IN_TO_RCLK_DELAY
|
||||
localparam PPS_IN_TO_RCLK_DELAY = 0; //PPS_IN_CTRL:PPS_IN_TO_RCLK_DELAY
|
||||
|
||||
// TBOLT_CTRL Register (from core_regs.sv)
|
||||
localparam TBOLT_CTRL = 'h48; // Register Offset
|
||||
localparam TBOLT_CTRL_SIZE = 32; // register width in bits
|
||||
localparam TBOLT_CTRL_MASK = 32'h1;
|
||||
localparam TBOLT_PD_CTRL_PULSE_RST_SIZE = 1; //TBOLT_CTRL:TBOLT_PD_CTRL_PULSE_RST
|
||||
localparam TBOLT_PD_CTRL_PULSE_RST_MSB = 0; //TBOLT_CTRL:TBOLT_PD_CTRL_PULSE_RST
|
||||
localparam TBOLT_PD_CTRL_PULSE_RST = 0; //TBOLT_CTRL:TBOLT_PD_CTRL_PULSE_RST
|
||||
|
||||
// POWER_CONTROL_STS Register (from core_regs.sv)
|
||||
localparam POWER_CONTROL_STS = 'h4C; // Register Offset
|
||||
localparam POWER_CONTROL_STS_SIZE = 32; // register width in bits
|
||||
localparam POWER_CONTROL_STS_MASK = 32'h133;
|
||||
localparam POWER_GOOD_1V2_SIZE = 1; //POWER_CONTROL_STS:POWER_GOOD_1V2
|
||||
localparam POWER_GOOD_1V2_MSB = 0; //POWER_CONTROL_STS:POWER_GOOD_1V2
|
||||
localparam POWER_GOOD_1V2 = 0; //POWER_CONTROL_STS:POWER_GOOD_1V2
|
||||
localparam POWER_MONITOR_ALERT_SIZE = 1; //POWER_CONTROL_STS:POWER_MONITOR_ALERT
|
||||
localparam POWER_MONITOR_ALERT_MSB = 1; //POWER_CONTROL_STS:POWER_MONITOR_ALERT
|
||||
localparam POWER_MONITOR_ALERT = 1; //POWER_CONTROL_STS:POWER_MONITOR_ALERT
|
||||
localparam POWER_25W_SRC_SIZE = 1; //POWER_CONTROL_STS:POWER_25W_SRC
|
||||
localparam POWER_25W_SRC_MSB = 4; //POWER_CONTROL_STS:POWER_25W_SRC
|
||||
localparam POWER_25W_SRC = 4; //POWER_CONTROL_STS:POWER_25W_SRC
|
||||
localparam TYPEC_POWER_NEGOTIATED_SIZE = 1; //POWER_CONTROL_STS:TYPEC_POWER_NEGOTIATED
|
||||
localparam TYPEC_POWER_NEGOTIATED_MSB = 5; //POWER_CONTROL_STS:TYPEC_POWER_NEGOTIATED
|
||||
localparam TYPEC_POWER_NEGOTIATED = 5; //POWER_CONTROL_STS:TYPEC_POWER_NEGOTIATED
|
||||
localparam POWER_LED_OVERRIDE_SIZE = 1; //POWER_CONTROL_STS:POWER_LED_OVERRIDE
|
||||
localparam POWER_LED_OVERRIDE_MSB = 8; //POWER_CONTROL_STS:POWER_LED_OVERRIDE
|
||||
localparam POWER_LED_OVERRIDE = 8; //POWER_CONTROL_STS:POWER_LED_OVERRIDE
|
||||
186
fpga/usrp3/top/b300/regmap/radio_control_regmap_utils.vh
Normal file
186
fpga/usrp3/top/b300/regmap/radio_control_regmap_utils.vh
Normal file
@ -0,0 +1,186 @@
|
||||
//
|
||||
// Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: radio_control_regmap_utils.vh
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
//
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// MISC_OUTPUTS : 0x0 (radio_control_regs.sv)
|
||||
// MISC_INPUTS : 0x4 (radio_control_regs.sv)
|
||||
// CH0_LED_ATR : 0x10 (radio_control_regs.sv)
|
||||
// CH0_LED_STATUS : 0x18 (radio_control_regs.sv)
|
||||
// CH1_LED_ATR : 0x20 (radio_control_regs.sv)
|
||||
// CH1_LED_STATUS : 0x28 (radio_control_regs.sv)
|
||||
// CH0_FP_GPIO_ATR : 0x30 (radio_control_regs.sv)
|
||||
// CH0_FP_GPIO_STATUS : 0x38 (radio_control_regs.sv)
|
||||
// CH1_FP_GPIO_ATR : 0x40 (radio_control_regs.sv)
|
||||
// CH1_FP_GPIO_STATUS : 0x48 (radio_control_regs.sv)
|
||||
// CH0_ADRV_GPIO_ATR : 0x50 (radio_control_regs.sv)
|
||||
// CH0_ADRV_GPIO_STATUS : 0x58 (radio_control_regs.sv)
|
||||
// CH1_ADRV_GPIO_ATR : 0x60 (radio_control_regs.sv)
|
||||
// CH1_ADRV_GPIO_STATUS : 0x68 (radio_control_regs.sv)
|
||||
// CH0_PATH_CTRL_ATR : 0x70 (radio_control_regs.sv)
|
||||
// CH0_PATH_CTRL_STATUS : 0x78 (radio_control_regs.sv)
|
||||
// CH1_PATH_CTRL_ATR : 0x80 (radio_control_regs.sv)
|
||||
// CH1_PATH_CTRL_STATUS : 0x88 (radio_control_regs.sv)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
// CH_ADRV_GPIO_ATR Type (from radio_control_regs.sv)
|
||||
localparam CH_ADRV_GPIO_ATR_SIZE = 32;
|
||||
localparam CH_ADRV_GPIO_ATR_MASK = 32'hFF;
|
||||
localparam TRX_CTRL_0_SIZE = 1; //CH_ADRV_GPIO_ATR:TRX_CTRL_0
|
||||
localparam TRX_CTRL_0_MSB = 0; //CH_ADRV_GPIO_ATR:TRX_CTRL_0
|
||||
localparam TRX_CTRL_0 = 0; //CH_ADRV_GPIO_ATR:TRX_CTRL_0
|
||||
localparam TRX_CTRL_1_SIZE = 1; //CH_ADRV_GPIO_ATR:TRX_CTRL_1
|
||||
localparam TRX_CTRL_1_MSB = 1; //CH_ADRV_GPIO_ATR:TRX_CTRL_1
|
||||
localparam TRX_CTRL_1 = 1; //CH_ADRV_GPIO_ATR:TRX_CTRL_1
|
||||
localparam TRX_CTRL_2_SIZE = 1; //CH_ADRV_GPIO_ATR:TRX_CTRL_2
|
||||
localparam TRX_CTRL_2_MSB = 2; //CH_ADRV_GPIO_ATR:TRX_CTRL_2
|
||||
localparam TRX_CTRL_2 = 2; //CH_ADRV_GPIO_ATR:TRX_CTRL_2
|
||||
localparam TRX_CTRL_3_SIZE = 1; //CH_ADRV_GPIO_ATR:TRX_CTRL_3
|
||||
localparam TRX_CTRL_3_MSB = 3; //CH_ADRV_GPIO_ATR:TRX_CTRL_3
|
||||
localparam TRX_CTRL_3 = 3; //CH_ADRV_GPIO_ATR:TRX_CTRL_3
|
||||
localparam ADRV_GPIO_0_SIZE = 1; //CH_ADRV_GPIO_ATR:ADRV_GPIO_0
|
||||
localparam ADRV_GPIO_0_MSB = 4; //CH_ADRV_GPIO_ATR:ADRV_GPIO_0
|
||||
localparam ADRV_GPIO_0 = 4; //CH_ADRV_GPIO_ATR:ADRV_GPIO_0
|
||||
localparam ADRV_GPIO_1_SIZE = 1; //CH_ADRV_GPIO_ATR:ADRV_GPIO_1
|
||||
localparam ADRV_GPIO_1_MSB = 5; //CH_ADRV_GPIO_ATR:ADRV_GPIO_1
|
||||
localparam ADRV_GPIO_1 = 5; //CH_ADRV_GPIO_ATR:ADRV_GPIO_1
|
||||
localparam ADRV_GPIO_2_SIZE = 1; //CH_ADRV_GPIO_ATR:ADRV_GPIO_2
|
||||
localparam ADRV_GPIO_2_MSB = 6; //CH_ADRV_GPIO_ATR:ADRV_GPIO_2
|
||||
localparam ADRV_GPIO_2 = 6; //CH_ADRV_GPIO_ATR:ADRV_GPIO_2
|
||||
localparam ADRV_GPIO_3_SIZE = 1; //CH_ADRV_GPIO_ATR:ADRV_GPIO_3
|
||||
localparam ADRV_GPIO_3_MSB = 7; //CH_ADRV_GPIO_ATR:ADRV_GPIO_3
|
||||
localparam ADRV_GPIO_3 = 7; //CH_ADRV_GPIO_ATR:ADRV_GPIO_3
|
||||
|
||||
// CH_FP_GPIO_ATR Type (from radio_control_regs.sv)
|
||||
localparam CH_FP_GPIO_ATR_SIZE = 32;
|
||||
localparam CH_FP_GPIO_ATR_MASK = 32'h3FF;
|
||||
localparam FP_DRIVE_VALUES_SIZE = 10; //CH_FP_GPIO_ATR:FP_DRIVE_VALUES
|
||||
localparam FP_DRIVE_VALUES_MSB = 9; //CH_FP_GPIO_ATR:FP_DRIVE_VALUES
|
||||
localparam FP_DRIVE_VALUES = 0; //CH_FP_GPIO_ATR:FP_DRIVE_VALUES
|
||||
|
||||
// CH_LED_ATR Type (from radio_control_regs.sv)
|
||||
localparam CH_LED_ATR_SIZE = 32;
|
||||
localparam CH_LED_ATR_MASK = 32'h13;
|
||||
localparam LED_TX_GREEN_SIZE = 1; //CH_LED_ATR:LED_TX_GREEN
|
||||
localparam LED_TX_GREEN_MSB = 0; //CH_LED_ATR:LED_TX_GREEN
|
||||
localparam LED_TX_GREEN = 0; //CH_LED_ATR:LED_TX_GREEN
|
||||
localparam LED_TX_RED_SIZE = 1; //CH_LED_ATR:LED_TX_RED
|
||||
localparam LED_TX_RED_MSB = 1; //CH_LED_ATR:LED_TX_RED
|
||||
localparam LED_TX_RED = 1; //CH_LED_ATR:LED_TX_RED
|
||||
localparam LED_RX_GREEN_SIZE = 1; //CH_LED_ATR:LED_RX_GREEN
|
||||
localparam LED_RX_GREEN_MSB = 4; //CH_LED_ATR:LED_RX_GREEN
|
||||
localparam LED_RX_GREEN = 4; //CH_LED_ATR:LED_RX_GREEN
|
||||
|
||||
// CH_PATH_CTRL_ATR Type (from radio_control_regs.sv)
|
||||
localparam CH_PATH_CTRL_ATR_SIZE = 32;
|
||||
localparam CH_PATH_CTRL_ATR_MASK = 32'h3;
|
||||
localparam CH_ENABLE_TXRX_TDR_SIZE = 1; //CH_PATH_CTRL_ATR:CH_ENABLE_TXRX_TDR
|
||||
localparam CH_ENABLE_TXRX_TDR_MSB = 0; //CH_PATH_CTRL_ATR:CH_ENABLE_TXRX_TDR
|
||||
localparam CH_ENABLE_TXRX_TDR = 0; //CH_PATH_CTRL_ATR:CH_ENABLE_TXRX_TDR
|
||||
localparam CH_BYPASS_RX_SIZE = 1; //CH_PATH_CTRL_ATR:CH_BYPASS_RX
|
||||
localparam CH_BYPASS_RX_MSB = 1; //CH_PATH_CTRL_ATR:CH_BYPASS_RX
|
||||
localparam CH_BYPASS_RX = 1; //CH_PATH_CTRL_ATR:CH_BYPASS_RX
|
||||
|
||||
//===============================================================================
|
||||
// Register Group RADIO_CONTROL_REGS
|
||||
//===============================================================================
|
||||
|
||||
// MISC_OUTPUTS Register (from radio_control_regs.sv)
|
||||
localparam MISC_OUTPUTS = 'h0; // Register Offset
|
||||
localparam MISC_OUTPUTS_SIZE = 32; // register width in bits
|
||||
localparam MISC_OUTPUTS_MASK = 32'h3;
|
||||
localparam ADRV9032_RESET_SIZE = 1; //MISC_OUTPUTS:ADRV9032_RESET
|
||||
localparam ADRV9032_RESET_MSB = 0; //MISC_OUTPUTS:ADRV9032_RESET
|
||||
localparam ADRV9032_RESET = 0; //MISC_OUTPUTS:ADRV9032_RESET
|
||||
localparam ADRV9032_TEST_EN_SIZE = 1; //MISC_OUTPUTS:ADRV9032_TEST_EN
|
||||
localparam ADRV9032_TEST_EN_MSB = 1; //MISC_OUTPUTS:ADRV9032_TEST_EN
|
||||
localparam ADRV9032_TEST_EN = 1; //MISC_OUTPUTS:ADRV9032_TEST_EN
|
||||
|
||||
// MISC_INPUTS Register (from radio_control_regs.sv)
|
||||
localparam MISC_INPUTS = 'h4; // Register Offset
|
||||
localparam MISC_INPUTS_SIZE = 32; // register width in bits
|
||||
localparam MISC_INPUTS_MASK = 32'h3;
|
||||
localparam ADRV_INTERRUPT_0_SIZE = 1; //MISC_INPUTS:ADRV_INTERRUPT_0
|
||||
localparam ADRV_INTERRUPT_0_MSB = 0; //MISC_INPUTS:ADRV_INTERRUPT_0
|
||||
localparam ADRV_INTERRUPT_0 = 0; //MISC_INPUTS:ADRV_INTERRUPT_0
|
||||
localparam ADRV_INTERRUPT_1_SIZE = 1; //MISC_INPUTS:ADRV_INTERRUPT_1
|
||||
localparam ADRV_INTERRUPT_1_MSB = 1; //MISC_INPUTS:ADRV_INTERRUPT_1
|
||||
localparam ADRV_INTERRUPT_1 = 1; //MISC_INPUTS:ADRV_INTERRUPT_1
|
||||
|
||||
// CH0_LED_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH0_LED_ATR = 'h10; // Register Offset
|
||||
localparam CH0_LED_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_LED_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH0_LED_STATUS = 'h18; // Register Offset
|
||||
localparam CH0_LED_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_LED_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH1_LED_ATR = 'h20; // Register Offset
|
||||
localparam CH1_LED_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_LED_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH1_LED_STATUS = 'h28; // Register Offset
|
||||
localparam CH1_LED_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_FP_GPIO_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH0_FP_GPIO_ATR = 'h30; // Register Offset
|
||||
localparam CH0_FP_GPIO_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_FP_GPIO_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH0_FP_GPIO_STATUS = 'h38; // Register Offset
|
||||
localparam CH0_FP_GPIO_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_FP_GPIO_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH1_FP_GPIO_ATR = 'h40; // Register Offset
|
||||
localparam CH1_FP_GPIO_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_FP_GPIO_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH1_FP_GPIO_STATUS = 'h48; // Register Offset
|
||||
localparam CH1_FP_GPIO_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_ADRV_GPIO_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH0_ADRV_GPIO_ATR = 'h50; // Register Offset
|
||||
localparam CH0_ADRV_GPIO_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_ADRV_GPIO_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH0_ADRV_GPIO_STATUS = 'h58; // Register Offset
|
||||
localparam CH0_ADRV_GPIO_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_ADRV_GPIO_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH1_ADRV_GPIO_ATR = 'h60; // Register Offset
|
||||
localparam CH1_ADRV_GPIO_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_ADRV_GPIO_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH1_ADRV_GPIO_STATUS = 'h68; // Register Offset
|
||||
localparam CH1_ADRV_GPIO_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_PATH_CTRL_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH0_PATH_CTRL_ATR = 'h70; // Register Offset
|
||||
localparam CH0_PATH_CTRL_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH0_PATH_CTRL_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH0_PATH_CTRL_STATUS = 'h78; // Register Offset
|
||||
localparam CH0_PATH_CTRL_STATUS_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_PATH_CTRL_ATR Register (from radio_control_regs.sv)
|
||||
localparam CH1_PATH_CTRL_ATR = 'h80; // Register Offset
|
||||
localparam CH1_PATH_CTRL_ATR_SIZE = 32; // register width in bits
|
||||
|
||||
// CH1_PATH_CTRL_STATUS Register (from radio_control_regs.sv)
|
||||
localparam CH1_PATH_CTRL_STATUS = 'h88; // Register Offset
|
||||
localparam CH1_PATH_CTRL_STATUS_SIZE = 32; // register width in bits
|
||||
15
fpga/usrp3/top/b300/setupenv.sh
Normal file
15
fpga/usrp3/top/b300/setupenv.sh
Normal file
@ -0,0 +1,15 @@
|
||||
#!/bin/bash
|
||||
|
||||
VIVADO_VER=2021.1
|
||||
VIVADO_VER_FULL=2021.1_AR76780
|
||||
DISPLAY_NAME="USRP-B310"
|
||||
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
|
||||
|
||||
declare -A PRODUCT_ID_MAP
|
||||
PRODUCT_ID_MAP["B310"]="kintex7/xc7k325t/fbg676/-1"
|
||||
|
||||
# Set default part for simulation
|
||||
export ARCH=kintex7
|
||||
export PART_ID="xc7k325t/fbg676/-1"
|
||||
|
||||
source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh
|
||||
70
fpga/usrp3/top/b300/yaml_include/b310_radio_base.yml
Normal file
70
fpga/usrp3/top/b300/yaml_include/b310_radio_base.yml
Normal file
@ -0,0 +1,70 @@
|
||||
#
|
||||
# Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
# General parameters
|
||||
# -----------------------------------------
|
||||
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
|
||||
copyright: >- # Copyright information used in file headers
|
||||
Copyright 2026 Ettus Research, a National Instruments Brand
|
||||
license: >- # License information used in file headers
|
||||
SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
stream_endpoints:
|
||||
ep0: # Stream endpoint name
|
||||
ctrl: True # Endpoint passes control traffic
|
||||
data: True # Endpoint passes data traffic
|
||||
buff_size_bytes: 262144 # Ingress buffer size for data
|
||||
ep1:
|
||||
ctrl: False
|
||||
data: True
|
||||
buff_size_bytes: 262144
|
||||
|
||||
# A list of all NoC blocks in design
|
||||
# ----------------------------------
|
||||
noc_blocks:
|
||||
duc0: # NoC block name
|
||||
block_desc: 'duc.yml' # Block device descriptor file
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
ddc0:
|
||||
block_desc: 'ddc.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
radio0:
|
||||
block_desc: 'radio.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
EN_COMP_GAIN_TX: 1
|
||||
EN_COMP_GAIN_RX: 1
|
||||
|
||||
# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect
|
||||
# - srcport = Port on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Port on the destination block to connect
|
||||
connections:
|
||||
# BSP Connections
|
||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
|
||||
0
host/tests/devtest/multi_usrp_test.py
Executable file → Normal file
0
host/tests/devtest/multi_usrp_test.py
Executable file → Normal file
Loading…
Reference in New Issue
Block a user