Commit Graph

12141 Commits

Author SHA1 Message Date
Javier Valenzuela
9c3959cdb0 fpga: b310: add synchronizers on async inputs 2026-08-19 11:42:54 -05:00
Max Köhler
87ee25d152 fpga: tools: exclude xsim kernel panic testbenches 2026-08-19 10:38:38 -05:00
Max Köhler
e503aaff88 fpga: tools: capture xsim fatal error in testbench execution 2026-08-19 10:38:38 -05:00
Javier Valenzuela
1c0dfa23d8 fpga: b310: update LMK_SYNC constraint 2026-08-18 12:39:10 -05:00
Javier Valenzuela
ed156ae6cf fpga: b310: removing stale comment 2026-08-18 12:39:10 -05:00
Abhishek Verma
99a05593d8 mpm: import no_claim in e31x
no_claim decorator was recently added in method
get_device_info_dyn() but it was missed to get imported from
usrp_mpm.rpc_utils which causes device initialize failure.
2026-08-17 11:01:17 +02:00
Javier Valenzuela
8676b3e257 fpga: b310: remove vhook comments 2026-08-14 16:33:50 -05:00
Javier Valenzuela
a9aed26306 fpga: lib: move ctrlport_to_jtag to lib sirectory 2026-08-14 16:32:09 -05:00
Javier Valenzuela
c17c6a4c3a fpga: b310: update jtag prescalar 2026-08-14 16:31:15 -05:00
Javier Valenzuela
8745af720e fpga: b310: add CPLD jtag constraints 2026-08-14 16:31:15 -05:00
Marian Koop
556b378912 Prepare for 4.11.0.0 RC1 2026-08-12 18:25:49 +02:00
Marian Koop
fdb3a497a5 debian: Add licenses for b310 sources 2026-08-12 18:25:49 +02:00
Marian Koop
4d0c9c8dfd ci: docker: Revert docker build improvements 2026-08-12 18:24:38 +02:00
Niels Garibaldi
c20e60a594 fpga: duc: only include TS in first packet of burst
For the multisample version of the DUC block, in order
to align with the singlesample behavior this changes the packet
generation in axi_rate_change_ms to only include the timestamp in
the first packet of each burst.
2026-08-11 10:47:57 +02:00
Niels Garibaldi
d91c2293d1 fpga: rfnoc: add TS-on-first-only option to axi_rate_change_ms
Add a parameter to the axi_rate_change_ms module called
EN_TIME_ALL_PKTS.
Set to 1, the module will calculate timestamps
for all packets of the output burst.
Set to 0, the module will only insert a timestamp in the first
pkt of each generated output burst.
2026-08-11 10:47:57 +02:00
Grant Meyerhoff
45ea2365b1 cores: restrict spi_core_adrv build for b300 2026-08-11 01:16:12 +02:00
Javier Valenzuela
9849f85918 fpga: b310: removed unused revision reg 2026-08-10 17:06:59 -05:00
Javier Valenzuela
984bc86793 fpga: b300: update jesd signal naming 2026-08-10 17:06:01 -05:00
Wade Fife
4a9b264b86 fpga: lib: Fix double driver in clocking_watchdog_tb 2026-08-10 17:03:45 -05:00
mhallada
e90b0b4643 fpga: Ensure constant initial phase of dds phase accumulator
between bursts

Reload the phase accumulator (with registered phase increment)
in dds_ms at EoB to maintain constant initial phase between bursts
2026-08-10 23:12:25 +02:00
Wade Fife
76ddd382f9 docs: fpga: Update simulator install location 2026-08-10 16:05:30 -05:00
Wade Fife
1bafc03e08 fpga: tools: Add simulator install locations 2026-08-10 16:05:30 -05:00
Grant Meyerhoff
00826ca054 adrv9032: fix licensing notices 2026-08-10 22:56:24 +02:00
Abhishek Verma
3ec3ea3ef6 host: add missing rpc cmds in proto file
- add missing x4xx rpc cmds in proto file
- add missing n3xx rpc cmds in proto file
2026-08-10 22:52:19 +02:00
Lars Amsel
dd7607fc17 ci: add 800 MHz X440 images to pipeline builds 2026-08-10 17:21:47 +02:00
Lars Amsel
30a4b7fc2b fpga: x440: add 800 MHz images 2026-08-10 17:21:47 +02:00
Lars Amsel
33a0dc16bd fpga: add clock watch circuit 2026-08-10 17:21:47 +02:00
Jörg Hofrichter
2618b51cb8 host: mpmd based uhd_image_loader: fallback to .bin file
If the expected FPGA image with .bit file ending is not available,
try with .bin file ending.

Co-authored-by: Lars Amsel <lars.amsel@emerson.com>
2026-08-10 16:40:53 +02:00
Jörg Hofrichter
aa2665d6f4 mpm: print error if loading FPGA bitstream failed 2026-08-10 16:40:53 +02:00
Jörg Hofrichter
752b878a08 mpm: tlv_eeprom: added eeprom IDs for X4XX L variants 2026-08-10 16:40:53 +02:00
Jörg Hofrichter
d46c011757 mpm: tlv_eeprom: print addtl. info in eeprom-id 2026-08-10 16:40:53 +02:00
Jörg Hofrichter
6284863e14 mpm: handle bootgen generated .bin files
- Verify signature in case the device does not support customizable
  FPGA (just as sanity check before actual loading the bitstream).
- Extract the bitstream from the bootgen generated .bin file
  otherwise.
2026-08-10 16:40:53 +02:00
Jörg Hofrichter
d4828aa208 mpm: add bootgen_wrapper script
Provide the following two functions by wrapping the "bootgen"
command line tool:

verify: verify the validity of the signature of the .bin file.

extract_bitstream: extract the FPGA bitstream from the .bin file.
This works if the .bin file includes the FPGA bitstream as a
single partition.
2026-08-10 16:40:53 +02:00
Jörg Hofrichter
eb21a19deb mpm: expose customizable_fpga flag 2026-08-10 16:40:53 +02:00
Jörg Hofrichter
4bf18365d8 mpm: support new L variants in x4xx_update_cpld 2026-08-10 16:40:53 +02:00
Jörg Hofrichter
294ced36f6 mpm: x4xx: l device only supports "bin" file extension for FPGA 2026-08-10 16:40:53 +02:00
Jörg Hofrichter
a58a06f50c mpm: x4xx: add l variant PIDs 2026-08-10 16:40:53 +02:00
Max Köhler
09b0346838 ci: fpga: change demand to super high CPU per thread 2026-08-10 14:35:48 +02:00
Grant Meyerhoff
7a0a5f8085 b300: search for FPGA images if not provided 2026-08-10 14:11:49 +02:00
Marian Koop
0b47148652 ci: docker: Improve windows docker build speed and stability
- Limit vcpkg port creation to release targets
- Re-use vcpkg cache for PR and during week in CI builds
- Merge vc2022 dockerfiles into single source
2026-08-10 09:51:18 +02:00
Marian Koop
82fb06bfe9 ci: docker: Enable support for partial docker pipelines
- add optional --empty-on-error-non-ci to derive_docker_image_matrix.py
  to downgrade derivation errors to warnings in non-strict builds
- handle partial DockerImageNames inputs by tolerating missing/empty
  source matrices and returning {} when fallback mode is active
- refactor matrix unit tests to be artifact-driven and non-strict
  outside CI (warn/skip instead of fail)
- keep strict failure behavior for CI reasons, while allowing fallback
  in manual and PR runs
2026-08-10 09:51:18 +02:00
Marian Koop
a3d8778a84 ci: Improve pipeline unit test test_derive_docker_image_matrix 2026-08-10 09:51:18 +02:00
Marian Koop
943692b9c7 ci: hardware dev test: Add sbom upload stage 2026-08-10 08:56:35 +02:00
Marian Koop
2788ac9e6d ci: Integrate SBOM upload stage into mono pipeline stage list 2026-08-10 08:56:35 +02:00
Marian Koop
0fd2f32cb8 doc: Mention B310 in release highlights 2026-08-10 08:46:44 +02:00
Frank Dietze
72bac0df60 ci: streaming: b310: cleanup implementation 2026-08-10 08:44:34 +02:00
mhallada
6883bb4d39 host: Fix NIPC calculation in ddc/duc
Computed NIPC values now resolve to 1 for
RF_BW < 200 MHz and the workaround in X410_X4_100
bitfile to ensure correct NIPC has been reverted.
2026-08-10 08:38:01 +02:00
Niels Garibaldi
f60ae0e17d doc: add Wideband DDC/DUC information to changelog 2026-08-05 08:43:42 +02:00
Niels Garibaldi
a1f558f16a fpga: add wideband ddc and duc blocks to default fpga images
Adding the RFNoC DDC and DUC blocks to our shipping bitfiles.

The new wideband DxC implementation allow processing input/output
rates up to a maximum of 2000MSps.
This commit adds the DDC/DUC blocks to some of our shipping
bitfiles for all channels.

Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com>
Co-authored-by: André Zoch <andre.zoch@emerson.com>
Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
2026-08-05 08:43:42 +02:00
Niels Garibaldi
66769905bb fpga: x400 add faster ce_clk variant
Add a new faster ce clock called fast_ce to x4xx that runs at
333.33MHz.

Co-authored-by: Max Köhler <max.koehler@emerson.com>
2026-08-05 08:43:42 +02:00