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b300: search for FPGA images if not provided
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0b47148652
commit
7a0a5f8085
@ -13,14 +13,20 @@
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#include <uhd/image_loader.hpp>
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#include <uhd/types/byte_vector.hpp>
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#include <uhd/utils/log.hpp>
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#include <uhd/utils/paths.hpp>
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#include <uhd/utils/static.hpp>
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#include <uhdlib/usrp/cores/i2c_core_100_wb32.hpp>
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#include <algorithm>
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#include <cctype>
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#include <chrono>
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#include <filesystem>
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#include <fstream>
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#include <thread>
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namespace {
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constexpr const char* DEFAULT_FPGA_TYPE = "replay";
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}
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namespace uhd { namespace usrp { namespace b300 {
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static const uint32_t READ_DATA_DATA_VALID = (1 << 31);
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@ -682,10 +688,47 @@ static bool b300_image_loader(const image_loader::image_loader_args_t& image_loa
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if (devs.empty())
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return false;
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else if (devs.size() > 1) {
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std::string err_msg =
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"Could not resolve given args to a single B3xx-Series device.\n"
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"Applicable devices:\n";
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if (not std::filesystem::exists(image_loader_args.fpga_path)) {
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throw uhd::runtime_error(
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"Could not find image at path " + image_loader_args.fpga_path);
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for (const uhd::device_addr_t& dev : devs) {
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err_msg += " * " + dev.get("product", "b3xx")
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+ " (resource=" + dev.get("resource") + ")\n";
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}
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err_msg += "\nSpecify one of these devices with the given args to load an image "
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"onto it.";
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throw uhd::runtime_error(err_msg);
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}
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std::string fpga_path_to_program = image_loader_args.fpga_path;
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if (!image_loader_args.fpga_path.empty()) {
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if (not std::filesystem::exists(image_loader_args.fpga_path)) {
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throw uhd::runtime_error(
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"Could not find image at path " + image_loader_args.fpga_path);
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}
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} else {
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std::string product_name = devs[0].get("product", "UNKNOWN");
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std::transform(product_name.begin(),
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product_name.end(),
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product_name.begin(),
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[](unsigned char c) { return static_cast<char>(std::tolower(c)); });
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if (product_name == "unknown") {
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throw uhd::runtime_error(
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"Could not determine product name for the device. "
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"Please either ensure the mb eeprom is programmed correctly "
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"using the usrp_burn_mb_eeprom utility, or provide the FPGA path to "
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"program explicitly with the '--fpga-path' argument.");
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}
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fpga_path_to_program = uhd::find_image_path(
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"usrp_" + product_name + "_fpga_"
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+ image_loader_args.args.get("fpga", DEFAULT_FPGA_TYPE) + ".bit");
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}
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for (size_t i = 0; i < devs.size(); ++i) {
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@ -696,7 +739,7 @@ static bool b300_image_loader(const image_loader::image_loader_args_t& image_loa
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b300_image_loader_helper image_loader_helper(
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[pcie_mgr](uint32_t addr) { return pcie_mgr->peek32(addr); },
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[pcie_mgr](uint32_t addr, uint32_t value) { pcie_mgr->poke32(addr, value); });
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image_loader_helper.writeBinToFlash(image_loader_args.fpga_path);
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image_loader_helper.writeBinToFlash(fpga_path_to_program);
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}
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return true;
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