RFNoC's `multi_usrp` did not fully propagate `set_master_clock_rate()`
to the DUC/DDC chain.
Before this change, `set_master_clock_rate()` updated only the radio
rate. If a channel had a DUC or DDC, the adjacent converter rate was
left stale:
- TX: the DUC output rate was not updated to the new radio rate
- RX: the DDC input rate was not updated to the new radio rate
That caused follow-up `set_tx_rate()` / `set_rx_rate()` calls on the
same `multi_usrp` object to operate on outdated DUC/DDC state. In
practice, after changing the master clock, setting the channel sample
rate could be coerced unexpectedly because interpolation/decimation was
derived from the old converter-side rate.
This change updates `multi_usrp_rfnoc` so that `set_master_clock_rate()`:
- propagates the new radio rate to the attached DUC/DDC
- reapplies the previously requested per-channel TX/RX rate so the
DUC/DDC continues to follow the user-requested sample rate
Note that property propagation by itself is insufficient here, because
multi_usrp_rfnoc caches RX and TX rates, and these caches require
manual updating.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Use a resources file to pass RFNoC OOT source files to Vivado TCL
scripts, avoiding ARG_MAX argument list limits.
This makes B310 consistent with other USRPs that were previously
updated in commit fa7c3604.
Use --seed only to initialize a local deterministic random number
generator. Generate a new signed 32-bit BUILD_SEED for each FPGA build
attempt instead of passing --seed directly to the first build. This
avoids accidentally using sequential pipeline attempt numbers as
BUILD_SEED values.
Using the same --seed produces the same BUILD_SEED sequence, preserving
reproducibility.
Added a state machine to fix a bug in the temporal decimation code
of the decimating halfband filter module.
Additionally added a testcase to the testbench for the issue this
change is fixing.
Reversing the order of the barrel shifter module used by the CIC
filter implementations, in order to reduce the possible bits
selectable from the last stage going into the rounding module.
This should make routing easier.
We can reduce the bus width of the comb filter stage in the CIC
interpolation filter, as it is the first module in the CIC filter and
only adds one bit per order stage. Therefore, we do not need to
immediately go to the full accumulation bit width needed for the later
integrator stages of the CIC interpolation filter, and can save some
FPGA resources by only extending to the required width for each CIC
stage.
The same logic also applies to the interpolation stage, which only adds
zeros into the bitstream and therefore does not change the bus width.
Adding a FIFO size module parameter to the comb filter module, in
order to selectively set only the last of N-order filter stages to
use a 2-stage FIFO.
Install nib310rio-dev before configuring the Fedora RPM installer build.
The RPM path runs CMake directly in the build container, so installing the
development package there makes nib310rio/nib310rio.h available when UHD
decides whether to enable B300 support.
Add nib310rio-dev to the Debian build dependencies so the UHD package
build fails if the B310 userspace header is unavailable instead of
silently disabling B300 support.
The Ubuntu installer pipeline downloads the nib310rio Debian package
artifact and exposes it to pbuilder as a local apt repository. This lets
pbuilder satisfy the new dependency inside the clean build root where
CMake checks for nib310rio/nib310rio.h.
Because X440 images now can also contain DDC/DUC we cannot direct
connect the radio with the replay block anymore. Instead we have
to rely on the uhd.rfnoc util connect_through_blocks function
which will find a route through the statically connected DDC/DUC
if they are present or connect the SEPs directly if they are not.
rfnoc_rx_replay_samples_to_file.py could hang and then abort with
"Timeout while loading replay buffer!" whenever the requested sample
rate was not an integer divisor of the master clock rate. For example,
requesting 200 Msps at an MCR of 368.64 MHz would leave the record
buffer stuck at exactly 50% fullness.
Two problems combined to cause this:
First, the rate was read back from the DDC before the graph was
committed. At that point the DDC's input sample rate property is not
yet valid, so set_output_rate() falls back to setting the output edge
property and returns the uncoerced, requested rate. The example then
reported a rate that the DDC never actually applied.
Second, run_capture() derived the number of samples to request from the
radio with int(radio_rate / rate), truncating instead of rounding. With
a radio rate of 368.64 Msps and a nominal rate of 200 Msps this yielded
a ratio of 1 rather than the decimation the DDC had actually settled on,
so the radio was told to produce only half the samples needed to fill
the record buffer.
The rate is now read back with get_output_rate() after graph.commit(),
when property propagation has completed, and the user is warned when
the requested rate had to be coerced. The rate ratio is computed with
rounding, so the radio is asked for the full number of samples the
record buffer needs.
While here, fix two related issues in the readback path. The DDC port
is now taken from the destination port of the discovered edge rather
than assuming it matches the radio channel index, and the rate is read
per channel (from the DDC where one is present, otherwise from the
radio) so that chains without a DDC are not ignored. Rates are compared
against a tolerance rather than for exact float equality.
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
