Commit Graph

12300 Commits

Author SHA1 Message Date
Max Köhler
dad6f906f9 fpga: remove X420 variants without DDC/DUC 2026-10-06 08:54:58 +02:00
Ahmed Salman
54f185ecdd ci: x420: add weekly hardware test coverage 2026-10-06 08:51:20 +02:00
Frank Dietze
e4672044f9 ci: Windows installer: add retry to checkout 2026-10-05 16:43:49 +02:00
Martin Braun
0cf40c3276 rfnoc_image_builder: Fix .grc builds for empty params
Some blocks (e.g., the fosphor block) don't have parameters in their
respective YAMLs, but the GRC file importer makes the assumption that
there are always parameters, and will crash on a faulty dictionary
lookup when that's not the case. This conditionally checks parameters,
making the lack of parameters non-fatal.
2026-10-05 15:04:22 +02:00
Max Köhler
8ad3b4961d ci: fpga: refactor IP cache 2026-10-05 09:05:39 +02:00
Javier Valenzuela
5709e8b546 fpga: lib: adjust ctrlport_to_wb_uart signal width 2026-10-01 13:02:57 -05:00
Martin Anderseck
1907032f7b firmware: Add descriptors for B2xx mini variants
The current firmware missed descriptors for B200-mini and
B205-mini. Added the missing descriptors.

Also this commit ammends the firmware howto. It specifies
the SDK version we are using as well as some additional
command applied to the SDK files to make the patch successful.

Co-authored-by: Lars Amsel <lars.amsel@emerson.com>
2026-09-30 11:54:00 +02:00
Martin Anderseck
155dfbf352 fx3: Upgrade B2xx build
This is an upgrade to the latest FX3 SDK (1.3.5) and to the ARM gcc in
version 15.3.rel1 for the build of the B2xx firmware and bootloader. All
required steps are explained in the updated readme file.
Additionally, some bounds checks were added both in the firmware and the
bootloader, as well as some more validations and checks to prevent over-
and underflows. Newly introduced checks were documented in the code.
2026-09-30 11:54:00 +02:00
Max Becker
416988b3b6 docs: Document X4xx GPIO SPI support
Document the updated X4xx GPIO SPI interface and transaction-width
behavior.
2026-09-29 13:12:32 +02:00
Max Becker
3ed25c39c7 host: Complete X4xx GPIO SPI support
Update the X4xx SPI core, radio-control integration, examples, and
tests for transactions up to 64 bits and the revised register map.
2026-09-29 13:12:32 +02:00
Max Becker
b1e4016c2b mpm: Update X4xx GPIO SPI support
Update MPM GPIO handling for the updated X4xx GPIO SPI register
interface.

Require the FPGA compatibility number bump introduced with the new
SPI support so MPM does not operate against an incompatible FPGA image.

Bump MPM compat number.
2026-09-29 13:12:32 +02:00
Max Becker
148c861163 host: Extend the SPI interface
Introduce 64-bit SPI transaction methods into the common spi_iface API,
default implementation throws an uhd::unsupported_operation exception.
Add explicit 32-bit aliases for the old/existing SPI transactions
methods.

Expose the width-specific operations through the RFNoC Python bindings.
2026-09-29 13:12:32 +02:00
Max Becker
e6470cf8ce fpga: x4xx: Extend GPIO SPI support
Extend GPIO SPI transactions up to 64 bits and update the X4xx FPGA
register map and RTL to support the new access width.
Migrate the GPIO SPI register definitions to SystemVerilog.

Add testbench for X4xx GPIO SPI module covering both exisiting
32bit functionality and added 64bit functionality.
Separate TB Makefiles for X4xx and X410 implementation variant.

Bump the FPGA compatibility number so host and MPM software can reject
images that do not provide the required GPIO SPI register interface.
2026-09-29 13:12:32 +02:00
Max Becker
772e682503 fpga: Update SPI simulation testbenches
Extend the SPI slave model to propagate simulation failures to the test
execution framework.

Extract the timing monitor from the control-port SPI testbench so it
can be shared by the GPIO SPI simulations while keeping timing checks
centralized and consistent.
2026-09-29 13:12:32 +02:00
Max Becker
440ed5ae76 fpga: tools: Fix --CHECK image build flag
Fix CHECK_VIVADO_DESIGN make target.
This fixes the --CHECK target/argument for available in the rfnoc_image_builder
2026-09-29 10:52:44 +02:00
Roman Pope
ec86cd7b2c lib: Fix lost wakeup in msg_task startup
msg_task_impl's constructor waits on _start_cv until _running is set,
checking the predicate under _mutex. task_loop() set _running and
called notify_one() without taking _mutex, so a notification sent
after the constructor had checked the predicate but before it started
to wait was lost, and the constructor then blocked forever.

The condition-variable handshake replaced a boost::barrier, which
cannot lose a wakeup, in 3855516f6f ("lib: Remove boost::thread usage
from USB transports"), so UHD 4.10.0.0 and 4.11.0.0 are affected. On
a B210 the hang leaves b200_impl's constructor blocked in
msg_task::make() right after "Operating over USB 3.". It shows up
most when the device is opened at a real-time priority, as SDR
applications that raise their priority before opening the device do.

Set _running while holding _mutex, then notify.
2026-09-29 10:49:42 +02:00
Ryan Volz
7a44637627 cmake: Add missing log_add_impl.hpp to distributed headers
This is a new header for v4.11, referenced by the existing log.hpp and
log_add.hpp public headers.

Signed-off-by: Ryan Volz <ryan.volz@gmail.com>
2026-09-29 10:47:51 +02:00
Max Köhler
65b9c0270e fpga: Upgrade to Vivado 2025.2: Repair all testbenches 2026-09-29 09:09:08 +02:00
Max Köhler
81c53bed91 fpga: ci: Replace modelsim with questasim 2026-09-29 09:09:08 +02:00
Max Köhler
0df07dcde8 fpga: Upgrade to Vivado 2025.2: Repair all FPGA compiles 2026-09-29 09:09:08 +02:00
Max Köhler
f3d6cd6c01 fpga: b300: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
4e8fa298dd fpga: n3xx: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
2a036118de fpga: e320: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
f8240b6871 fpga: e31x: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
91ae70080e fpga: x300: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
31ff7ce148 fpga: x400: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
1e80ef2fe9 fpga: lib: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
edac52a8d9 fpga: tools: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Max Köhler
626bcb32ea ci: Upgrade to Vivado 2025.2 2026-09-29 09:09:08 +02:00
Javier Valenzuela
34a43948aa fpga: b310: add synchronizers on async inputs 2026-09-28 23:35:16 -05:00
Javier Valenzuela
ef0a814a3d fpga: lib: fixup uart non-blocking assignments 2026-09-24 08:56:44 +02:00
Javier Valenzuela
7351887ab5 fpga: lib: fixup i2c non-blocking assignments 2026-09-24 08:56:44 +02:00
Javier Valenzuela
04a7f8c6bf fpga: lib: fixup simple_uart instantiation 2026-09-24 08:56:44 +02:00
Grant Meyerhoff
c6e4c50945 tests: replace .format() usage with f-strings 2026-09-22 15:19:41 +02:00
mhallada
9f8defc537 ci: Enable EVM test for x410-x4-400 pipeline job 2026-09-22 15:18:50 +02:00
Grant Meyerhoff
66c66a4d2b devtest: use tx eob ack timeout for benchmark_rate 2026-09-22 15:13:03 +02:00
Grant Meyerhoff
4eeee62aad examples: optionally wait for Tx EOB on benchmark_rate 2026-09-22 15:13:03 +02:00
Grant Meyerhoff
8720fe87ec ci: download b3xx images rather than hardcoding 2026-09-22 10:00:45 +02:00
Abhishek Verma
633782b405 rpc_server: return UNAVAILABLE for RPCs during device reset
Treat a RuntimeError raised while the periph manager is resetting as
transient. Log once at WARNING and abort with gRPC status UNAVAILABLE
so the client retries, instead of logging a scary ERROR.
Real runtime errors still log ERROR and abort when periph manager
object is live.
2026-09-18 16:18:00 +01:00
Max Köhler
3fe3610eb8 fpga: ci: add b310 option to FPGA pipeline 2026-09-18 16:16:53 +01:00
Max Köhler
3f46b68c6d fpga: lib: disable clocks at startup for ddc_ms_tb 2026-09-18 16:15:40 +01:00
Grant Meyerhoff
50a47f75de b300: fix GPS timepulse polarity 2026-09-18 16:14:09 +01:00
Abhishek Verma
6e11078807 mpm: net.py: optimize netlink ops to fix RPC starvation
usrp_hwd runs all gRPC greenlets on a single gevent hub, so any
non-yielding C call blocks every other RPC. Under a uhd_find_devices
discovery flood, the GetDeviceInfo interface enumeration run long enough
And may starve most claimed RPC past its default 2s client deadline,
causing "Deadline Exceeded" failures.

Three places that this commit optimizes, all in net.py:

- get_local_ip_addrs() used pyroute2 IPDB, which spawns helper threads
  and mirrors the full link/addr/route/neighbour tables on every call
  (~100s of ms, non-yielding) --> Replace it with a single stateless
  IPRoute get_addr() dump. Keep IFA_LOCAL (falling back to IFA_ADDRESS)
  so the returned set matches IPDB's behaviour, including point-to-point
  links.

- get_link_speed() used to create a new pyudev.Context() per interface,
  which forks on creation, tripping gRPC's fork handlers. gRPC then
  freezes all workder threads and restarts after fork is done. Fix is to
  reuse one PID-guarded pyudev context per process.

- get_valid_interfaces() did an O(N) netlink round-trip per interface.
  This stalls gRPC server. --> Dump all links and IPv4 addresses once
   and filter in Python.

IPRoute stays per-call: it opens its own netlink socket and does not
fork, so there is no shared state to lock.
2026-09-18 16:12:41 +01:00
Max Köhler
cf14224aa6 fpga: tools: skip phy_opt step for partially routed designs 2026-09-18 16:08:29 +01:00
Max Köhler
ec32eb04ec ci: do not use publish permission for usrp4-hw 2026-09-18 16:07:14 +01:00
Max Köhler
a76ab6ffc9 Revert "ci: usrp4 sim: only run this stage if source is not master"
This reverts commit 879ed08bb1.
2026-09-18 16:07:14 +01:00
Max Köhler
99fe17071f image builder: find FPGA path from Git repository root 2026-09-18 16:05:51 +01:00
TalFel
2feedf3338 multi_usrp: set_master_clock_rate function now sets duc/ddc rates
RFNoC's `multi_usrp` did not fully propagate `set_master_clock_rate()`
to the DUC/DDC chain.

Before this change, `set_master_clock_rate()` updated only the radio
rate. If a channel had a DUC or DDC, the adjacent converter rate was
left stale:
- TX: the DUC output rate was not updated to the new radio rate
- RX: the DDC input rate was not updated to the new radio rate

That caused follow-up `set_tx_rate()` / `set_rx_rate()` calls on the
same `multi_usrp` object to operate on outdated DUC/DDC state. In
practice, after changing the master clock, setting the channel sample
rate could be coerced unexpectedly because interpolation/decimation was
derived from the old converter-side rate.

This change updates `multi_usrp_rfnoc` so that `set_master_clock_rate()`:
- propagates the new radio rate to the attached DUC/DDC
- reapplies the previously requested per-channel TX/RX rate so the
  DUC/DDC continues to follow the user-requested sample rate

Note that property propagation by itself is insufficient here, because
multi_usrp_rfnoc caches RX and TX rates, and these caches require
manual updating.

Co-authored-by: Martin Braun <martin.braun@ettus.com>
2026-09-18 15:51:09 +01:00
Frank Dietze
a48ccdb0a0 ci: mutex_hardware: remove vivado_dir parameter 2026-09-17 18:40:18 +02:00
Frank Dietze
2fa91b605a ci: replace static obx rftest parameters by variables 2026-09-17 18:40:18 +02:00