Adds a direct MMCM output for the quarter rfdc_clk.
Additionally, all other consumers of the rfdc_clk and rfdc_clk_2x
receive their clock from the MMCM output directly instead of
the clock buffers. Thus, making the clock buffers obsolete and
removing them from the design.
no_claim decorator was recently added in method
get_device_info_dyn() but it was missed to get imported from
usrp_mpm.rpc_utils which causes device initialize failure.
For the multisample version of the DUC block, in order
to align with the singlesample behavior this changes the packet
generation in axi_rate_change_ms to only include the timestamp in
the first packet of each burst.
Add a parameter to the axi_rate_change_ms module called
EN_TIME_ALL_PKTS.
Set to 1, the module will calculate timestamps
for all packets of the output burst.
Set to 0, the module will only insert a timestamp in the first
pkt of each generated output burst.
- Verify signature in case the device does not support customizable
FPGA (just as sanity check before actual loading the bitstream).
- Extract the bitstream from the bootgen generated .bin file
otherwise.
Provide the following two functions by wrapping the "bootgen"
command line tool:
verify: verify the validity of the signature of the .bin file.
extract_bitstream: extract the FPGA bitstream from the .bin file.
This works if the .bin file includes the FPGA bitstream as a
single partition.
- add optional --empty-on-error-non-ci to derive_docker_image_matrix.py
to downgrade derivation errors to warnings in non-strict builds
- handle partial DockerImageNames inputs by tolerating missing/empty
source matrices and returning {} when fallback mode is active
- refactor matrix unit tests to be artifact-driven and non-strict
outside CI (warn/skip instead of fail)
- keep strict failure behavior for CI reasons, while allowing fallback
in manual and PR runs
