A missing "else" after 6ea4e48 was causing two configurations to occur
at the same time for some values of SIZE.
This commit also sets the "space" and "occupied" outputs to 0 when in
pass-through mode.
This brings back the package PkgChdrUtils after it was removed in
d9f8c08. Its contents were moved because most of the contents were
synthesizable, but many existing testbenches might still reference the
old package name. This new version of PkgChdrUtils simply imports then
exports the things it used to include. New testbenches are encouraged
to reference the new files instead of PkgChdrUtils.
This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.
This changes the -onfinish setting from "stop" to "final" for Questa
and ModelSim. The "final" setting is required so that SystemVerilog
final blocks run. This also has the same effect as "stop" in that it
won't ask you in the GUI if you want to exit the simulator when
$finish() is called.
This commit addresses several issues that can occur with different
simulators. It changes the following:
- Update documentation
- Ignore testbenches in build-ip folders
- Tolerate extra lines in the testbench results regular expression
- Match numbers using \d instead of + to avoid ValueError exceptions
- Only fetch the start_time if it exists
- Allow any simulator make target (don't limit it to specific choices)
This adds the NIPC parameter, which configures support for processing
multiple items or samples per clock cycle. With this enabled, the FFT
block can process at rates higher than 250 MSPS, such as 500 MSPS and
beyond.
On the CPU to Ethernet path (c2e) in some configurations the trailing
bytes length was not being properly set in TUSER. This can lead to
extra bytes being added onto packets. Most of the time this is fine,
since the extra bytes would be ignored by the underlying protocols.
But when the packet was near the MTU size, it could lead to an
oversized packet that would get dropped by the network or host
computer.
This adapts the CI scripts such that there is a single pipeline (the
"mono" pipeline) which builds both FPGA bitfiles and all of UHD, and
runs the hardware tests.
Note that this change does not load the FPGA bitfiles built in the same
pipeline, which means this change really enables the same behaviour as
before. Consuming bitfiles created in the same pipeline will be phase
2 of this endeavour.
This reverts commit e572bab3ee.
The problem with skipping the "unnecessary" bash wrappers is that Ubuntu
systems use 'dash' as a default shell, which does not support our build
infrastructure. While we do recommend not using dash for building FPGA
builds in our documentation, it's not obvious that dash is the problem
when calling rfnoc_image_builder.
Radio command FIFO will back pressure commands until there is room
for new elements.
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Together with an update to the LMK04832 register config according to
TIs data sheet, all clock outputs are now aligned to SYSREF rising edge.
Therefore, I needed to adjust the SYSREF capture mechanism inside the
RFSoC and the SYSREF LMK Delay.
SYSREF is now captured first at the falling edge of PRC.
To be on the safe side, we are still double synchronizing SYSREF
afterwards on the rising edges of PRC.
As we are now independent of any MCR regarding timing constraints the
SYSREF Delay is also set to '0' for all X4xx devices.
In cases when the info FIFO fills, it was possible for
in_pkt_info_tvalid to be asserted then on the next cycle
in_pkt_info_tready would deassert, in which case the input would be
dropped. This change ensures that tvalid remains asserted until tready
deasserts.
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.
This Python utility was getting a bit rotten. The following updates
where made:
- Reformatted using ni-python-styleguide
- Fixed formatting of regex strings by declaring them 'raw'
- Updated docstrings and any linter issues
On Pyton 3.12 and beyond, this will no longer throw SyntaxError
warnings.
Previously, the build tools for the FPGA bitfiles would try and
autodetect the Vivado executable, but would allow for a `vivado_lab`
executable. However, Vivado Lab Edition can't build bitfiles nor run
testbenches. Its only use with the USRP FPGA build tooling is to run
`viv_jtag_program` and `viv_jtag_list` (which are command-line proxies
for probing FPGAs attached to JTAG, and for programming bitfiles over
JTAG, e.g. to an X3x0).
When Vivado Lab and Vivado were present, it was possible that we ran
into issues where Vivado Labs would be preferred, and then builds or
testbenches would fail.
We therefore remove the ability to use Vivado Lab. Running the Vivado
Lab Edition with the GUI, and loading and probing bitfiles is of course
still possible, but tools like `rfnoc_image_builder` can no longer
accidentally try to use Vivado Lab instead of regular Vivado.
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.
This simplifies image core files by generating a RADIO_NIPC parameter
for the X410, X440 and E31x BSP files. The IO port widths for X410 are
now dynamically widened based on the NIPC value, which is a function of
the RF_BW parameter, and cannot be modified.
The radio block can now read the NIPC value from the BSP, and populate
its spc parameter dynamically. This avoids having to know the right spc
value when writing YAML image core files and reduces redundancy.
This also removes the RADIO_NIPC parameter entirely from all the image
core files. This parameter was fine, but it was a bit confusing because
it referenced a Verilog parameter, which you just had to know was there
in the generated Verilog. By referencing the BSP parameter instead, the
YAML files (BSP, radio.yml, and image core file) are now self-contained
regarding the RADIO_NIPC/spc information.
As a minor upside, the input wire widths for X410's and N310's
rfnoc_image_core.sv module are now generated with the correct widths,
and not, as before, with the worst-case width (and then we assume Vivado
will do the right thing).
... to support custom image core name, example:
rfnoc_image_builder -y n310_rfnoc_image_core.yml -n my_custom_name
The device tree source files were renamed to match the target
name used in the Makefile.
example:
old: dts/usrp_n310_fpga_hg.dts
new: dts/N310_HG.dts
The source file is used to compile the final .dts file in the BUILD_DIR.
example: build-my_custom_name/N310_HG.dts
The final .dts file is copied to the BUILD_OUTPUT_DIR as part of the
post build steps and renamed to the custom image core name.
example: build/my_custom_name.dts
This completes the change that was introduced with commit 2afc66f132.
Adapted changeset analyzer rules change 99865b1, which renamed the
folder host/python/uhd/imgbuilder to host/python/uhd/rfnoc_utils.
This change was made in the "RFNoC OOT overhaul + rfnoc_modtool"
changeset.
Not a functional change. The comments for the replay block in the
crossbar_routes reflect a single replay block, but the FPGA image
actually has two replay blocks with half the number of ports as the
single block design.
The image builder will currently emit a warning if a NoC-block has
unconnected ports. This requires specifying `-W` to continue building,
which is the intended behaviour.
However, there are cases where there are legitimate reasons to not
connect a block, e.g., in the X310, where the radio block has 2x2 ports,
but we only connect 2 RX ports, and 1 TX port.
This adds a way to declare a "null" connection, which makes it explicit
in the image core YAML that a connection was deliberately omitted. Such
connections are created by connecting to a port called "_none_", e.g.:
```
connections:
- { srcblk: _device_, srcport: _none_, dstblk: radio0, dstport: in_1 }
```
The block name is irrelevant, but the schema requires providing a block
name.
This commit also amends the x3xx_radio_base.yml to avoid warnings when
building X3x0 bitfiles.
A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.
This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.
Signed-off-by: Ryan Volz <ryan.volz@gmail.com>
- Removes target names for X3x0 and X4x0 builds (these are now encoded
in the YAML file)
- Change the image core YAML file names referenced in the pipeline YAMLs
to match the contents of fpga/usrp3/top/x?00/*.yml
- Remove X410_XG_100 image since it is not a shipping image
- Add image_core_name arguments for all E320, E31x, N3xx targets
- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
(required for building N3xx BIST images, which use this)
- Bumps FPGA compat from 8.2 to 8.3
- Adds three global motherboard registers to read the 96-bit device DNA
- MPM is updated to read these registers and update the device_info if
compat version 8.3 is available
This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`)
for X440 which allows modules inside the RFNoC image core to access the
FPGA. Note that accessing the PPS signal is generally not required for
RFNoC blocks which require access to timing.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!
This is a huge changeset to the image builder that combines multiple new
features:
- There no longer is a separate edge file for the static router. The
static routes are generated as a Verilog parameter directly into the
rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
endpoints, we can now instantiate arbitrary modules (they also require
a YAML description file).
- To enable such modules, resets are now also tracked the same way that
clock domains are.
- The ImageBuilderConfig config object now more closes matches the
original YAML file. The attributes 'clk_domain_con' and 'block_con' are
removed. Instead, the attributes 'connections' and 'clk_domains' are
sanitized and amended with extra annotations. The templates are
updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
This allows image core files to (recursively) inherit from other image
core files. To do so, simply put an 'inherit' entry at the top of the
file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
the build directory. This requires the usage of rfnoc_image_builder to
build images. As a consequence, it is no longer required to check in
image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
image. Because of the inheritance feature and the requirement to use
the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
transport adapters were inferred from the make target (e.g.,
X410_X4_200 would have four 10GbE links based on the 'X4' substring).
Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
series. Older devices may or may not be ported to allow custom
transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
setting global parameters in the image core files. For example, the
X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
blocks/transport adapter through their YAML files. They do no longer
need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
incorporating RFNoC blocks that require license keys and thus can't
live in an open-source environment. This solution adds the option for
secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
defined in a single file (io_signatures). This file will persist. In
addition each module can add its own IO signature as with the same
format the core IO signatures placed under the top level key
`io_signatures`. IO signatures are still maintained in a global
dictionary. The consequence is that they can be shared among
independent modules as well as they have to have a globally unique
name. The image builder will warn about detected name clashes for the
signatures.
- As a consequence, some less commonly used IO signatures were moved to
their corresponding module YAML files.
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>
The following modifications are applied to allow RFNoC blocks with zero
input- or output ports (or none at all):
- The backend interface will no longer synthesize any flushing logic if
there are no streaming ports
- The Mako templates are modified to allow generating code for blocks
without streaming ports
- The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out
into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the
simulation of such RFNoC blocks
This modifies repeat_fpga_build.py such that it can take a YAML file as
input, not just a make target. It will then use the image builder to
prepare the build and generate a valid make command, which in turn is
used to build FPGA images repeatedly.
It is, in principle, possible to use an external clock to synchronize
N3x0 devices in frequency, and then use a GPSDO for a coarse time
synchronization. This use case is deliberately not supported, as the
GPSDO PPS signal and the external clock signal are by definition not
matched, which will remove any guarantees on time/phase alignment.
Because there are certain, niche use cases where the lack of phase
alignment is acceptable, but only an external clock is available (no
shared external PPS), usage of GPS for generating a PPS signal may be
fine. This patch does not enable the usage of this combination out of
the box, but adds comments and an update to the manual to explain the
risks of this combination, and how to enable it (by patching MPM).
This removes a duplicate code section that causes build warnings. It
also references a wire that gets declared further down and the removed
and remaining code sections were incorrectly indented.
In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.
In several cases, we call `python` explicitly. On many modern operating
systems (e.g., Ubuntu 22.04), this command no longer exists, and if it
does, it's often an alias to python3.
Because the python3 executable has been around for so long, simply
using that directly (instead of, e.g., autodetecting the OS preferences)
is a simple fix that immediately allows building bitfiles, e.g. for the
B2xx series, on more recent OSes.
