ci: Merge FPGA pipelines into mono pipelines

This adapts the CI scripts such that there is a single pipeline (the
"mono" pipeline) which builds both FPGA bitfiles and all of UHD, and
runs the hardware tests.

Note that this change does not load the FPGA bitfiles built in the same
pipeline, which means this change really enables the same behaviour as
before. Consuming bitfiles created in the same pipeline will be phase
2 of this endeavour.

.ci/fpga/devices/job-build-fpga-e31x.yml

@@ -102,8 +102,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.e31x'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.e31x'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_e31x }}', 'true')
                   )
                 )
@@ -153,8 +153,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.e31x'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.e31x'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_e31x }}', 'true')
                   )
                 )

.ci/fpga/devices/job-build-fpga-e320.yml

@@ -82,8 +82,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.e320'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.e320'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_e320 }}', 'true')
                   )
                 )

.ci/fpga/devices/job-build-fpga-n3xx.yml

@@ -188,8 +188,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.n3xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.n3xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_n3xx }}', 'true')
                   )
                 )
@@ -242,8 +242,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.n3xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.n3xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_n3xx }}', 'true')
                   )
                 )
@@ -296,8 +296,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.n3xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.n3xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_n3xx }}', 'true')
                   )
                 )

.ci/fpga/devices/job-build-fpga-x300.yml

@@ -104,8 +104,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x3xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.x3xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_x3x0 }}', 'true')
                   )
                 )
@@ -158,8 +158,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x3xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.x3xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_x3x0 }}', 'true')
                   )
                 )

.ci/fpga/devices/job-build-fpga-x400.yml

@@ -168,8 +168,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x4xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.x4xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_x410 }}', 'true')
                   )
                 )
@@ -232,8 +232,8 @@ stages:
   dependsOn: analyze_changeset
   condition: and( succeeded(),
                   or(
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x4xx'),
-                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.x4xx'),
+                    contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.all'),
                     eq('${{ parameters.build_x440 }}', 'true')
                   )
                 )

.ci/fpga/scripts/run_setup.sh

@@ -32,7 +32,7 @@ echo "---- Run hwsetup ----"
 # This script sets the XILINX_VIVADO, MODELSIM, and LIB_BASE_PATH
 # variables based on the agent's configuration so we can find the EDA
 # tools.
-pushd $BUILD_SOURCESDIRECTORY/uhddev/fpga/.ci/hwtools
+pushd $BUILD_SOURCESDIRECTORY/uhddev/.ci/hwtools
 source hwsetup.sh hwtools=0.1.3
 popd
 

.ci/fpga/templates/job-build-fpga.yml

@@ -74,7 +74,7 @@ jobs:
         # same step as building the bitfile: To avoid having to run hwsetup.sh
         # twice.
         echo "##[group]Setting up build environment..."
-        source $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/run_setup.sh ./
+        source $(Build.SourcesDirectory)/uhddev/.ci/fpga/scripts/run_setup.sh ./
         pip3 install -U numpy mako "ruamel.yaml<0.18.0" jsonschema
         set -o xtrace
         # hwsetup.sh injects garbage cmake versions into PATH, so avoid that by

.ci/fpga/templates/job-build-ip.yml

@@ -70,7 +70,7 @@ jobs:
         BUILD_IP_CACHE_HASH=`cat build-ip/.ci/build-hash`
         echo "BUILD_IP_CACHE_HASH=$BUILD_IP_CACHE_HASH"
         git fetch origin $BUILD_IP_CACHE_HASH
-        bash $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/refresh_ip.sh \
+        bash $(Build.SourcesDirectory)/uhddev/.ci/fpga/scripts/refresh_ip.sh \
           `realpath build-ip/` $BUILD_IP_CACHE_HASH
       workingDirectory: ${{ parameters.directory }}
       # Refresh IP when caching is allowed (clean_build = false) and a cache
@@ -87,7 +87,7 @@ jobs:
       displayName: "Prune IP"
 
     - bash: |
-        source $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/run_setup.sh ./
+        source $(Build.SourcesDirectory)/uhddev/.ci/fpga/scripts/run_setup.sh ./
         make -j ${{ parameters.num_jobs }} ${{ parameters.ip_target }}
         mkdir -p build-ip/.ci/
         git rev-parse --verify HEAD 2>/dev/null 1>build-ip/.ci/build-hash

.ci/fpga/templates/job-run-testbenches.yml

@@ -23,7 +23,7 @@ jobs:
     - template: setup_steps.yml
 
     - bash: |
-        source $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/run_setup.sh ./top/x300
+        source $(Build.SourcesDirectory)/uhddev/.ci/fpga/scripts/run_setup.sh ./top/x300
 
         echo "---- Run testbenches ----"
         pushd ./tools/utils

.ci/templates/fpga_setup_steps.yml

@@ -1,36 +0,0 @@
-parameters:
-  - name: checkoutSteps
-    type: stepList
-    default:
-    # Checkout the repository under test
-    - checkout: self
-      clean: true
-      fetchDepth: 1
-      persistCredentials: true
-    # Checkout hwtools repo
-    - checkout: hwtools
-      fetchDepth: '1'
-      fetchTags: false
-      path: s/hwtools/head
-      persistCredentials: true
-  - name: demands_default
-    type: object
-    default:
-      pool:
-        name: Drivers-NIBuildFarm-RFMIBUILD
-        demands:
-        - Agent.OS -equals Linux
-      hwhookVersion: 2
-
-steps:
-  - template: build/pipelines/helpers/setup_steps.yml@hwtools
-    parameters:
-      caller: setup_steps.yml
-      pool: Drivers-NIBuildFarm-RFMIBUILD
-      checkoutSteps: ${{ parameters.checkoutSteps }}
-      demands: ${{ parameters.demands_default }}
-      repoBase: $(Build.SourcesDirectory)
-      directory: uhddev
-      name: FPGA build
-
-

.ci/templates/job-rfnoc_modtool-test-testbenches.yml

@@ -37,12 +37,12 @@ jobs:
     displayName: List rfnoc_test_oot directory
 
   # Initialize Vivado toolchain
-  - template: fpga_setup_steps.yml
+  - template: ../fpga/templates/setup_steps.yml
 
   - bash: |
       set -x
       # Init toolchain
-      source $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/run_setup.sh $(Build.SourcesDirectory)/uhddev/fpga/usrp3/top/x300
+      source $(Build.SourcesDirectory)/uhddev/.ci/fpga/scripts/run_setup.sh $(Build.SourcesDirectory)/uhddev/fpga/usrp3/top/x300
       pushd $(Build.SourcesDirectory)/uhddev/fpga/usrp3/tools/utils
       pip3 install -r requirements.txt
       popd

.ci/templates/stages-uhd-pipeline.yml

@@ -56,6 +56,123 @@ parameters:
 - name: skip_analyze_changeset
   type: boolean
   default: false
+  # FPGA parameters
+## Optional parameters
+# Run testbenches
+- name: run_testbenches
+  type: boolean
+  default: true
+# Option to ignore cached artifacts (if available) and perform
+# a clean IP build.
+- name: clean_ip_build
+  type: boolean
+  default: false
+# Number of parallel jobs to use for IP build
+- name: num_ip_jobs
+  type: number
+  default: 5
+# Option to publish intermediate files
+- name: publish_int_files
+  type: boolean
+  default: false
+# Package and publish images
+- name: package_and_publish_images
+  type: boolean
+  default: true
+# Package access in the SDR server ('Internal' or 'Public')
+- name: package_access
+  type: string
+  default: 'Internal'
+# Build X3x0 FPGA targets
+- name: build_fpgaimg_x3x0
+  type: boolean
+  displayName: Build X3x0
+  default: false
+# Build N3xx FPGA targets
+- name: build_fpgaimg_n3xx
+  type: boolean
+  displayName: Build N3xx
+  default: false
+# Build E31x FPGA targets
+- name: build_fpgaimg_e31x
+  type: boolean
+  displayName: Build E31x
+  default: false
+# Build E32x FPGA targets
+- name: build_fpgaimg_e32x
+  type: boolean
+  displayName: Build E32x
+  default: false
+# Build X410 FPGA targets
+- name: build_fpgaimg_x410
+  type: boolean
+  default: false
+# Requested X410 targets (if build_x410 is true)
+- name: x410_targets_matrix
+  type: object
+  default:
+    X410_X4_400:
+      image_core: x410_X4_400_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_X4_400
+      artifact_name: X410_X4_400
+      timeout: 720
+      max_attempts: 2
+    X410_UC_200:
+      image_core: x410_UC_200_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_UC_200
+      artifact_name: X410_UC_200
+      timeout: 720
+      max_attempts: 2
+    X410_X4_200:
+      image_core: x410_X4_200_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_X4_200
+      artifact_name: X410_X4_200
+      timeout: 720
+      max_attempts: 2
+    X410_CG_400:
+      image_core: x410_CG_400_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_CG_400
+      artifact_name: X410_CG_400
+      timeout: 720
+      max_attempts: 2
+# Build X440 FPGA targets
+- name: build_fpgaimg_x440
+  type: boolean
+  default: false
+# Requested X440 targets
+- name: x440_targets_matrix
+  type: object
+  default:
+    X440_CG_1600:
+      image_core: x440_CG_1600_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_CG_1600
+      artifact_name: X440_CG_1600
+      timeout: 720
+      max_attempts: 2
+    X440_CG_400:
+      image_core: x440_CG_400_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_CG_400
+      artifact_name: X440_CG_400
+      timeout: 720
+      max_attempts: 2
+    X440_X4_1600:
+      image_core: x440_X4_1600_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_X4_1600
+      artifact_name: X440_X4_1600
+      timeout: 720
+      max_attempts: 2
+    X440_X4_400:
+      image_core: x440_X4_400_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_X4_400
+      artifact_name: X440_X4_400
+      timeout: 720
+      max_attempts: 2
+    X440_X4_200:
+      image_core: x440_X4_200_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_X4_200
+      artifact_name: X440_X4_200
+      timeout: 720
+      max_attempts: 2
 
 variables:
 - template: ../uhd-pipeline-vars.yml
@@ -68,8 +185,11 @@ resources:
   - pipeline: usrp-kas-pipeline
     source: 'usrp-kas'
     branch: kirkstone
-  - pipeline: uhd_fpga_pipeline
-    source: 'uhddev fpga pipeline'
+  - pipeline: uhd_mono_pipeline
+    source: 'uhddev mono pipeline'
+    branch: master
+  - pipeline: uhd_mono_pipeline_pr
+    source: 'uhddev mono pipeline PR'
     branch: master
   repositories:
   - repository: meta-ettus
@@ -395,7 +515,7 @@ stages:
     parameters:
       testOS: ubuntu2004
       uhdSrcDir: $(Build.SourcesDirectory)
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testDevices: 'x3xx,b2xx'
 
@@ -420,7 +540,7 @@ stages:
     parameters:
       testOS: ubuntu2004
       uhdSrcDir: $(Build.SourcesDirectory)
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testDevices: 'n3xx,e320'
 
@@ -451,11 +571,11 @@ stages:
   jobs:
   - template: tests/job-uhd-x410-hardware-tests-sdr-test0.yml
     parameters:
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
   - template: tests/job-uhd-x440-hardware-tests-sdr-test0.yml
     parameters:
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
 - stage: test_uhd_x4xx_pebbles_stage
@@ -485,12 +605,12 @@ stages:
   jobs:
   - template: tests/job-uhd-x410-hardware-tests-pebbles.yml
     parameters:
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
   - template: tests/job-uhd-x440-hardware-tests-pebbles.yml
     parameters:
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
 
@@ -521,7 +641,7 @@ stages:
   jobs:
   - template: tests/job-uhd-x440-hardware-tests-saison.yml
     parameters:
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: --test_selector test_rx_phase_coherence.py test_tx_phase_coherence.py
       testLength: ${{ parameters.testLength }}
@@ -547,7 +667,7 @@ stages:
   - template: job-uhd-rf-tests-pebbles.yml
     parameters:
       uhdSrcDir: $(Build.SourcesDirectory)/uhddev
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testOS: ubuntu1804
       testDevices: 'n3xx'
@@ -573,7 +693,7 @@ stages:
     parameters:
       testOS: ubuntu2004
       uhdSrcDir: $(Build.SourcesDirectory)/uhddev
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
 
@@ -598,6 +718,90 @@ stages:
     parameters:
       testOS: ubuntu2204
       uhdSrcDir: $(Build.SourcesDirectory)/uhddev
-      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
+
+
+
+####### FPGA Stages ###########################################################
+
+### START: Testbenches stage
+
+- stage: run_testbenches_stage
+  displayName: Run Testbenches
+  dependsOn: analyze_changeset
+  condition: and(succeeded(),
+                 or(
+                   eq('${{ parameters.run_testbenches }}', 'true'),
+                   contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.UhdChangeList'], 'fpga.usrp3.testbenches')
+                   )
+                )
+  jobs:
+  - template: ../fpga/templates/job-run-testbenches.yml
+
+### END: Testbenches stage
+
+
+### START: X400 stages
+
+- template: ../fpga/devices/job-build-fpga-x400.yml
+  parameters:
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files: ${{ parameters.publish_int_files }}
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_x410: ${{ parameters.build_fpgaimg_x410 }}
+    build_x440: ${{ parameters.build_fpgaimg_x440 }}
+    x410_requests_matrix: ${{ parameters.x410_targets_matrix }}
+    x440_requests_matrix: ${{ parameters.x440_targets_matrix }}
+
+### END: X400 stages
+
+### START: X3x0 stages
+
+- template: ../fpga/devices/job-build-fpga-x300.yml
+  parameters:
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files: ${{ parameters.publish_int_files }}
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_x3x0: ${{ parameters.build_fpgaimg_x3x0 }}
+
+### END: X3x0 stages
+
+### START: N3xx stages
+
+- template: ../fpga/devices/job-build-fpga-n3xx.yml
+  parameters:
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files:  ${{ parameters.publish_int_files }}
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_n3xx: ${{ parameters.build_fpgaimg_n3xx }}
+
+### END: N3xx stages
+
+### START: E31x stages
+
+- template: ../fpga/devices/job-build-fpga-e31x.yml
+  parameters:
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files:  ${{ parameters.publish_int_files }}
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_e31x: ${{ parameters.build_fpgaimg_e31x }}
+
+### END: E31x stages
+
+### START: E320 stages
+
+- template: ../fpga/devices/job-build-fpga-e320.yml
+  parameters:
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files:  ${{ parameters.publish_int_files }}
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_e320: ${{ parameters.build_fpgaimg_e32x }}
+
+### END: E320 stages

.ci/uhd-hardware-test-dev.yml

@@ -68,15 +68,12 @@ resources:
   - pipeline: uhd_mono_pipeline
     source: 'uhddev mono pipeline'
     branch: master
+  - pipeline: uhd_mono_pipeline_pr
+    source: 'uhddev mono pipeline PR'
+    branch: master
   - pipeline: usrp-kas-pipeline
     source: 'usrp-kas'
     branch: kirkstone
-  - pipeline: uhd_fpga_pipeline
-    source: 'uhddev fpga pipeline'
-    branch: master
-  - pipeline: uhd_fpga_pr_pipeline
-    source: 'uhddev fpga pipeline PR'
-    branch: master
   repositories:
   - repository: meta-ettus
     type: github
@@ -104,9 +101,9 @@ stages:
     parameters:
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
 - stage: test_uhd_x440_embedded_stage
@@ -118,9 +115,9 @@ stages:
     parameters:
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
 - stage: test_streaming_stage
@@ -134,9 +131,9 @@ stages:
       uhdSrcDir: $(Build.SourcesDirectory)/uhddev
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
       dpdkDirs: '${{ parameters.dpdkDirs }}'
@@ -152,9 +149,9 @@ stages:
       uhdSrcDir: $(Build.SourcesDirectory)/uhddev
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
       dpdkDirs: '${{ parameters.dpdkDirs }}'
@@ -170,9 +167,9 @@ stages:
       uhdSrcDir: $(Build.SourcesDirectory)
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
 - stage: test_n310_rf_tests
@@ -186,9 +183,9 @@ stages:
       uhdSrcDir: $(Build.SourcesDirectory)/uhddev
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
 
@@ -201,9 +198,9 @@ stages:
     parameters:
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
       testLength: ${{ parameters.testLength }}
@@ -218,9 +215,9 @@ stages:
     parameters:
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
       testLength: ${{ parameters.testLength }}
@@ -234,9 +231,9 @@ stages:
     parameters:
       uhdArtifactSource: uhd_mono_pipeline
       ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-        uhdFpgaArtifactSource: uhd_fpga_pr_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline_pr
       ${{ else }}:
-        uhdFpgaArtifactSource: uhd_fpga_pipeline
+        uhdFpgaArtifactSource: uhd_mono_pipeline
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       ${{ if contains(parameters['extra_rf_test_args'],  'test_selector') }}:
         extra_rf_test_args: ${{ parameters.extra_rf_test_args }}

.ci/uhd-hardware-test-weekly-pipeline.yml

@@ -29,24 +29,21 @@ parameters:
 variables:
   - name: uhd_fpga_artifact_source
     ${{ if eq(parameters.fpga_imgs_source,  'FPGA Pipeline PR') }}:
-      value: uhd_fpga_pr_pipeline
+      value: uhd_mono_pipeline_pr
     ${{ else }}:
-      value: uhd_fpga_pipeline
+      value: uhd_mono_pipeline
 
 resources:
   pipelines:
   - pipeline: uhd_mono_pipeline
     source: 'uhddev mono pipeline'
     branch: master
+  - pipeline: uhd_mono_pipeline_pr
+    source: 'uhddev mono pipeline PR'
+    branch: master
   - pipeline: usrp-kas-pipeline
     source: 'usrp-kas'
     branch: kirkstone
-  - pipeline: uhd_fpga_pipeline
-    source: 'uhddev fpga pipeline'
-    branch: master
-  - pipeline: uhd_fpga_pr_pipeline
-    source: 'uhddev fpga pipeline PR'
-    branch: master
   repositories:
   - repository: meta-ettus
     type: github

.ci/uhd-pipeline-pr.yml

@@ -63,23 +63,23 @@ parameters:
   default: true
 - name: build_e310_sg1
   type: boolean
-  displayName: Build e310_sg1 image
+  displayName: Build e310_sg1 filesystem image
   default: true
 - name: build_e310_sg3
   type: boolean
-  displayName: Build e310_sg3 image
+  displayName: Build e310_sg3 filesystem image
   default: true
 - name: build_e320
   type: boolean
-  displayName: Build e320 image
+  displayName: Build e320 filesystem image
   default: true
 - name: build_n3xx
   type: boolean
-  displayName: Build n3xx image
+  displayName: Build n3xx filesystem image
   default: true
 - name: build_x4xx
   type: boolean
-  displayName: Build x4xx image
+  displayName: Build x4xx filesystem image
   default: true
 - name: fpga_imgs_source
   type: string
@@ -89,6 +89,124 @@ parameters:
   - 'FPGA Pipeline'
   displayName: FPGA Images Source
   default: 'FPGA Pipeline'
+  # FPGA Parameters
+- name: run_testbenches
+  type: boolean
+  displayName: Run Testbenches
+  default: true
+- name: clean_ip_build
+  type: boolean
+  displayName: Clean IP Build
+  default: false
+- name: num_ip_jobs
+  type: number
+  default: 5
+  displayName: Number of parallel IP jobs
+- name: package_and_publish_images
+  type: boolean
+  displayName: Package & Publish Images
+  default: false
+- name: package_access
+  type: string
+  values:
+  - 'Internal'
+  - 'files.ettus.com (Public)'
+  displayName: Published Package Access
+  default: 'Internal'
+- name: skip_analyze_changeset
+  type: boolean
+  displayName: Skip Analyze Changeset
+  default: false
+- name: build_fpgaimg_x3x0
+  type: boolean
+  displayName: Build X3x0 FPGA Images
+  default: false
+- name: build_fpgaimg_n3xx
+  type: boolean
+  displayName: Build N3xx FPGA Images
+  default: false
+- name: build_fpgaimg_e31x
+  type: boolean
+  displayName: Build E31x FPGA Images
+  default: false
+- name: build_fpgaimg_e32x
+  type: boolean
+  displayName: Build E32x FPGA Images
+  default: false
+- name: build_fpgaimg_x410
+  type: boolean
+  displayName: Build X410 FPGA Images
+  default: false
+- name: build_fpgaimg_x440
+  type: boolean
+  displayName: Build X440 FPGA Images
+  default: false
+# Requested X410 targets
+- name: x410_targets_matrix
+  type: object
+  displayName: X410 Targets
+  default:
+    X410_UC_200:
+      image_core: x410_UC_200_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_UC_200
+      target_name: X410
+      artifact_name: X410_UC_200
+      timeout: 720
+      max_attempts: 2
+    X410_X4_200:
+      image_core: x410_X4_200_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_X4_200
+      target_name: X410
+      artifact_name: X410_X4_200
+      timeout: 720
+      max_attempts: 2
+    X410_CG_400:
+      image_core: x410_CG_400_rfnoc_image_core.yml
+      image_core_name: usrp_x410_fpga_CG_400
+      target_name: X410
+      artifact_name: X410_CG_400
+      timeout: 720
+      max_attempts: 2
+- name: x440_targets_matrix
+  type: object
+  displayName: X440 Targets
+  default:
+    X440_CG_1600:
+      image_core: x440_CG_1600_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_CG_1600
+      target_name: X440
+      artifact_name: X440_CG_1600
+      timeout: 720
+      max_attempts: 2
+    X440_CG_400:
+      image_core: x440_CG_400_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_CG_400
+      target_name: X440
+      artifact_name: X440_CG_400
+      timeout: 720
+      max_attempts: 2
+    X440_X4_1600:
+      image_core: x440_X4_1600_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_X4_1600
+      target_name: X440
+      artifact_name: X440_X4_1600
+      timeout: 720
+      max_attempts: 2
+    X440_X4_400:
+      image_core: x440_X4_400_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_X4_400
+      target_name: X440
+      artifact_name: X440_X4_400
+      timeout: 720
+      max_attempts: 2
+    X440_X4_200:
+      image_core: x440_X4_200_rfnoc_image_core.yml
+      image_core_name: usrp_x440_fpga_X4_200
+      target_name: X440
+      artifact_name: X440_X4_200
+      timeout: 720
+      max_attempts: 2
+
 
 trigger: none
 
@@ -101,6 +219,7 @@ pr:
     include:
     - host
     - mpm
+    - fpga
     - .ci
     - images/manifest.txt
     exclude:
@@ -129,3 +248,17 @@ extends:
     build_n3xx: ${{ parameters.build_n3xx }}
     build_x4xx: ${{ parameters.build_x4xx }}
     fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
+    # FPGA parameters
+    run_testbenches: ${{ parameters.run_testbenches }}
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files: true
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_fpgaimg_x3x0: ${{ parameters.build_fpgaimg_x3x0 }}
+    build_fpgaimg_n3xx: ${{ parameters.build_fpgaimg_n3xx }}
+    build_fpgaimg_e31x: ${{ parameters.build_fpgaimg_e31x }}
+    build_fpgaimg_e32x: ${{ parameters.build_fpgaimg_e32x }}
+    build_fpgaimg_x410: ${{ parameters.build_fpgaimg_x410 }}
+    build_fpgaimg_x440: ${{ parameters.build_fpgaimg_x440 }}
+    x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
+    x440_targets_matrix: ${{ parameters.x440_targets_matrix }}

.ci/uhd-pipeline.yml

@@ -78,6 +78,54 @@ parameters:
   - 'FPGA Pipeline'
   displayName: FPGA Images Source
   default: 'FPGA Pipeline'
+## FPGA parameters
+- name: run_testbenches
+  type: boolean
+  displayName: Run Testbenches
+  default: true
+- name: clean_ip_build
+  type: boolean
+  displayName: Clean IP Build
+  default: true
+- name: num_ip_jobs
+  type: number
+  default: 5
+  displayName: Number of parallel IP jobs
+- name: package_and_publish_images
+  type: boolean
+  displayName: Package & Publish Images
+  default: true
+- name: package_access
+  type: string
+  values:
+  - 'Internal'
+  - 'files.ettus.com (Public)'
+  displayName: Published Package Access
+  default: 'Internal'
+- name: build_fpgaimg_x3x0
+  type: boolean
+  displayName: Build X3x0 FPGA Images
+  default: true
+- name: build_fpgaimg_n3xx
+  type: boolean
+  displayName: Build N3xx FPGA Images
+  default: true
+- name: build_fpgaimg_e31x
+  type: boolean
+  displayName: Build E31x FPGA Images
+  default: true
+- name: build_fpgaimg_e32x
+  type: boolean
+  displayName: Build E32x FPGA Images
+  default: true
+- name: build_fpgaimg_x410
+  type: boolean
+  displayName: Build X410 FPGA Images
+  default: true
+- name: build_fpgaimg_x440
+  type: boolean
+  displayName: Build X440 FPGA Images
+  default: true
 
 trigger:
   batch: true
@@ -117,3 +165,17 @@ extends:
     build_x4xx: ${{ parameters.build_x4xx }}
     fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     skip_analyze_changeset: true
+    # FPGA parameters
+    run_testbenches: ${{ parameters.run_testbenches }}
+    clean_ip_build: ${{ parameters.clean_ip_build }}
+    publish_int_files: true
+    package_and_publish_images: ${{ parameters.package_and_publish_images }}
+    package_access: ${{ parameters.package_access }}
+    build_fpgaimg_x3x0: ${{ parameters.build_fpgaimg_x3x0 }}
+    build_fpgaimg_n3xx: ${{ parameters.build_fpgaimg_n3xx }}
+    build_fpgaimg_e31x: ${{ parameters.build_fpgaimg_e31x }}
+    build_fpgaimg_e32x: ${{ parameters.build_fpgaimg_e32x }}
+    build_fpgaimg_x410: ${{ parameters.build_fpgaimg_x410 }}
+    build_fpgaimg_x440: ${{ parameters.build_fpgaimg_x440 }}
+    x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
+    x440_targets_matrix: ${{ parameters.x440_targets_matrix }}

fpga/.ci/fpga-pipeline-pr.yml

@@ -1,165 +0,0 @@
-#
-# Copyright 2022 Ettus Research, a National Instruments Brand
-#
-# SPDX-License-Identifier: LGPL-3.0-or-later
-#
-# Description:
-#
-#   This pipeline is used to build FPGAs and run testbenches for PRs.
-#
-#   See https://aka.ms/yaml for pipeline YAML documentation.
-#
-
-parameters:
-- name: run_testbenches
-  type: boolean
-  displayName: Run Testbenches
-  default: true
-- name: clean_ip_build
-  type: boolean
-  displayName: Clean IP Build
-  default: false
-- name: num_ip_jobs
-  type: number
-  default: 5
-  displayName: Number of parallel IP jobs
-- name: package_and_publish_images
-  type: boolean
-  displayName: Package & Publish Images
-  default: false
-- name: package_access
-  type: string
-  values:
-  - 'Internal'
-  - 'files.ettus.com (Public)'
-  displayName: Published Package Access
-  default: 'Internal'
-- name: skip_analyze_changeset
-  type: boolean
-  displayName: Skip Analyze Changeset
-  default: false
-- name: build_x3x0
-  type: boolean
-  displayName: Build X3x0
-  default: false
-- name: build_n3xx
-  type: boolean
-  displayName: Build N3xx
-  default: false
-- name: build_e31x
-  type: boolean
-  displayName: Build E31x
-  default: false
-- name: build_e32x
-  type: boolean
-  displayName: Build E32x
-  default: false
-- name: build_x410
-  type: boolean
-  displayName: Build X410
-  default: false
-- name: build_x440
-  type: boolean
-  displayName: Build X440
-  default: false
-# Requested X410 targets
-- name: x410_targets_matrix
-  type: object
-  displayName: X410 Targets
-  default:
-    X410_UC_200:
-      image_core: x410_UC_200_rfnoc_image_core.yml
-      image_core_name: usrp_x410_fpga_UC_200
-      target_name: X410
-      artifact_name: X410_UC_200
-      timeout: 720
-      max_attempts: 2
-    X410_X4_200:
-      image_core: x410_X4_200_rfnoc_image_core.yml
-      image_core_name: usrp_x410_fpga_X4_200
-      target_name: X410
-      artifact_name: X410_X4_200
-      timeout: 720
-      max_attempts: 2
-    X410_CG_400:
-      image_core: x410_CG_400_rfnoc_image_core.yml
-      image_core_name: usrp_x410_fpga_CG_400
-      target_name: X410
-      artifact_name: X410_CG_400
-      timeout: 720
-      max_attempts: 2
-- name: x440_targets_matrix
-  type: object
-  displayName: X440 Targets
-  default:
-    X440_CG_1600:
-      image_core: x440_CG_1600_rfnoc_image_core.yml
-      image_core_name: usrp_x440_fpga_CG_1600
-      target_name: X440
-      artifact_name: X440_CG_1600
-      timeout: 720
-      max_attempts: 2
-    X440_CG_400:
-      image_core: x440_CG_400_rfnoc_image_core.yml
-      image_core_name: usrp_x440_fpga_CG_400
-      target_name: X440
-      artifact_name: X440_CG_400
-      timeout: 720
-      max_attempts: 2
-    X440_X4_1600:
-      image_core: x440_X4_1600_rfnoc_image_core.yml
-      image_core_name: usrp_x440_fpga_X4_1600
-      target_name: X440
-      artifact_name: X440_X4_1600
-      timeout: 720
-      max_attempts: 2
-    X440_X4_400:
-      image_core: x440_X4_400_rfnoc_image_core.yml
-      image_core_name: usrp_x440_fpga_X4_400
-      target_name: X440
-      artifact_name: X440_X4_400
-      timeout: 720
-      max_attempts: 2
-    X440_X4_200:
-      image_core: x440_X4_200_rfnoc_image_core.yml
-      image_core_name: usrp_x440_fpga_X4_200
-      target_name: X440
-      artifact_name: X440_X4_200
-      timeout: 720
-      max_attempts: 2
-
-trigger: none
-
-pr:
-  branches:
-    include:
-    - master
-    - UHD-*
-  paths:
-    include:
-    - fpga/usrp3/lib
-    - fpga/usrp3/top
-    - fpga/usrp3/sim
-    - fpga/.ci
-    - host/utils/rfnoc_image_builder.py
-    - host/utils/repeat_fpga_build.py
-    - host/python/uhd/rfnoc_utils
-    - host/include/uhd/rfnoc
-
-extends:
-  template: templates/stages-fpga-pipeline.yml
-  parameters:
-    run_testbenches: ${{ parameters.run_testbenches }}
-    clean_ip_build: ${{ parameters.clean_ip_build }}
-    publish_int_files: true
-    package_and_publish_images: ${{ parameters.package_and_publish_images }}
-    package_access: ${{ parameters.package_access }}
-    skip_analyze_changeset: ${{ parameters.skip_analyze_changeset }}
-    build_x3x0: ${{ parameters.build_x3x0 }}
-    build_n3xx: ${{ parameters.build_n3xx }}
-    build_e31x: ${{ parameters.build_e31x }}
-    build_e32x: ${{ parameters.build_e32x }}
-    build_x410: ${{ parameters.build_x410 }}
-    build_x440: ${{ parameters.build_x440 }}
-    x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
-    x440_targets_matrix: ${{ parameters.x440_targets_matrix }}

fpga/.ci/fpga-pipeline.yml

@@ -1,107 +0,0 @@
-#
-# Copyright 2022 Ettus Research, a National Instruments Brand
-#
-# SPDX-License-Identifier: LGPL-3.0-or-later
-#
-# Description:
-#
-#   This pipeline is used to build FPGAs and run testbenches as CI
-#   from commits in master.
-#
-#   See https://aka.ms/yaml for pipeline YAML documentation.
-#
-
-parameters:
-- name: run_testbenches
-  type: boolean
-  displayName: Run Testbenches
-  default: true
-- name: clean_ip_build
-  type: boolean
-  displayName: Clean IP Build
-  default: true
-- name: num_ip_jobs
-  type: number
-  default: 5
-  displayName: Number of parallel IP jobs
-- name: package_and_publish_images
-  type: boolean
-  displayName: Package & Publish Images
-  default: true
-- name: package_access
-  type: string
-  values:
-  - 'Internal'
-  - 'files.ettus.com (Public)'
-  displayName: Published Package Access
-  default: 'Internal'
-- name: skip_analyze_changeset
-  type: boolean
-  displayName: Skip Analyze Changeset
-  default: true
-- name: build_x3x0
-  type: boolean
-  displayName: Build X3x0
-  default: true
-- name: build_n3xx
-  type: boolean
-  displayName: Build N3xx
-  default: true
-- name: build_e31x
-  type: boolean
-  displayName: Build E31x
-  default: true
-- name: build_e32x
-  type: boolean
-  displayName: Build E32x
-  default: true
-- name: build_x410
-  type: boolean
-  displayName: Build X410
-  default: true
-- name: build_x440
-  type: boolean
-  displayName: Build X440
-  default: true
-
-trigger:
-  batch: true
-  branches:
-    include:
-    - master
-    - UHD-*
-  paths:
-    include:
-    - fpga/usrp3/lib
-    - fpga/usrp3/top
-    - fpga/usrp3/sim
-    - fpga/.ci
-    - host/utils/rfnoc_image_builder.py
-    - host/utils/repeat_fpga_build.py
-    - host/python/uhd/rfnoc_utils
-    - host/include/uhd/rfnoc
-
-pr: none
-
-schedules:
-- cron: "0 18 * * Sun"
-  displayName: Weekly FPGA CI Build master branch
-  branches:
-    include:
-    - master
-  always: true
-
-extends:
-  template: templates/stages-fpga-pipeline.yml
-  parameters:
-    run_testbenches: ${{ parameters.run_testbenches }}
-    clean_ip_build: ${{ parameters.clean_ip_build }}
-    package_and_publish_images: ${{ parameters.package_and_publish_images }}
-    package_access: ${{ parameters.package_access }}
-    skip_analyze_changeset: ${{ parameters.skip_analyze_changeset }}
-    build_x3x0: ${{ parameters.build_x3x0 }}
-    build_n3xx: ${{ parameters.build_n3xx }}
-    build_e31x: ${{ parameters.build_e31x }}
-    build_e32x: ${{ parameters.build_e32x }}
-    build_x410: ${{ parameters.build_x410 }}
-    build_x440: ${{ parameters.build_x440 }}

fpga/.ci/templates/changeset_build_list.yaml

@@ -1,90 +0,0 @@
-# build targets:
-# - fpga.usrp3.$PLATFORM: Build FPGA images for given platforms.
-
-# library changes
-- re: fpga/usrp3/lib
-  add:
-    - fpga.usrp3.all
-
-# image builder changes
-- re: host/utils/rfnoc_image_builder.py
-  add:
-    - fpga.usrp3.all
-# only trigger on .py files, exclude modtools_commands and templates
-- re: host/python/uhd/rfnoc_utils/[^/]+py$
-  add:
-    - fpga.usrp3.all
-# RFNoC blocks
-- re: host/include/uhd/rfnoc/blocks/.*\.yml
-  add:
-    - fpga.usrp3.all
-# RFNoC core (the device-specific BSP files are checked below)
-- re: host/include/uhd/rfnoc/core/rfnoc_imagebuilder_args\.json
-  add:
-    - fpga.usrp3.all
-# RFNoC modules
-- re: host/include/uhd/rfnoc/modules/.*\.yml
-  add:
-    - fpga.usrp3.all
-# RFNoC transport adapters (only relevant for x4xx)
-- re: host/include/uhd/rfnoc/transport_adapters/.*\.yml
-  add:
-    - fpga.usrp3.x4xx
-
-# Device-specific changes.
-- re: fpga/usrp3/top/x400
-  add:
-    - fpga.usrp3.x4xx
-- re: host/include/uhd/rfnoc/core/x4.._bsp.yml
-  add:
-    - fpga.usrp3.x4xx
-- re: fpga/usrp3/top/x300
-  add:
-    - fpga.usrp3.x3xx
-- re: host/include/uhd/rfnoc/core/x3.._bsp.yml
-  add:
-    - fpga.usrp3.x3xx
-- re: fpga/usrp3/top/e31x
-  add:
-    - fpga.usrp3.e31x
-- re: host/include/uhd/rfnoc/core/e310_bsp.yml
-  add:
-    - fpga.usrp3.e31x
-- re: fpga/usrp3/top/e320
-  add:
-    - fpga.usrp3.e320
-- re: host/include/uhd/rfnoc/core/e320_bsp.yml
-  add:
-    - fpga.usrp3.e320
-- re: fpga/usrp3/top/n3xx
-  add:
-    - fpga.usrp3.n3xx
-- re: host/include/uhd/rfnoc/core/n3.._bsp.yml
-  add:
-    - fpga.usrp3.n3xx
-
-###############################################################################
-# CI CHANGES
-###############################################################################
-- re: fpga/.ci/fpga-pipeline*
-  add:
-    - fpga.usrp3.all
-- re: fpga/.ci/templates*
-  add:
-    - fpga.usrp3.all
-# Device-specific pipeline changes.
-- re: fpga/.ci/devices/job-build-x400.yml
-  add:
-    - fpga.usrp3.x4xx
-- re: fpga/.ci/devices/job-build-x300.yml
-  add:
-    - fpga.usrp3.x3xx
-- re: fpga/.ci/devices/job-build-e31x.yml
-  add:
-    - fpga.usrp3.e31x
-- re: fpga/.ci/devices/job-build-e320.yml
-  add:
-    - fpga.usrp3.e320
-- re: fpga/.ci/devices/job-build-n3xx.yml
-  add:
-    - fpga.usrp3.n3xx

fpga/.ci/templates/job-analyze-changeset.yml

@@ -1,33 +0,0 @@
-# This job will execute the changeset_testlist.py script, which in turn will
-# compute a list of tests that need to be executed.
-# The script itself produces the correct output to set a variable for a future
-# stage.
-
-parameters:
-- name: skip_analyze_changeset
-  type: boolean
-  default: false
-
-jobs:
-  - job: analyze
-    displayName: Analyze Changeset
-    pool:
-      name: Drivers-NIBuildFarm-RFMIBUILD
-      demands: sh
-    condition: not(${{ parameters.skip_analyze_changeset }})
-    steps:
-    - checkout: self
-      clean: true
-    - bash: |
-        if [[ $AGENT_OS == "Windows_NT" ]]; then
-            VENV_BIN_DIR="Scripts"
-        else
-            VENV_BIN_DIR="bin"
-        fi
-        python3 -m venv $AGENT_TEMPDIRECTORY/ac_venv
-        $AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/pip install --upgrade pip
-        $AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/pip install ruamel.yaml requests
-        git branch
-        $AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/python3 tools/changeset_testlist.py --target-branch origin/master --set-azdo-var HdlChangeList --rule-file fpga/.ci/templates/changeset_build_list.yaml --verbose --list-tests
-      name: gen_build_list
-      displayName: Generate Build-List

tools/changeset_testlist.yaml

@@ -213,6 +213,79 @@
     - hw.rf.all
     - devtest.all
 
+###############################################################################
+# FPGA CHANGES
+###############################################################################
+# build targets:
+# - fpga.usrp3.$PLATFORM: Build FPGA images for given platforms.
+
+- re: fpga/usrp3/
+  add:
+    - fpga.usrp3.testbenches
+  stop: False
+
+# library changes
+- re: fpga/usrp3/lib
+  add:
+    - fpga.usrp3.all
+
+# image builder changes
+- re: host/utils/rfnoc_image_builder.py
+  add:
+    - fpga.usrp3.all
+# only trigger on .py files, exclude modtools_commands and templates
+- re: host/python/uhd/rfnoc_utils/[^/]+py$
+  add:
+    - fpga.usrp3.all
+# RFNoC blocks
+- re: host/include/uhd/rfnoc/blocks/.*\.yml
+  add:
+    - fpga.usrp3.all
+# RFNoC core (the device-specific BSP files are checked below)
+- re: host/include/uhd/rfnoc/core/rfnoc_imagebuilder_args\.json
+  add:
+    - fpga.usrp3.all
+# RFNoC modules
+- re: host/include/uhd/rfnoc/modules/.*\.yml
+  add:
+    - fpga.usrp3.all
+# RFNoC transport adapters (only relevant for x4xx)
+- re: host/include/uhd/rfnoc/transport_adapters/.*\.yml
+  add:
+    - fpga.usrp3.x4xx
+
+# Device-specific changes.
+- re: fpga/usrp3/top/x400
+  add:
+    - fpga.usrp3.x4xx
+- re: host/include/uhd/rfnoc/core/x4.._bsp.yml
+  add:
+    - fpga.usrp3.x4xx
+- re: fpga/usrp3/top/x300
+  add:
+    - fpga.usrp3.x3xx
+- re: host/include/uhd/rfnoc/core/x3.._bsp.yml
+  add:
+    - fpga.usrp3.x3xx
+- re: fpga/usrp3/top/e31x
+  add:
+    - fpga.usrp3.e31x
+- re: host/include/uhd/rfnoc/core/e310_bsp.yml
+  add:
+    - fpga.usrp3.e31x
+- re: fpga/usrp3/top/e320
+  add:
+    - fpga.usrp3.e320
+- re: host/include/uhd/rfnoc/core/e320_bsp.yml
+  add:
+    - fpga.usrp3.e320
+- re: fpga/usrp3/top/n3xx
+  add:
+    - fpga.usrp3.n3xx
+- re: host/include/uhd/rfnoc/core/n3.._bsp.yml
+  add:
+    - fpga.usrp3.n3xx
+
 ###############################################################################
 # CI CHANGES
 ###############################################################################
@@ -254,6 +327,27 @@
     - uhd.build.linux
     - uhd.rfnoc_modtool.all
 
+
+- re: fpga/.ci/templates*
+  add:
+    - fpga.usrp3.all
+# Device-specific pipeline changes.
+- re: .ci/fpga/devices/job-build-x400.yml
+  add:
+    - fpga.usrp3.x4xx
+- re: .ci/fpga/devices/job-build-x300.yml
+  add:
+    - fpga.usrp3.x3xx
+- re: .ci/fpga/devices/job-build-e31x.yml
+  add:
+    - fpga.usrp3.e31x
+- re: .ci/fpga/devices/job-build-e320.yml
+  add:
+    - fpga.usrp3.e320
+- re: .ci/fpga/devices/job-build-n3xx.yml
+  add:
+    - fpga.usrp3.n3xx
+
 ###############################################################################
 # LABEL-BASED RULES
 ###############################################################################