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x300: Add support for reading device DNA

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This commit is contained in:
Martin Braun 2024-02-21 16:37:00 +01:00 committed by Joerg Hofrichter
parent af64b32d54
commit 14f487f165
7 changed files with 71 additions and 11 deletions
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8
fpga/usrp3/top/x300/bus_int.v
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@ -177,11 +177,13 @@ module bus_int #(
localparam RB_FP_GPIO_SRC = 8'd13;
localparam RB_DEVICE_ID = 8'd14;
localparam RB_BUILD_SEED = 8'd15;
localparam RB_DEVICE_DNA_LO = 8'd16;
localparam RB_DEVICE_DNA_HI = 8'd17;
localparam RB_TA_SFP0_BASE = SR_TA_SFP0_BASE;
localparam RB_TA_SFP1_BASE = SR_TA_SFP1_BASE;
localparam COMPAT_MAJOR = 16'h0027;
localparam COMPAT_MINOR = 16'h0002;
localparam COMPAT_MINOR = 16'h0003;
localparam NUM_TIMEKEEPERS = 1;
// Include the RFNoC image core header file
@ -212,6 +214,7 @@ module bus_int #(
wire spi_ready;
wire [31:0] rb_spi_data;
wire [15:0] device_id;
wire [63:0] dna; // DNA is 57 bits, but we pad to 64
wire m_ctrlport_req_wr_radio0;
wire m_ctrlport_req_rd_radio0;
@ -468,6 +471,8 @@ module bus_int #(
`define BUILD_SEED 32'b0
`endif
RB_BUILD_SEED: rb_data = `BUILD_SEED;
RB_DEVICE_DNA_LO: rb_data = dna[31:0];
RB_DEVICE_DNA_HI: rb_data = dna[63:32];
RB_XADC_VALS: rb_data = xadc_readback;
RB_FP_GPIO_SRC: rb_data = fp_gpio_src;
SR_BASE_TIME: begin
@ -783,6 +788,7 @@ module bus_int #(
.radio_clk (radio_clk ),
.ce_clk (ce_clk ),
.dram_clk (ddr3_axi_clk_x2),
.dna (dna ),
.m_ctrlport_radio1_req_wr (m_ctrlport_req_wr_radio1 ),
.m_ctrlport_radio1_req_rd (m_ctrlport_req_rd_radio1 ),
.m_ctrlport_radio1_req_addr (m_ctrlport_req_addr_radio1 ),

14
host/include/uhd/rfnoc/core/x300_bsp.yml
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@ -54,3 +54,17 @@ io_ports:
dram:
type: axi4_mm
drive: slave
serial:
type: device_dna
drive: listener
parameters:
width: 64
default_secure_image_core:
modules:
device_dna:
block_desc: 'device_dna.yml'
parameters:
device_type: "7SERIES"
connections:
- { srcblk: device_dna, srcport: device_dna, dstblk: _device_, dstport: serial}

14
host/include/uhd/rfnoc/core/x310_bsp.yml
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@ -54,3 +54,17 @@ io_ports:
dram:
type: axi4_mm
drive: slave
serial:
type: device_dna
drive: listener
parameters:
width: 64
default_secure_image_core:
modules:
device_dna:
block_desc: 'device_dna.yml'
parameters:
device_type: "7SERIES"
connections:
- { srcblk: device_dna, srcport: device_dna, dstblk: _device_, dstport: serial}

3
host/lib/usrp/x300/x300_defaults.hpp
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@ -8,6 +8,7 @@
#define INCLUDED_X300_DEFAULTS_HPP
#include <uhd/transport/udp_simple.hpp> //mtu
#include <uhdlib/utils/compat_check.hpp>
#include <string>
#include <vector>
@ -55,6 +56,8 @@ static constexpr double THREAD_BUFFER_TIMEOUT = 0.1; // Time in seconds
static constexpr double DEFAULT_EXT_ADC_SELF_TEST_DURATION = 30.0;
static constexpr uhd::compat_num32 MIN_COMPAT_NUM_DNA = {0x27, 0x3};
}}} /* namespace uhd::usrp::x300 */
#endif /* INCLUDED_X300_DEFAULTS_HPP */

9
host/lib/usrp/x300/x300_impl.cpp
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@ -23,6 +23,7 @@
#include <uhd/utils/safe_call.hpp>
#include <uhd/utils/static.hpp>
#include <uhdlib/rfnoc/device_id.hpp>
#include <uhdlib/utils/compat_check.hpp>
#include <chrono>
#include <fstream>
#include <thread>
@ -40,8 +41,10 @@ namespace asio = boost::asio;
namespace uhd { namespace usrp { namespace x300 {
void init_prop_tree(
const size_t mb_idx, uhd::rfnoc::x300_mb_controller* mbc, property_tree::sptr pt);
void init_prop_tree(const size_t mb_idx,
uhd::rfnoc::x300_mb_controller* mbc,
property_tree::sptr pt,
const uhd::compat_num32 fpga_compat);
}}} // namespace uhd::usrp::x300
@ -416,7 +419,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t& dev_addr)
////////////////////////////////////////////////////////////////////
// setup properties
////////////////////////////////////////////////////////////////////
init_prop_tree(mb_i, mb_ctrl.get(), _tree);
init_prop_tree(mb_i, mb_ctrl.get(), _tree, fpga_compat);
////////////////////////////////////////////////////////////////////
// RFNoC Stuff

17
host/lib/usrp/x300/x300_prop_tree.cpp
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@ -8,13 +8,17 @@
#include "x300_mb_controller.hpp"
#include <uhd/property_tree.hpp>
#include <uhd/utils/math.hpp>
#include <uhdlib/utils/compat_check.hpp>
using namespace uhd;
using namespace uhd::rfnoc;
namespace uhd { namespace usrp { namespace x300 {
void init_prop_tree(const size_t mb_idx, x300_mb_controller* mbc, property_tree::sptr pt)
void init_prop_tree(const size_t mb_idx,
x300_mb_controller* mbc,
property_tree::sptr pt,
const uhd::compat_num32 fpga_compat)
{
const fs_path mb_path = fs_path("/mboards") / mb_idx;
try {
@ -29,6 +33,17 @@ void init_prop_tree(const size_t mb_idx, x300_mb_controller* mbc, property_tree:
pt->create<std::string>(mb_path / "name").set(mbc->get_mboard_name());
pt->create<std::string>(mb_path / "codename").set("Yetti");
if (fpga_compat >= MIN_COMPAT_NUM_DNA) {
const uint64_t device_dna_lo = static_cast<uint64_t>(
mbc->get_zpu_ctrl()->peek32(SR_ADDR(SET0_BASE, ZPU_RB_DNA_LO)));
const uint64_t device_dna_hi = static_cast<uint64_t>(
mbc->get_zpu_ctrl()->peek32(SR_ADDR(SET0_BASE, ZPU_RB_DNA_HI)));
const uint64_t device_dna = device_dna_lo | (device_dna_hi << 32);
pt->create<std::string>(mb_path / "device_dna")
.set(str(boost::format("%016X") % device_dna));
UHD_LOG_DEBUG("X300", "Device DNA: " << boost::format("%016X") % device_dna);
}
////////////////////////////////////////////////////////////////////
// create clock properties
////////////////////////////////////////////////////////////////////

17
host/lib/usrp/x300/x300_regs.hpp
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@ -58,23 +58,28 @@ static const int ZPU_SR_SFP1_ADAPTER = 160;
#define ZPU_SR_SW_RST_RADIO_CLK_PLL (1 << 2)
#define ZPU_SR_SW_RST_ADC_IDELAYCTRL (1 << 3)
// These registers are read directly out of the FPGA via wishbone (starting at
// SET0_BASE). They have corresponding localparams in bus_int.v.
static const int ZPU_RB_SPI = 2;
static const int ZPU_RB_CLK_STATUS = 3;
static const int ZPU_RB_COMPAT_NUM = 6;
static const int ZPU_RB_RFNOC_INFO = 7;
static const int ZPU_RB_GIT_HASH = 10;
static const int ZPU_RB_SFP0_TYPE = 4;
static const int ZPU_RB_SFP1_TYPE = 5;
static const int ZPU_RB_COMPAT_NUM = 6;
static const int ZPU_RB_RFNOC_INFO = 7; // See defines below for bits
static const int ZPU_RB_GIT_HASH = 10;
static const int ZPU_RB_FP_GPIO_SRC = 13;
static const int ZPU_RB_DEVICE_ID = 14;
static const int ZPU_RB_BUILD_SEED = 15;
static const int ZPU_RB_DNA_LO = 16;
static const int ZPU_RB_DNA_HI = 17;
// RFNoC info bits
#define ZPU_RB_RFNOC_INFO_PROTOVER(X) (((X) >> 0) & 0xFFFF)
#define ZPU_RB_RFNOC_INFO_CHDR_WIDTH(X) (((X) >> 16) & 0xFFFF)
static const uint32_t RB_SFP_1G_ETH = 0;
static const uint32_t RB_SFP_10G_ETH = 1;
static const uint32_t RB_SFP_AURORA = 2;
// RFNoC info bits
#define ZPU_RB_RFNOC_INFO_PROTOVER(X) (((X) >> 0) & 0xFFFF)
#define ZPU_RB_RFNOC_INFO_CHDR_WIDTH(X) (((X) >> 16) & 0xFFFF)
// spi slaves on radio
#define DB_DAC_SEN (1 << 7)