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fpga: ci: trigger fpga builds based on changeset
This commit is contained in:
Javier Valenzuela
Wade Fife
parent
3422210550
commit
08031bed9e
194
fpga/.ci/devices/job-build-e31x.yml
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194
fpga/.ci/devices/job-build-e31x.yml
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@ -0,0 +1,194 @@
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#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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#
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# This template defines a stages-based pipeline for building E31X FPGA targets.
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#
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# See https://aka.ms/yaml for pipeline YAML documentation.
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#
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parameters:
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## Optional parameters
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# Run testbenches
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- name: run_testbenches
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type: boolean
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default: true
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# Option to ignore cached artifacts (if available) and perform
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# a clean IP build.
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- name: clean_ip_build
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type: boolean
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default: false
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# Number of parallel jobs to use for IP build
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- name: num_ip_jobs
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type: number
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default: 5
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# Option to publish intermediate files
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- name: publish_int_files
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type: boolean
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default: false
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# Package and publish images
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- name: package_and_publish_images
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type: boolean
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default: true
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# Package access in the SDR server ('Internal' or 'Public')
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- name: package_access
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type: string
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default: 'Internal'
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# Build E310 FPGA targets
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- name: build_e31x
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type: boolean
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default: true
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# E310 FPGA targets to build (if build_e31x is true)
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- name: e31x_sg1_full_targets_matrix
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type: object
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default:
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E310_SG1:
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image_core: e310_rfnoc_image_core.yml
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target_name: E310_SG1
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timeout: 720
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max_attempts: 2
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E310_SG1_IDLE:
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image_core: e310_rfnoc_image_core.yml
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target_name: E310_SG1_IDLE
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timeout: 720
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max_attempts: 2
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- name: e31x_sg1_reduced_targets_matrix
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type: object
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default:
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E310_SG1:
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image_core: e310_rfnoc_image_core.yml
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target_name: E310_SG1
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timeout: 720
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max_attempts: 2
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- name: e31x_sg3_full_targets_matrix
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type: object
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default:
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E310_SG3:
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image_core: e310_rfnoc_image_core.yml
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target_name: E310_SG3
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timeout: 720
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max_attempts: 2
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E310_SG3_IDLE:
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image_core: e310_rfnoc_image_core.yml
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target_name: E310_SG3_IDLE
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timeout: 720
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max_attempts: 2
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- name: e31x_sg3_reduced_targets_matrix
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type: object
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default:
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E310_SG3:
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image_core: e310_rfnoc_image_core.yml
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target_name: E310_SG3
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timeout: 720
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max_attempts: 2
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stages:
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### START: E310 stages
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- stage: build_e31x_sg1_ip_stage
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displayName: Build E310 SG1 IP
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dependsOn: analyze_changeset
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condition: and( succeeded(),
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or(
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contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.e31x'),
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contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
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eq('${{ parameters.build_e31x }}', 'true')
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)
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)
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jobs:
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- template: ../templates/job-build-ip.yml
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parameters:
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directory: uhddev/fpga/usrp3/top/e31x
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ip_target: E310_SG1_IP
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clean_build: ${{ parameters.clean_ip_build }}
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num_jobs: ${{ parameters.num_ip_jobs }}
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- stage: build_e31x_sg1_targets_stage
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displayName: Build E310 FPGA Targets
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dependsOn: build_e31x_sg1_ip_stage
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condition: succeeded('build_e31x_sg1_ip_stage')
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jobs:
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- ${{ if eq(parameters.package_and_publish_images, true) }}:
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- template: ../templates/job-build-fpga.yml
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parameters:
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targets_matrix: ${{ parameters.e31x_sg1_full_targets_matrix }}
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ip_artifact: E310_SG1_IP
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top_dir: uhddev/fpga/usrp3/top/e31x
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publish_int_files: ${{ parameters.publish_int_files }}
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- ${{ if eq(parameters.package_and_publish_images, false) }}:
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- template: ../templates/job-build-fpga.yml
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parameters:
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targets_matrix: ${{ parameters.e31x_sg1_reduced_targets_matrix }}
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ip_artifact: E310_SG1_IP
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top_dir: uhddev/fpga/usrp3/top/e31x
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publish_int_files: ${{ parameters.publish_int_files }}
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- stage: create_e31x_sg1_packages_stage
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displayName: Package & Publish E310 SG1 Binaries
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dependsOn: build_e31x_sg1_targets_stage
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condition: and(succeeded('build_e31x_sg1_targets_stage'),
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eq('${{ parameters.package_and_publish_images }}', 'true'))
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jobs:
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- template: ../templates/job-package-images.yml
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parameters:
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package_name: e3xx_e310_sg1_fpga_default
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artifacts_matrix: ${{ parameters.e31x_sg1_full_targets_matrix }}
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build_directory: uhddev/fpga/usrp3/top/e31x/build/
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package_access: ${{ parameters.package_access }}
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- stage: build_e31x_sg3_ip_stage
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displayName: Build E310 SG3 IP
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dependsOn: analyze_changeset
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condition: and( succeeded(),
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or(
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contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.e31x'),
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contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
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eq('${{ parameters.build_e31x }}', 'true')
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)
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)
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jobs:
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- template: ../templates/job-build-ip.yml
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parameters:
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directory: uhddev/fpga/usrp3/top/e31x
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ip_target: E310_SG3_IP
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clean_build: ${{ parameters.clean_ip_build }}
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num_jobs: ${{ parameters.num_ip_jobs }}
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- stage: build_e31x_sg3_targets_stage
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displayName: Build E310 SG3 FPGA Targets
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dependsOn: build_e31x_sg3_ip_stage
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condition: succeeded('build_e31x_sg3_ip_stage')
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jobs:
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- ${{ if eq(parameters.package_and_publish_images, true) }}:
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- template: ../templates/job-build-fpga.yml
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parameters:
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targets_matrix: ${{ parameters.e31x_sg3_full_targets_matrix }}
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ip_artifact: E310_SG3_IP
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top_dir: uhddev/fpga/usrp3/top/e31x
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publish_int_files: ${{ parameters.publish_int_files }}
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- ${{ if eq(parameters.package_and_publish_images, false) }}:
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- template: ../templates/job-build-fpga.yml
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parameters:
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targets_matrix: ${{ parameters.e31x_sg3_reduced_targets_matrix }}
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ip_artifact: E310_SG3_IP
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top_dir: uhddev/fpga/usrp3/top/e31x
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publish_int_files: ${{ parameters.publish_int_files }}
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- stage: create_e31x_sg3_packages_stage
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displayName: Package & Publish E310 Binaries
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dependsOn: build_e31x_sg3_targets_stage
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condition: and(succeeded('build_e31x_sg3_targets_stage'),
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eq('${{ parameters.package_and_publish_images }}', 'true'))
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jobs:
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- template: ../templates/job-package-images.yml
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parameters:
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package_name: e3xx_e310_sg3_fpga_default
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artifacts_matrix: ${{ parameters.e31x_sg3_full_targets_matrix }}
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build_directory: uhddev/fpga/usrp3/top/e31x/build/
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package_access: ${{ parameters.package_access }}
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### END: E310 stages
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126
fpga/.ci/devices/job-build-e320.yml
Normal file
126
fpga/.ci/devices/job-build-e320.yml
Normal file
@ -0,0 +1,126 @@
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#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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#
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# This template defines a stages-based pipeline for building E32X FPGA targets.
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#
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# See https://aka.ms/yaml for pipeline YAML documentation.
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#
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parameters:
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## Optional parameters
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# Run testbenches
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- name: run_testbenches
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type: boolean
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default: true
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# Option to ignore cached artifacts (if available) and perform
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# a clean IP build.
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- name: clean_ip_build
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type: boolean
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default: false
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# Number of parallel jobs to use for IP build
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- name: num_ip_jobs
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type: number
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default: 5
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# Option to publish intermediate files
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- name: publish_int_files
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type: boolean
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default: false
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# Package and publish images
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- name: package_and_publish_images
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type: boolean
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default: true
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# Package access in the SDR server ('Internal' or 'Public')
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- name: package_access
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type: string
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default: 'Internal'
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# Build E320 FPGA targets
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- name: build_e320
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type: boolean
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default: true
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# E320 FPGA targets to build (if build_e320 is true)
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- name: e320_full_targets_matrix
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type: object
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default:
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E320_1G:
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image_core: e320_rfnoc_image_core.yml
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target_name: E320_1G
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timeout: 720
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max_attempts: 2
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E320_XG:
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image_core: e320_rfnoc_image_core.yml
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target_name: E320_XG
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timeout: 720
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max_attempts: 2
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E320_AA:
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image_core: e320_rfnoc_image_core.yml
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target_name: E320_AA
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timeout: 720
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max_attempts: 2
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- name: e320_reduced_targets_matrix
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type: object
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default:
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E320_XG:
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image_core: e320_rfnoc_image_core.yml
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target_name: E320_XG
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timeout: 720
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max_attempts: 2
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stages:
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### START: E320 stages
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- stage: build_e320_ip_stage
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displayName: Build E320 IP
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dependsOn: analyze_changeset
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condition: and( succeeded(),
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or(
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contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.e320'),
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contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
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eq('${{ parameters.build_e320 }}', 'true')
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)
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)
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jobs:
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- template: ../templates/job-build-ip.yml
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parameters:
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directory: uhddev/fpga/usrp3/top/e320
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ip_target: E320_IP
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clean_build: ${{ parameters.clean_ip_build }}
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num_jobs: ${{ parameters.num_ip_jobs }}
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- stage: build_e320_targets_stage
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displayName: Build E320 FPGA Targets
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dependsOn: build_e320_ip_stage
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condition: succeeded('build_e320_ip_stage')
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jobs:
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- ${{ if eq(parameters.package_and_publish_images, true) }}:
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- template: ../templates/job-build-fpga.yml
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parameters:
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targets_matrix: ${{ parameters.e320_full_targets_matrix }}
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ip_artifact: E320_IP
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top_dir: uhddev/fpga/usrp3/top/e320
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publish_int_files: ${{ parameters.publish_int_files }}
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- ${{ if eq(parameters.package_and_publish_images, false) }}:
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- template: ../templates/job-build-fpga.yml
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parameters:
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targets_matrix: ${{ parameters.e320_reduced_targets_matrix }}
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ip_artifact: E320_IP
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top_dir: uhddev/fpga/usrp3/top/e320
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publish_int_files: ${{ parameters.publish_int_files }}
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- stage: create_e320_packages_stage
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displayName: Package & Publish E320 Binaries
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dependsOn: build_e320_targets_stage
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condition: and(succeeded('build_e320_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
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jobs:
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- template: ../templates/job-package-images.yml
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parameters:
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package_name: e3xx_e320_fpga_default
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artifacts_matrix: ${{ parameters.e320_full_targets_matrix }}
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build_directory: uhddev/fpga/usrp3/top/e320/build/
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package_access: ${{ parameters.package_access }}
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### END: E320 stages
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315
fpga/.ci/devices/job-build-n3xx.yml
Normal file
315
fpga/.ci/devices/job-build-n3xx.yml
Normal file
@ -0,0 +1,315 @@
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#
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# Copyright 2024 Ettus Research, a National Instruments Brand
|
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#
|
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# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
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# Description:
|
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#
|
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# This template defines a stages-based pipeline for building N3xx FPGA targets.
|
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#
|
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# See https://aka.ms/yaml for pipeline YAML documentation.
|
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#
|
||||
|
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parameters:
|
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## Optional parameters
|
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# Run testbenches
|
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- name: run_testbenches
|
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type: boolean
|
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default: true
|
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# Option to ignore cached artifacts (if available) and perform
|
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# a clean IP build.
|
||||
- name: clean_ip_build
|
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type: boolean
|
||||
default: false
|
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# Number of parallel jobs to use for IP build
|
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- name: num_ip_jobs
|
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type: number
|
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default: 5
|
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# Option to publish intermediate files
|
||||
- name: publish_int_files
|
||||
type: boolean
|
||||
default: false
|
||||
# Package and publish images
|
||||
- name: package_and_publish_images
|
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type: boolean
|
||||
default: true
|
||||
# Package access in the SDR server ('Internal' or 'Public')
|
||||
- name: package_access
|
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type: string
|
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default: 'Internal'
|
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# Build N300 FPGA targets
|
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- name: build_n3xx
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type: boolean
|
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default: true
|
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# N300 FPGA targets to build (if build_n3xx is true)
|
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- name: n300_full_targets_matrix
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type: object
|
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default:
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N300_HG:
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image_core: n300_rfnoc_image_core.yml
|
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target_name: N300_HG
|
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timeout: 720
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max_attempts: 2
|
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N300_XG:
|
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image_core: n300_rfnoc_image_core.yml
|
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target_name: N300_XG
|
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timeout: 720
|
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max_attempts: 2
|
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N300_WX:
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image_core: n300_rfnoc_image_core.yml
|
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target_name: N300_WX
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timeout: 720
|
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max_attempts: 2
|
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N300_AA:
|
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image_core: n300_bist_image_core.yml
|
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target_name: N300_AA
|
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timeout: 720
|
||||
max_attempts: 2
|
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- name: n300_reduced_targets_matrix
|
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type: object
|
||||
default:
|
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N300_HG:
|
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image_core: n300_rfnoc_image_core.yml
|
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target_name: N300_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
# N310 FPGA targets to build (if build_n3xx is true)
|
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- name: n310_full_targets_matrix
|
||||
type: object
|
||||
default:
|
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N310_HG:
|
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image_core: n310_rfnoc_image_core.yml
|
||||
target_name: N310_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
N310_XG:
|
||||
image_core: n310_rfnoc_image_core.yml
|
||||
target_name: N310_XG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
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N310_WX:
|
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image_core: n310_rfnoc_image_core.yml
|
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target_name: N310_WX
|
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timeout: 720
|
||||
max_attempts: 2
|
||||
N310_AA:
|
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image_core: n310_bist_image_core.yml
|
||||
target_name: N310_AA
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
- name: n310_reduced_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
N310_HG:
|
||||
image_core: n310_rfnoc_image_core.yml
|
||||
target_name: N310_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
# N320 FPGA targets to build (if build_n3xx is true)
|
||||
- name: n320_full_targets_matrix
|
||||
type: object
|
||||
default:
|
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N320_HG:
|
||||
image_core: n320_rfnoc_image_core.yml
|
||||
target_name: N320_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
N320_XG:
|
||||
image_core: n320_rfnoc_image_core.yml
|
||||
target_name: N320_XG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
N320_WX:
|
||||
image_core: n320_rfnoc_image_core.yml
|
||||
target_name: N320_WX
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
N320_AA:
|
||||
image_core: n320_rfnoc_bist_core.yml
|
||||
target_name: N320_AA
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
N320_AQ:
|
||||
image_core: n320_rfnoc_image_core.yml
|
||||
target_name: N320_AQ
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
N320_XQ:
|
||||
image_core: n320_rfnoc_image_core.yml
|
||||
target_name: N320_XQ
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
- name: n320_reduced_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
N320_HG:
|
||||
image_core: n320_rfnoc_image_core.yml
|
||||
target_name: N320_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
|
||||
|
||||
stages:
|
||||
|
||||
### START: N300 stages
|
||||
|
||||
- stage: build_n300_ip_stage
|
||||
displayName: Build N300 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.n3xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_n3xx }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/n3xx
|
||||
ip_target: N300_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
num_jobs: ${{ parameters.num_ip_jobs }}
|
||||
|
||||
- stage: build_n300_targets_stage
|
||||
displayName: Build N300 FPGA Targets
|
||||
dependsOn: build_n300_ip_stage
|
||||
condition: succeeded('build_n300_ip_stage')
|
||||
jobs:
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.n300_full_targets_matrix }}
|
||||
ip_artifact: N300_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/n3xx
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
- ${{ if eq(parameters.package_and_publish_images, false) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.n300_reduced_targets_matrix }}
|
||||
ip_artifact: N300_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/n3xx
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_n300_packages_stage
|
||||
displayName: Package & Publish N300 Binaries
|
||||
dependsOn: build_n300_targets_stage
|
||||
condition: and(succeeded('build_n300_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: n3xx_n300_fpga_default
|
||||
artifacts_matrix: ${{ parameters.n300_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/n3xx/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: N300 stages
|
||||
|
||||
### START: N310 stages
|
||||
|
||||
- stage: build_n310_ip_stage
|
||||
displayName: Build N310 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.n3xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_n3xx }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/n3xx
|
||||
ip_target: N310_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
num_jobs: ${{ parameters.num_ip_jobs }}
|
||||
|
||||
- stage: build_n310_targets_stage
|
||||
displayName: Build N310 FPGA Targets
|
||||
dependsOn: build_n310_ip_stage
|
||||
condition: succeeded('build_n310_ip_stage')
|
||||
jobs:
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.n310_full_targets_matrix }}
|
||||
ip_artifact: N310_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/n3xx
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
- ${{ if eq(parameters.package_and_publish_images, false) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.n310_reduced_targets_matrix }}
|
||||
ip_artifact: N310_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/n3xx
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_n310_packages_stage
|
||||
displayName: Package & Publish N310 Binaries
|
||||
dependsOn: build_n310_targets_stage
|
||||
condition: and(succeeded('build_n310_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: n3xx_n310_fpga_default
|
||||
artifacts_matrix: ${{ parameters.n310_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/n3xx/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: N310 stages
|
||||
|
||||
### START: N320 stages
|
||||
|
||||
- stage: build_n320_ip_stage
|
||||
displayName: Build N320 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.n3xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_n3xx }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/n3xx
|
||||
ip_target: N320_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
num_jobs: ${{ parameters.num_ip_jobs }}
|
||||
|
||||
- stage: build_n320_targets_stage
|
||||
displayName: Build N320 FPGA Targets
|
||||
dependsOn: build_n320_ip_stage
|
||||
condition: succeeded('build_n320_ip_stage')
|
||||
jobs:
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.n320_full_targets_matrix }}
|
||||
ip_artifact: N320_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/n3xx
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
- ${{ if eq(parameters.package_and_publish_images, false) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.n320_reduced_targets_matrix }}
|
||||
ip_artifact: N320_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/n3xx
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_n320_packages_stage
|
||||
displayName: Package & Publish N320 Binaries
|
||||
dependsOn: build_n320_targets_stage
|
||||
condition: and(succeeded('build_n320_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: n3xx_n320_fpga_default
|
||||
artifacts_matrix: ${{ parameters.n320_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/n3xx/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: N320 stages
|
||||
|
||||
197
fpga/.ci/devices/job-build-x300.yml
Normal file
197
fpga/.ci/devices/job-build-x300.yml
Normal file
@ -0,0 +1,197 @@
|
||||
#
|
||||
# Copyright 2024 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
#
|
||||
# This template defines a stages-based pipeline for building X300 and X310 FPGA.
|
||||
#
|
||||
# See https://aka.ms/yaml for pipeline YAML documentation.
|
||||
#
|
||||
|
||||
parameters:
|
||||
## Optional parameters
|
||||
# Run testbenches
|
||||
- name: run_testbenches
|
||||
type: boolean
|
||||
default: true
|
||||
# Option to ignore cached artifacts (if available) and perform
|
||||
# a clean IP build.
|
||||
- name: clean_ip_build
|
||||
type: boolean
|
||||
default: false
|
||||
# Number of parallel jobs to use for IP build
|
||||
- name: num_ip_jobs
|
||||
type: number
|
||||
default: 5
|
||||
# Option to publish intermediate files
|
||||
- name: publish_int_files
|
||||
type: boolean
|
||||
default: false
|
||||
# Package and publish images
|
||||
- name: package_and_publish_images
|
||||
type: boolean
|
||||
default: true
|
||||
# Package access in the SDR server ('Internal' or 'Public')
|
||||
- name: package_access
|
||||
type: string
|
||||
default: 'Internal'
|
||||
# Build X300 FPGA targets
|
||||
- name: build_x3x0
|
||||
type: boolean
|
||||
default: true
|
||||
# X300 FPGA targets to build (if build_x300 is true)
|
||||
- name: x300_full_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X300_HG:
|
||||
image_core: x300_rfnoc_image_core.yml
|
||||
target_name: X300_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X300_XG:
|
||||
image_core: x300_rfnoc_image_core.yml
|
||||
target_name: X300_XG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
- name: x300_reduced_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X300_XG:
|
||||
image_core: x300_rfnoc_image_core.yml
|
||||
target_name: X300_XG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
# X310 FPGA targets to build (if build_x310 is true)
|
||||
- name: x310_full_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X310_HG:
|
||||
image_core: x310_rfnoc_image_core.yml
|
||||
target_name: X310_HG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X310_XG:
|
||||
image_core: x310_rfnoc_image_core.yml
|
||||
target_name: X310_XG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
- name: x310_reduced_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X310_XG:
|
||||
image_core: x310_rfnoc_image_core.yml
|
||||
target_name: X310_XG
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
|
||||
|
||||
stages:
|
||||
|
||||
### START: X300 stages
|
||||
|
||||
- stage: build_x300_ip_stage
|
||||
displayName: Build X300 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x3xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_x3x0 }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/x300
|
||||
ip_target: X300_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
num_jobs: ${{ parameters.num_ip_jobs }}
|
||||
|
||||
- stage: build_x300_targets_stage
|
||||
displayName: Build X300 FPGA Targets
|
||||
dependsOn: build_x300_ip_stage
|
||||
condition: succeeded('build_x300_ip_stage')
|
||||
jobs:
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x300_full_targets_matrix }}
|
||||
ip_artifact: X300_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x300
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
- ${{ if eq(parameters.package_and_publish_images, false) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x300_reduced_targets_matrix }}
|
||||
ip_artifact: X300_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x300
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_x300_packages_stage
|
||||
displayName: Package & Publish X300 Binaries
|
||||
dependsOn: build_x300_targets_stage
|
||||
condition: and(succeeded('build_x300_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: x3xx_x300_fpga_default
|
||||
artifacts_matrix: ${{ parameters.x300_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/x300/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: X300 stages
|
||||
|
||||
### START: X310 stages
|
||||
|
||||
- stage: build_x310_ip_stage
|
||||
displayName: Build X310 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x3xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_x3x0 }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/x300
|
||||
ip_target: X310_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
|
||||
- stage: build_x310_targets_stage
|
||||
displayName: Build X310 FPGA Targets
|
||||
dependsOn: build_x310_ip_stage
|
||||
condition: succeeded('build_x310_ip_stage')
|
||||
jobs:
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x310_full_targets_matrix }}
|
||||
ip_artifact: X310_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x300
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
- ${{ if eq(parameters.package_and_publish_images, false) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x310_reduced_targets_matrix }}
|
||||
ip_artifact: X310_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x300
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_x310_packages_stage
|
||||
displayName: Package & Publish X310 Binaries
|
||||
dependsOn: build_x310_targets_stage
|
||||
condition: and(succeeded('build_x310_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: x3xx_x310_fpga_default
|
||||
artifacts_matrix: ${{ parameters.x310_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/x300/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: X310 stages
|
||||
267
fpga/.ci/devices/job-build-x400.yml
Normal file
267
fpga/.ci/devices/job-build-x400.yml
Normal file
@ -0,0 +1,267 @@
|
||||
#
|
||||
# Copyright 2024 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
#
|
||||
# This template defines a stages-based pipeline for building X410 and X440 FPGA.
|
||||
#
|
||||
# See https://aka.ms/yaml for pipeline YAML documentation.
|
||||
#
|
||||
|
||||
parameters:
|
||||
## Optional parameters
|
||||
# Run testbenches
|
||||
- name: run_testbenches
|
||||
type: boolean
|
||||
default: true
|
||||
# Option to ignore cached artifacts (if available) and perform
|
||||
# a clean IP build.
|
||||
- name: clean_ip_build
|
||||
type: boolean
|
||||
default: false
|
||||
# Number of parallel jobs to use for IP build
|
||||
- name: num_ip_jobs
|
||||
type: number
|
||||
default: 5
|
||||
# Option to publish intermediate files
|
||||
- name: publish_int_files
|
||||
type: boolean
|
||||
default: false
|
||||
# Package and publish images
|
||||
- name: package_and_publish_images
|
||||
type: boolean
|
||||
default: true
|
||||
# Package access in the SDR server ('Internal' or 'Public')
|
||||
- name: package_access
|
||||
type: string
|
||||
default: 'Internal'
|
||||
# Build X410 FPGA targets
|
||||
- name: build_x410
|
||||
type: boolean
|
||||
default: true
|
||||
# X410 FPGA targets to build(if triggered by changeset, packaging enabled)
|
||||
- name: x410_full_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X410_X4_200:
|
||||
image_core: x410_200_rfnoc_image_core.yml
|
||||
target_name: X410_X4_200
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X410_UC_200:
|
||||
image_core: x410_200_rfnoc_image_core.yml
|
||||
target_name: X410_UC_200
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X410_X4_400:
|
||||
image_core: x410_400_d_rfnoc_image_core.yml
|
||||
target_name: X410_X4_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X410_CG_400:
|
||||
image_core: x410_400_rfnoc_image_core.yml
|
||||
target_name: X410_CG_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
- name: x410_reduced_targets_matrix
|
||||
# X410 FPGA targets to build (if triggered by changeset, no packaging)
|
||||
type: object
|
||||
default:
|
||||
X410_X4_200:
|
||||
image_core: x410_200_rfnoc_image_core.yml
|
||||
target_name: X410_X4_200
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X410_X4_400:
|
||||
image_core: x410_400_d_rfnoc_image_core.yml
|
||||
target_name: X410_X4_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
# Build X440 FPGA targets
|
||||
- name: build_x440
|
||||
type: boolean
|
||||
default: true
|
||||
# X440 FPGA targets to build(if triggered by changeset, packaging enabled)
|
||||
- name: x440_full_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X440_CG_1600:
|
||||
image_core: x440_1600_rfnoc_image_core.yml
|
||||
target_name: X440_CG_1600
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X440_CG_400:
|
||||
image_core: x440_400_rfnoc_image_core.yml
|
||||
target_name: X440_CG_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X440_X4_1600:
|
||||
image_core: x440_1600_d_rfnoc_image_core.yml
|
||||
target_name: X440_X4_1600
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X440_X4_400:
|
||||
image_core: x440_400_d_rfnoc_image_core.yml
|
||||
target_name: X440_X4_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X440_X4_200:
|
||||
image_core: x440_200_rfnoc_image_core.yml
|
||||
target_name: X440_X4_200
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
# X440 FPGA targets to build (if triggered by changeset, no packaging)
|
||||
- name: x440_reduced_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
X440_CG_400:
|
||||
image_core: x440_400_rfnoc_image_core.yml
|
||||
target_name: X440_CG_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
X440_X4_400:
|
||||
image_core: x440_400_d_rfnoc_image_core.yml
|
||||
target_name: X440_X4_400
|
||||
timeout: 720
|
||||
max_attempts: 2
|
||||
# Requested X410 targets(used if build_x410 is true)
|
||||
- name: x410_requests_matrix
|
||||
type: object
|
||||
displayName: X410 Targets
|
||||
default: []
|
||||
# Requested X440 target(used if build_x440 is true)
|
||||
- name: x440_requests_matrix
|
||||
type: object
|
||||
displayName: X440 Targets
|
||||
default: []
|
||||
|
||||
stages:
|
||||
|
||||
### START: X410 stages
|
||||
|
||||
- stage: build_x410_ip_stage
|
||||
displayName: Build X410 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x4xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_x410 }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/x400
|
||||
ip_target: X410_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
num_jobs: ${{ parameters.num_ip_jobs }}
|
||||
|
||||
- stage: build_x410_targets_stage
|
||||
displayName: Build X410 FPGA Targets
|
||||
dependsOn: build_x410_ip_stage
|
||||
condition: succeeded('build_x410_ip_stage')
|
||||
jobs:
|
||||
# trigger full list of targets if packaging is enabled
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x410_full_targets_matrix }}
|
||||
ip_artifact: X410_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
# trigger reduced list of targets if packaging is disabled, and no specific targets are requested
|
||||
- ${{ if and(eq(parameters.package_and_publish_images, false),eq(parameters.build_x410, false)) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x410_reduced_targets_matrix }}
|
||||
ip_artifact: X410_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
# trigger specific targets if packaging is disabled, and specific targets are requested
|
||||
- ${{ if and(eq(parameters.package_and_publish_images, true),eq(parameters.build_x410, true)) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x410_requests_matrix }}
|
||||
ip_artifact: X410_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_x410_packages_stage
|
||||
displayName: Package & Publish X410 Binaries
|
||||
dependsOn: build_x410_targets_stage
|
||||
condition: and(succeeded('build_x410_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: x4xx_x410_fpga_default
|
||||
artifacts_matrix: ${{ parameters.x410_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/x400/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: X410 stages
|
||||
|
||||
### START: X440 stages
|
||||
|
||||
- stage: build_x440_ip_stage
|
||||
displayName: Build X440 IP
|
||||
dependsOn: analyze_changeset
|
||||
condition: and( succeeded(),
|
||||
or(
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.x4xx'),
|
||||
contains(dependencies.analyze_changeset.outputs['analyze.gen_build_list.HdlChangeList'], 'fpga.usrp3.all'),
|
||||
eq('${{ parameters.build_x440 }}', 'true')
|
||||
)
|
||||
)
|
||||
jobs:
|
||||
- template: ../templates/job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/x400
|
||||
ip_target: X440_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
|
||||
- stage: build_x440_targets_stage
|
||||
displayName: Build X440 FPGA Targets
|
||||
dependsOn: build_x440_ip_stage
|
||||
condition: succeeded('build_x440_ip_stage')
|
||||
jobs:
|
||||
# trigger full list of targets if packaging is enabled
|
||||
- ${{ if eq(parameters.package_and_publish_images, true) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x440_full_targets_matrix }}
|
||||
ip_artifact: X440_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
# trigger reduced list of targets if packaging is disabled, and no specific targets are requested
|
||||
- ${{ if and(eq(parameters.package_and_publish_images, false),eq(parameters.build_x440, false)) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x440_reduced_targets_matrix }}
|
||||
ip_artifact: X440_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
# trigger specific targets if packaging is disabled, and specific targets are requested
|
||||
- ${{ if and(eq(parameters.package_and_publish_images, false),eq(parameters.build_x440, true)) }}:
|
||||
- template: ../templates/job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x440_requests_matrix }}
|
||||
ip_artifact: X440_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
|
||||
- stage: create_x440_packages_stage
|
||||
displayName: Package & Publish X440 Binaries
|
||||
dependsOn: build_x440_targets_stage
|
||||
condition: and(succeeded('build_x440_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: ../templates/job-package-images.yml
|
||||
parameters:
|
||||
package_name: x4xx_x440_fpga_default
|
||||
artifacts_matrix: ${{ parameters.x440_full_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/x400/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
|
||||
### END: X440 stages
|
||||
@ -26,7 +26,7 @@ parameters:
|
||||
- name: package_and_publish_images
|
||||
type: boolean
|
||||
displayName: Package & Publish Images
|
||||
default: true
|
||||
default: false
|
||||
- name: package_access
|
||||
type: string
|
||||
values:
|
||||
@ -34,14 +34,35 @@ parameters:
|
||||
- 'files.ettus.com (Public)'
|
||||
displayName: Published Package Access
|
||||
default: 'Internal'
|
||||
- name: skip_analyze_changeset
|
||||
type: boolean
|
||||
displayName: Skip Analyze Changeset
|
||||
default: false
|
||||
- name: build_x3x0
|
||||
type: boolean
|
||||
displayName: Build X3x0
|
||||
default: false
|
||||
- name: build_n3xx
|
||||
type: boolean
|
||||
displayName: Build N3xx
|
||||
default: false
|
||||
- name: build_e31x
|
||||
type: boolean
|
||||
displayName: Build E31x
|
||||
default: false
|
||||
- name: build_e32x
|
||||
type: boolean
|
||||
displayName: Build E32x
|
||||
default: false
|
||||
- name: build_x410
|
||||
type: boolean
|
||||
displayName: Build X410
|
||||
default: true
|
||||
default: false
|
||||
- name: build_x440
|
||||
type: boolean
|
||||
displayName: Build X440
|
||||
default: true
|
||||
default: false
|
||||
# Requested X410 targets
|
||||
- name: x410_targets_matrix
|
||||
type: object
|
||||
displayName: X410 Targets
|
||||
@ -105,7 +126,7 @@ pr:
|
||||
paths:
|
||||
include:
|
||||
- fpga/usrp3/lib
|
||||
- fpga/usrp3/top/x400
|
||||
- fpga/usrp3/top
|
||||
- fpga/.ci
|
||||
|
||||
schedules:
|
||||
@ -124,6 +145,11 @@ extends:
|
||||
publish_int_files: true
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
skip_analyze_changeset: ${{ parameters.skip_analyze_changeset }}
|
||||
build_x3x0: ${{ parameters.build_x3x0 }}
|
||||
build_n3xx: ${{ parameters.build_n3xx }}
|
||||
build_e31x: ${{ parameters.build_e31x }}
|
||||
build_e32x: ${{ parameters.build_e32x }}
|
||||
build_x410: ${{ parameters.build_x410 }}
|
||||
build_x440: ${{ parameters.build_x440 }}
|
||||
x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
|
||||
|
||||
@ -35,6 +35,26 @@ parameters:
|
||||
- 'files.ettus.com (Public)'
|
||||
displayName: Published Package Access
|
||||
default: 'Internal'
|
||||
- name: skip_analyze_changeset
|
||||
type: boolean
|
||||
displayName: Skip Analyze Changeset
|
||||
default: true
|
||||
- name: build_x3x0
|
||||
type: boolean
|
||||
displayName: Build X3x0
|
||||
default: true
|
||||
- name: build_n3xx
|
||||
type: boolean
|
||||
displayName: Build N3xx
|
||||
default: true
|
||||
- name: build_e31x
|
||||
type: boolean
|
||||
displayName: Build E31x
|
||||
default: true
|
||||
- name: build_e32x
|
||||
type: boolean
|
||||
displayName: Build E32x
|
||||
default: true
|
||||
- name: build_x410
|
||||
type: boolean
|
||||
displayName: Build X410
|
||||
@ -52,7 +72,7 @@ trigger:
|
||||
paths:
|
||||
include:
|
||||
- fpga/usrp3/lib
|
||||
- fpga/usrp3/top/x400
|
||||
- fpga/usrp3/top
|
||||
- fpga/.ci
|
||||
|
||||
pr: none
|
||||
@ -72,5 +92,10 @@ extends:
|
||||
clean_ip_build: ${{ parameters.clean_ip_build }}
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
skip_analyze_changeset: ${{ parameters.skip_analyze_changeset }}
|
||||
build_x3x0: ${{ parameters.build_x3x0 }}
|
||||
build_n3xx: ${{ parameters.build_n3xx }}
|
||||
build_e31x: ${{ parameters.build_e31x }}
|
||||
build_e32x: ${{ parameters.build_e32x }}
|
||||
build_x410: ${{ parameters.build_x410 }}
|
||||
build_x440: ${{ parameters.build_x440 }}
|
||||
|
||||
37
fpga/.ci/templates/changeset_build_list.yaml
Normal file
37
fpga/.ci/templates/changeset_build_list.yaml
Normal file
@ -0,0 +1,37 @@
|
||||
# build targets:
|
||||
# - fpga.usrp3.$PLATFORM: Build FPGA images for given platforms.
|
||||
|
||||
# library changes
|
||||
- re: fpga/usrp3/lib
|
||||
add:
|
||||
- fpga.usrp3.all
|
||||
|
||||
# Device-specific changes.
|
||||
- re: fpga/usrp3/top/x400
|
||||
add:
|
||||
- fpga.usrp3.x4xx
|
||||
- re: fpga/usrp3/top/x300
|
||||
add:
|
||||
- fpga.usrp3.x3xx
|
||||
- re: fpga/usrp3/top/b200
|
||||
add:
|
||||
- fpga.usrp3.b200
|
||||
- re: fpga/usrp3/top/b200mini
|
||||
add:
|
||||
- fpga.usrp3.b200mini
|
||||
- re: fpga/usrp3/top/e31x
|
||||
add:
|
||||
- fpga.usrp3.e31x
|
||||
- re: fpga/usrp3/top/e320
|
||||
add:
|
||||
- fpga.usrp3.e320
|
||||
- re: fpga/usrp3/top/n3xx
|
||||
add:
|
||||
- fpga.usrp3.n3xx
|
||||
|
||||
###############################################################################
|
||||
# CI CHANGES
|
||||
###############################################################################
|
||||
- re: fpga/.ci/*
|
||||
add:
|
||||
- fpga.usrp3.all
|
||||
33
fpga/.ci/templates/job-analyze-changeset.yml
Normal file
33
fpga/.ci/templates/job-analyze-changeset.yml
Normal file
@ -0,0 +1,33 @@
|
||||
# This job will execute the changeset_testlist.py script, which in turn will
|
||||
# compute a list of tests that need to be executed.
|
||||
# The script itself produces the correct output to set a variable for a future
|
||||
# stage.
|
||||
|
||||
parameters:
|
||||
- name: skip_analyze_changeset
|
||||
type: boolean
|
||||
default: false
|
||||
|
||||
jobs:
|
||||
- job: analyze
|
||||
displayName: Analyze Changeset
|
||||
pool:
|
||||
name: Drivers-NIBuildFarm-RFMIBUILD
|
||||
demands: sh
|
||||
condition: not(${{ parameters.skip_analyze_changeset }})
|
||||
steps:
|
||||
- checkout: self
|
||||
clean: true
|
||||
- bash: |
|
||||
if [[ $AGENT_OS == "Windows_NT" ]]; then
|
||||
VENV_BIN_DIR="Scripts"
|
||||
else
|
||||
VENV_BIN_DIR="bin"
|
||||
fi
|
||||
python3 -m venv $AGENT_TEMPDIRECTORY/ac_venv
|
||||
$AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/pip install --upgrade pip
|
||||
$AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/pip install ruamel.yaml
|
||||
git branch
|
||||
$AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/python3 tools/changeset_testlist.py --target-branch origin/master --set-azdo-var HdlChangeList --rule-file fpga/.ci/templates/changeset_build_list.yaml
|
||||
name: gen_build_list
|
||||
displayName: Generate Build-List
|
||||
@ -38,11 +38,35 @@ parameters:
|
||||
- name: package_access
|
||||
type: string
|
||||
default: 'Internal'
|
||||
# Skip analyze changeset stage
|
||||
- name: skip_analyze_changeset
|
||||
type: boolean
|
||||
default: false
|
||||
# Build X3x0 FPGA targets
|
||||
- name: build_x3x0
|
||||
type: boolean
|
||||
displayName: Build X3x0
|
||||
default: false
|
||||
# Build N3xx FPGA targets
|
||||
- name: build_n3xx
|
||||
type: boolean
|
||||
displayName: Build N3xx
|
||||
default: false
|
||||
# Build E31x FPGA targets
|
||||
- name: build_e31x
|
||||
type: boolean
|
||||
displayName: Build E31x
|
||||
default: false
|
||||
# Build E32x FPGA targets
|
||||
- name: build_e32x
|
||||
type: boolean
|
||||
displayName: Build E32x
|
||||
default: false
|
||||
# Build X410 FPGA targets
|
||||
- name: build_x410
|
||||
type: boolean
|
||||
default: true
|
||||
# X410 FPGA targets to build (if build_x410 is true)
|
||||
default: false
|
||||
# Requested X410 targets (if build_x410 is true)
|
||||
- name: x410_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
@ -69,8 +93,8 @@ parameters:
|
||||
# Build X440 FPGA targets
|
||||
- name: build_x440
|
||||
type: boolean
|
||||
default: true
|
||||
# X440 FPGA targets to build (if build_x440 is true)
|
||||
default: false
|
||||
# Requested X440 targets
|
||||
- name: x440_targets_matrix
|
||||
type: object
|
||||
default:
|
||||
@ -123,81 +147,76 @@ stages:
|
||||
### END: Testbenches stage
|
||||
|
||||
|
||||
### START: X410 stages
|
||||
|
||||
- stage: build_x410_ip_stage
|
||||
displayName: Build X410 IP
|
||||
### START: Change History analysis stage
|
||||
- stage: analyze_changeset
|
||||
displayName: Analyze Changeset
|
||||
dependsOn: []
|
||||
condition: and(succeeded(), eq('${{ parameters.build_x410 }}', 'true'))
|
||||
jobs:
|
||||
- template: job-build-ip.yml
|
||||
- template: job-analyze-changeset.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/x400
|
||||
ip_target: X410_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
num_jobs: ${{ parameters.num_ip_jobs }}
|
||||
skip_analyze_changeset: ${{ parameters.skip_analyze_changeset }}
|
||||
|
||||
- stage: build_x410_targets_stage
|
||||
displayName: Build X410 FPGA Targets
|
||||
dependsOn: build_x410_ip_stage
|
||||
condition: succeeded('build_x410_ip_stage')
|
||||
jobs:
|
||||
- template: job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x410_targets_matrix }}
|
||||
ip_artifact: X410_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
### END: Change History analysis stage
|
||||
|
||||
- stage: create_x410_packages_stage
|
||||
displayName: Package & Publish X410 Binaries
|
||||
dependsOn: build_x410_targets_stage
|
||||
condition: and(succeeded('build_x410_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: job-package-images.yml
|
||||
parameters:
|
||||
package_name: x4xx_x410_fpga_default
|
||||
artifacts_matrix: ${{ parameters.x410_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/x400/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
### START: X400 stages
|
||||
|
||||
### END: X410 stages
|
||||
- template: ../devices/job-build-x400.yml
|
||||
parameters:
|
||||
clean_ip_build: ${{ parameters.clean_ip_build }}
|
||||
publish_int_files: true
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
build_x410: ${{ parameters.build_x410 }}
|
||||
build_x440: ${{ parameters.build_x440 }}
|
||||
x410_requests_matrix: ${{ parameters.x410_targets_matrix }}
|
||||
x440_requests_matrix: ${{ parameters.x440_targets_matrix }}
|
||||
|
||||
### START: X440 stages
|
||||
### END: X400 stages
|
||||
|
||||
- stage: build_x440_ip_stage
|
||||
displayName: Build X440 IP
|
||||
dependsOn: []
|
||||
condition: and(succeeded(), eq('${{ parameters.build_x440 }}', 'true'))
|
||||
jobs:
|
||||
- template: job-build-ip.yml
|
||||
parameters:
|
||||
directory: uhddev/fpga/usrp3/top/x400
|
||||
ip_target: X440_IP
|
||||
clean_build: ${{ parameters.clean_ip_build }}
|
||||
### START: X3x0 stages
|
||||
|
||||
- stage: build_x440_targets_stage
|
||||
displayName: Build X440 FPGA Targets
|
||||
dependsOn: build_x440_ip_stage
|
||||
condition: succeeded('build_x440_ip_stage')
|
||||
jobs:
|
||||
- template: job-build-fpga.yml
|
||||
parameters:
|
||||
targets_matrix: ${{ parameters.x440_targets_matrix }}
|
||||
ip_artifact: X440_IP
|
||||
top_dir: uhddev/fpga/usrp3/top/x400
|
||||
publish_int_files: ${{ parameters.publish_int_files }}
|
||||
- template: ../devices/job-build-x300.yml
|
||||
parameters:
|
||||
clean_ip_build: ${{ parameters.clean_ip_build }}
|
||||
publish_int_files: true
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
build_x3x0: ${{ parameters.build_x3x0 }}
|
||||
|
||||
- stage: create_x440_packages_stage
|
||||
displayName: Package & Publish X440 Binaries
|
||||
dependsOn: build_x440_targets_stage
|
||||
condition: and(succeeded('build_x440_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
|
||||
jobs:
|
||||
- template: job-package-images.yml
|
||||
parameters:
|
||||
package_name: x4xx_x440_fpga_default
|
||||
artifacts_matrix: ${{ parameters.x440_targets_matrix }}
|
||||
build_directory: uhddev/fpga/usrp3/top/x400/build/
|
||||
package_access: ${{ parameters.package_access }}
|
||||
### END: X3x0 stages
|
||||
|
||||
### END: X440 stages
|
||||
### START: N3xx stages
|
||||
|
||||
- template: ../devices/job-build-n3xx.yml
|
||||
parameters:
|
||||
clean_ip_build: ${{ parameters.clean_ip_build }}
|
||||
publish_int_files: true
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
build_n3xx: ${{ parameters.build_n3xx }}
|
||||
|
||||
### END: N3xx stages
|
||||
|
||||
### START: E31x stages
|
||||
|
||||
- template: ../devices/job-build-e31x.yml
|
||||
parameters:
|
||||
clean_ip_build: ${{ parameters.clean_ip_build }}
|
||||
publish_int_files: true
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
build_e31x: ${{ parameters.build_e31x }}
|
||||
|
||||
### END: E31x stages
|
||||
|
||||
### START: E320 stages
|
||||
|
||||
- template: ../devices/job-build-e320.yml
|
||||
parameters:
|
||||
clean_ip_build: ${{ parameters.clean_ip_build }}
|
||||
publish_int_files: true
|
||||
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
||||
package_access: ${{ parameters.package_access }}
|
||||
build_e320: ${{ parameters.build_e32x }}
|
||||
|
||||
### END: E320 stages
|
||||
|
||||
Loading…
Reference in New Issue
Block a user