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fpga: ci: move patches to IT owned share

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Max Köhler 2024-10-18 00:28:50 +02:00 committed by mkoop-ni
parent eab6e8c7dd
commit 77bf8a9d81
4 changed files with 3 additions and 9 deletions
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4
fpga/.ci/scripts/run_setup.sh
View File

@ -49,11 +49,11 @@ export PATCHES_DIR=$BUILD_SOURCESDIRECTORY/patches
mkdir -p $PATCHES_DIR
pushd $PATCHES_DIR
# Fetch the AR76780 patch for Vivado
wget -q $PATCHES_PATH/2021.1/AR76780_Vivado_2021_1_preliminary_rev1.zip -O ./AR76780_Vivado_2021_1_preliminary_rev1.zip
cp /opt/synced/Xilinx/patches/AR76780_Vivado_2021_1_preliminary_rev1.zip ./AR76780_Vivado_2021_1_preliminary_rev1.zip
unzip -q -o ./AR76780_Vivado_2021_1_preliminary_rev1.zip -d ./AR76780_Vivado_2021/
rm -f AR76780_Vivado_2021_1_preliminary_rev1.zip
# Add the AR76780 patch for the simulation library
wget -q $PATCHES_PATH/2021.1/fir_compiler_v7_2_76780.zip -O ./fir_compiler_v7_2_76780.zip
cp /opt/synced/modelsim/patches/fir_compiler_v7_2_76780.zip ./fir_compiler_v7_2_76780.zip
unzip -q -o ./fir_compiler_v7_2_76780.zip -d ./fir_compiler_v7_2_76780/
rm -f ./fir_compiler_v7_2_76780.zip
popd

4
fpga/.ci/templates/job-build-fpga.yml
View File

@ -105,8 +105,6 @@ jobs:
--num $(max_attempts) --seed $(($(System.JobAttempt)-1)) --persistent
pip3 uninstall -y uhd
workingDirectory: ${{ parameters.top_dir }}
env:
PATCHES_PATH: $(sdr-vivado-patches)
displayName: 'Build Target'
name: build_target
@ -122,7 +120,7 @@ jobs:
echo "##vso[task.setvariable variable=BuildArtifactDir;isOutput=true]$BUILD_ARTIFACT_DIR"
workingDirectory: ${{ parameters.top_dir }}
displayName: 'Find Build Artifact Directory'
name: find_build_artifact_dir
name: find_build_artifact_dir
condition: and(always(), eq('${{ parameters.publish_int_files }}', true))
# Publish intermediate files.

2
fpga/.ci/templates/job-build-ip.yml
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@ -92,8 +92,6 @@ jobs:
mkdir -p build-ip/.ci/
git rev-parse --verify HEAD 2>/dev/null 1>build-ip/.ci/build-hash
workingDirectory: ${{ parameters.directory }}
env:
PATCHES_PATH: $(sdr-vivado-patches)
displayName: "Build IP"
- publish: ${{ parameters.directory }}/build-ip

2
fpga/.ci/templates/job-run-testbenches.yml
View File

@ -30,6 +30,4 @@ jobs:
python3 ./run_testbenches.py --logged --simulator modelsim --excludes=modelsim.excludes -j4 run
popd
workingDirectory: uhddev/fpga/usrp3
env:
PATCHES_PATH: $(sdr-vivado-patches)
displayName: "Run Testbenches"