mirror of https://github.com/EttusResearch/uhd.git synced 2026-10-25 17:36:10 +00:00

History

Jonathon Pendlum c352536264 fpga: x400: Add PPS interface to X410/X440 BSP This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`) for X440 which allows modules inside the RFNoC image core to access the FPGA. Note that accessing the PPS signal is generally not required for RFNoC blocks which require access to timing. Co-authored-by: Martin Braun <martin.braun@ettus.com>		2024-06-11 10:20:07 +02:00
..
.ci	fpga: ci: Clean out rfnoc_image_builder install	2024-05-03 08:27:20 -05:00
docs	fpga: docs: Bump minimum Python version to 3.6	2024-01-11 00:10:00 -06:00
usrp1	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
usrp2	fpga: usrp2: update build tools to use python3	2021-12-08 12:08:29 -08:00
usrp3	fpga: x400: Add PPS interface to X410/X440 BSP	2024-06-11 10:20:07 +02:00
.clang-format	fpga: Clear clang-format settings for FPGA code	2023-08-17 10:51:55 -05:00
.gitignore	fpga: Add more spurious files to gitignore	2023-12-13 17:28:09 -06:00
CODING.md	fpga: Update recommended HDL header guideline	2021-06-10 11:56:58 -05:00
CONTRIBUTING.md	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
README.md	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00

README.md

Ettus Research USRP FPGA HDL Source

Welcome to the USRP FPGA HDL source code tree! This repository contains free & open-source FPGA HDL for the Universal Software Radio Peripheral (USRP™) SDR platform, created and sold by Ettus Research. A large percentage of the source code is written in Verilog.

Product Generations

This repository contains the FPGA source for the following generations of USRP devices.

Generation 1

Directory: usrp1
Devices: USRP Classic Only
Tools: Quartus from Altera
Build Instructions

Generation 2

Directory: usrp2
Devices: USRP N2X0, USRP B100, USRP E1X0, USRP2
Tools: ISE from Xilinx, GNU make
Build Instructions
Customization Instructions

Generation 3

Directory: usrp3
Devices: USRP B2X0, USRP X Series, USRP E3X0, USRP N3xx
Tools: Vivado from Xilinx, ISE from Xilinx, GNU make
Build Instructions
Simulation

Pre-built FPGA Images

Pre-built FPGA and Firmware images are not hosted here. Please visit the FPGA and Firmware manual page for instructions on downloading and using pre-built images. In most cases, running the following command will do the right thing.

$ uhd_images_downloader

Building This Manual

This FPGA manual is available on the web at http://files.ettus.com/manual/md_fpga.html for the most recent stable version of UHD. If you wish to read documentation for a custom/unstable branch you will need to build it and open it locally using a web browser. To do so please install Doxygen on your system and run the following commands:

$ cd docs
$ make
$ sensible-browser html/index.html