fpga: fix various warnings in CPLD related code

fpga/usrp3/lib/control/reset_sync.v

@@ -14,7 +14,7 @@ module reset_sync (
   // glitch-free input reset
   input  reset_in,
   // output reset in the clk domain
-  output reg reset_out);
+  output reg reset_out = 1'b1);
 
   wire reset_c;
 

fpga/usrp3/lib/control/simple_spi_core_64bit.v

@@ -68,7 +68,7 @@ module simple_spi_core_64bit
 
     //spi interface, slave selects, clock, data in, data out
     output [WIDTH-1:0] sen,
-    output reg sclk,
+    output reg sclk = CLK_IDLE,
     output reg mosi,
     input miso,
 
@@ -111,14 +111,14 @@ module simple_spi_core_64bit
   localparam POST_IDLE = 4;
   localparam IDLE_SEN = 5;
 
-  reg [2:0] state;
+  reg [2:0] state = WAIT_TRIG;
 
   reg ready_reg;
   assign ready = ready_reg && ~trigger_spi;
 
   //serial clock either idles or is in one of two clock states
   //One pipeline stage to align output data with clock edge.
-  reg sclk_reg;
+  reg sclk_reg = CLK_IDLE;
   always @(posedge clock) begin
     sclk <= sclk_reg;
   end

fpga/usrp3/top/x400/cpld/common/spi_slave.v

@@ -104,15 +104,18 @@ module spi_slave #(
   // Reset with cs_n might occur too early during clk sync.
   // Reset half way through the reception.
   always @(posedge sclk) begin
-    // Complete word was received
-    if (current_bit_index == 7) begin
-      reception_complete_sclk <= 1'b1;
-      received_word <= {receiver_reg[6:0], mosi};
-
-    // Reset after half transaction
-    end else if (current_bit_index == 3) begin
-      reception_complete_sclk <= 1'b0;
-    end
+    case (current_bit_index)
+      3: begin
+        // Reset after half transaction
+        reception_complete_sclk <= 1'b0;
+      end
+      7: begin
+        // Save received word
+        received_word <= {receiver_reg[6:0], mosi};
+        // Set after complete word was received
+        reception_complete_sclk <= 1'b1;
+      end
+    endcase
   end
 
   //---------------------------------------------------------------

fpga/usrp3/top/x400/cpld/common/spi_slave_to_ctrlport_master.v

@@ -151,7 +151,6 @@ module spi_slave_to_ctrlport_master #(
       end
 
       // Detect complete request
-      request_received <= 1'b0;
       if (data_out_valid) begin
         if (write_request && (num_bytes_received == NUM_BYTES_WRITE_REQUEST_PAYLOAD-1)) begin
           request_received <= 1'b1;
@@ -159,7 +158,11 @@ module spi_slave_to_ctrlport_master #(
         end else if (~write_request && (num_bytes_received == NUM_BYTES_READ_REQUEST_PAYLOAD-1)) begin
           request_received <= 1'b1;
           provide_response <= 1'b1;
+        end else begin
+          request_received <= 1'b0;
         end
+      end else begin
+        request_received <= 1'b0;
       end
 
       // Detect end of response on last received byte

fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v

@@ -196,7 +196,8 @@ module ctrlport_byte_deserializer (
         end
 
         default: begin
-          // NOP
+          // dummy assignment to avoid an empty block
+          bytestream_data_out <= 8'bx;
         end
       endcase
     end