Commit Graph

12244 Commits

Author SHA1 Message Date
Max Köhler
5b1bcabcf8 fpga: dsp: register halfband cascade routing selects 2026-09-15 23:47:05 +01:00
Max Köhler
e5c05cfde1 fpga: dsp: flush stale data across reset boundaries 2026-09-15 23:47:05 +01:00
Max Köhler
c1540c92f1 fpga: dsp: simplify interpolation and decimation configuration 2026-09-15 23:47:05 +01:00
Max Köhler
b7a92cd9d9 fpga: dsp: block input during reset and reconfiguration 2026-09-15 23:47:05 +01:00
Max Köhler
efa47018e4 fpga: dsp: distribute reset and clear through DSP paths 2026-09-15 23:47:05 +01:00
Max Köhler
d394ae626a dsp: cic: Add FIFO in CIC interpolation to allow tready bypass 2026-09-15 23:47:05 +01:00
Max Köhler
5ea031a946 fpga: lib: dsp: add multicycle path for CIC barrel shift 2026-09-15 23:47:05 +01:00
Niels Garibaldi
9365ae9b6a fpga: dsp: reverse order of cic barrel shifter
Reversing the order of the barrel shifter module used by the CIC
filter implementations, in order to reduce the possible bits
selectable from the last stage going into the rounding module.
This should make routing easier.
2026-09-15 23:47:05 +01:00
Niels Garibaldi
4904d06da2 fpga: dsp: Reduce CIC comb bus width for cic_filter_interp
We can reduce the bus width of the comb filter stage in the CIC
interpolation filter, as it is the first module in the CIC filter and
only adds one bit per order stage. Therefore, we do not need to
immediately go to the full accumulation bit width needed for the later
integrator stages of the CIC interpolation filter, and can save some
FPGA resources by only extending to the required width for each CIC
stage.

The same logic also applies to the interpolation stage, which only adds
zeros into the bitstream and therefore does not change the bus width.
2026-09-15 23:47:05 +01:00
Niels Garibaldi
57df0ca685 fpga: dsp: Add FIFO_SIZE parameter to CIC comb filter
Adding a FIFO size module parameter to the comb filter module, in
order to selectively set only the last of N-order filter stages to
use a 2-stage FIFO.
2026-09-15 23:47:05 +01:00
Virendra Kakade
285cce69a2 ci: Build UHD RPMs with B310 support
Install nib310rio-dev before configuring the Fedora RPM installer build.
The RPM path runs CMake directly in the build container, so installing the
development package there makes nib310rio/nib310rio.h available when UHD
decides whether to enable B300 support.
2026-09-15 23:44:29 +01:00
Virendra Kakade
eb785ff23b ci: Build UHD DEBs with B310 support
Add nib310rio-dev to the Debian build dependencies so the UHD package
build fails if the B310 userspace header is unavailable instead of
silently disabling B300 support.

The Ubuntu installer pipeline downloads the nib310rio Debian package
artifact and exposes it to pbuilder as a local apt repository. This lets
pbuilder satisfy the new dependency inside the clean build root where
CMake checks for nib310rio/nib310rio.h.
2026-09-15 23:44:29 +01:00
Marian Koop
0d7ed3b1a4 images: Update to final 4.11.0.0 release candidate 2026-09-08 10:24:37 +01:00
Marian Koop
6fbadafde6 cmake: Update stable branch property 2026-09-08 10:24:37 +01:00
Marian Koop
c57e8cb30d doc: Extend x4xx loading the fpga image section. 2026-09-08 10:06:38 +01:00
Martin Anderseck
72d896bd25 CHANGELOG: Correct and update UHD 4.11 features
This adds the Linux kernel update as highlight and corrects the
statement about the X420/X440 repeatable phase offsets.
2026-09-08 09:28:31 +01:00
Jörg Hofrichter
d687c4ebbe host: mpmd based uhd_image_loader: prefer .bin files
Prefer .bin over .bit files when loading FPGA without full
FPGA path name. This changes the order which was introduced
with commit 2618b51cb8.
2026-09-08 09:27:55 +01:00
Michael Dickens
6cb889675f python: add range property tree access 2026-09-08 00:02:36 +01:00
Lars Amsel
9e8b5b9553 examples: Fix l-band capture setup
Because X440 images now can also contain DDC/DUC we cannot direct
connect the radio with the replay block anymore. Instead we have
to rely on the uhd.rfnoc util connect_through_blocks function
which will find a route through the statically connected DDC/DUC
if they are present or connect the SEPs directly if they are not.
2026-09-07 17:06:06 +01:00
Grant Meyerhoff
4caf56aa0d docs: b300: add more complete multi-device sync docs 2026-09-07 17:03:43 +01:00
Virendra Kakade
94fd6241b8 examples: Fix replay capture at coerced sample rates
rfnoc_rx_replay_samples_to_file.py could hang and then abort with
"Timeout while loading replay buffer!" whenever the requested sample
rate was not an integer divisor of the master clock rate. For example,
requesting 200 Msps at an MCR of 368.64 MHz would leave the record
buffer stuck at exactly 50% fullness.

Two problems combined to cause this:

First, the rate was read back from the DDC before the graph was
committed. At that point the DDC's input sample rate property is not
yet valid, so set_output_rate() falls back to setting the output edge
property and returns the uncoerced, requested rate. The example then
reported a rate that the DDC never actually applied.

Second, run_capture() derived the number of samples to request from the
radio with int(radio_rate / rate), truncating instead of rounding. With
a radio rate of 368.64 Msps and a nominal rate of 200 Msps this yielded
a ratio of 1 rather than the decimation the DDC had actually settled on,
so the radio was told to produce only half the samples needed to fill
the record buffer.

The rate is now read back with get_output_rate() after graph.commit(),
when property propagation has completed, and the user is warned when
the requested rate had to be coerced. The rate ratio is computed with
rounding, so the radio is asked for the full number of samples the
record buffer needs.

While here, fix two related issues in the readback path. The DDC port
is now taken from the destination port of the discovered edge rather
than assuming it matches the radio channel index, and the rate is read
per channel (from the DDC where one is present, otherwise from the
radio) so that chains without a DDC are not ignored. Rates are compared
against a tolerance rather than for exact float equality.

Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
2026-09-07 17:03:01 +01:00
Marian Koop
323d066e64 images: Update manifest for v4.11.0.0-rc3 2026-09-02 20:35:42 +01:00
Jörg Hofrichter
9a3a47bb69 CHANGELOG: Update UHD 4.11 new features descriptions
- Updated the description of the fabric resampler addition.
- Corrected the documentation for the default state of the MPM serialization setting.
2026-09-02 18:40:29 +01:00
Frank Dietze
7bd5f8047a debian: update upload_debs.sh 2026-09-02 18:39:53 +01:00
Frank Dietze
635e73e7e0 debian: fix arch strings 2026-09-02 18:39:53 +01:00
Marian Koop
856a3e7dd2 docs: Update statement in x4xx user manual section. 2026-09-02 18:34:54 +01:00
Jörg Hofrichter
7d26845c08 docs: x4xx: Added information on locked FPGA variants 2026-09-02 16:45:32 +01:00
Jörg Hofrichter
218975dd22 CHANGELOG: Added information on X4XX Locked FPGA Variants 2026-09-02 16:45:32 +01:00
Jörg Hofrichter
b5718dc22b mpm: usrp_update_fs: adopt EEPROM path for E31X 2026-09-02 15:55:00 +01:00
Grant Meyerhoff
394768bcff docs: b300: adjust wording with default change
- Tx QEC tracking cals were enabled by default in a recent change.
2026-09-02 10:12:37 +02:00
Javier Valenzuela
31ca7a5497 host: docs: add b300 resource utilization 2026-09-02 10:11:07 +02:00
Virendra Kakade
b8114103c7 docs: b300 streaming docs
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
2026-09-02 10:09:32 +02:00
Wade Fife
081429caa9 fpga: lib: Disable XPM FIFO for Spartan-6 FPGAs 2026-09-02 09:58:09 +02:00
Wade Fife
85e163a0d9 fpga: lib: Add DEVICE parameter to gpif2 and radio_legacy 2026-09-02 09:58:09 +02:00
Wade Fife
6a8a56afb2 fpga: b2xx: Add DEVICE parameter
Adds a DEVICE parameter set to SPARTAN6 to properly indicate the FPGA
device family.
2026-09-02 09:58:09 +02:00
Wade Fife
d110c060f2 fpga: Fix check_timing.py break indent
This fixes an issue introduced by commit 699cff5941, where the break
statement was incorrectly indented outside the for loop.
2026-09-02 09:40:20 +02:00
Grant Meyerhoff
881f19db7c examples: handle sigint in rx_ascii_art_dft 2026-08-28 16:11:32 +01:00
Max Köhler
4e3912efd8 fpga: fix typo in yml files 2026-08-28 16:09:35 +01:00
Max Köhler
9da28f06f7 fpga: x420: Use standard ce clock for DDC and DUC blocks for 400 MHz 2026-08-28 16:09:35 +01:00
Max Köhler
be791eb065 ci: apply target name for X420 FPGA compiles 2026-08-28 16:06:17 +01:00
Max Köhler
0e680f9cb6 image builder: add x420 support 2026-08-28 16:06:17 +01:00
Grant Meyerhoff
e866ff81f9 adrv9032: make tx qec tracking cals default 2026-08-28 15:03:39 +01:00
Jörg Hofrichter
3cfb163340 fpga: e320/n3xx: dts: Fixed PHY mode for 1G connections
Without this change, kernel 6.12 generates the following warning:

nixge 40000000.ethernet (unnamed net_device) (uninitialized): fixed link full duplex 1000Mbps not recognised

With the change, the link is correctly detected as 1G:

nixge 40000000.ethernet sfp0: configuring for fixed/gmii link mode
2026-08-28 15:02:53 +01:00
Niels Garibaldi
17c0114771 fpga: dsp: fix race condition in axi_tag_time_ms
Fixed an issue when multiple timed DDS commands were present, where
the first one was popped and then the second command immediately
got popped as well to the stale a lookahead signal.
The fix is to clear the lookahead signal and threshold signal on
every fifo pop command.
2026-08-28 14:59:35 +01:00
Niels Garibaldi
31be5b875a fpga: dsp: add rounding to CIC filter barrel shifter
Add an additional rounding step to the cic barrel shifter module
to avoid any DC bias occuring, caused by bit truncation without
rounding.
2026-08-28 14:59:35 +01:00
Wade Fife
02f11f970c b310: Flush stale RX data before enabling DMA
Signed-off-by: Grant Meyerhoff <grant.meyerhoff@emerson.com>
2026-08-28 14:58:07 +01:00
Wade Fife
53a1ef762e rfnoc: fir filter: Use burst op to write coefficients 2026-08-27 16:13:24 +01:00
Wade Fife
000cd8e3cb fpga: b310: Fix synthesis-only builds 2026-08-27 16:10:53 +01:00
mschill
0e3b241021 fpga: x440: add X1_200 bifile variant 2026-08-27 13:31:33 +01:00
Marian Koop
84d6af328b ci: Update fpga packaging configs 2026-08-27 08:41:16 +01:00