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map
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fpga: lib: Fix Vivado warnings
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2023-06-09 09:01:04 -05:00 |
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ad5662_auto_spi.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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arb_qualify_master.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_crossbar_intf.sv
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_crossbar_regport.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_crossbar.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_fifo_header.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_forwarding_cam.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_setting_reg.v
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fpga: rfnoc: Add Signal Generator RFNoC block
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2020-07-30 12:51:41 -05:00 |
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axi_slave_mux.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_test_vfifo.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axil_ctrlport_master.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axil_regport_master.v
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fpga: lib: Fix writes in axil_regport_master
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2020-06-04 11:53:10 -05:00 |
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axil_to_ni_regport.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axis_spi.sv
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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axis_to_ctrlport.sv
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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bin2gray.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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binary_encoder.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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clock_div.v
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fpga: lib: Add clock_div module
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2023-04-05 15:10:14 -05:00 |
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clocking_watchdog.sv
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fpga: add clock watch circuit
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2026-08-10 17:21:47 +02:00 |
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ctrlport_spi_adrv_pkg.sv
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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ctrlport_spi_adrv.sv
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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ctrlport_to_axis.sv
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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ctrlport_to_jtag.v
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fpga: lib: move ctrlport_to_jtag to lib sirectory
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2026-08-14 16:32:09 -05:00 |
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ctrlport_to_regport.v
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fpga: lib: Add ctrlport_to_regport bridge
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2020-08-19 12:28:22 -05:00 |
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ctrlport_to_simple_spi_regmap_utils.vh
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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ctrlport_to_simple_spi.sv
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fpga: lib: add ctrlport endpoints for I2C, UART and high-throughput SPI
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2026-08-04 10:40:31 +02:00 |
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ctrlport_to_wb_i2c.v
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fpga: lib: fixup i2c non-blocking assignments
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2026-09-24 08:56:44 +02:00 |
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ctrlport_to_wb_uart.v
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fpga: lib: adjust ctrlport_to_wb_uart signal width
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2026-10-01 13:02:57 -05:00 |
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db_control.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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fe_control.v
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fpga: Update copyright
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2023-01-19 15:55:56 -08:00 |
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filter_bad_sid.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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gearbox_2x1.v
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fpga: lib: Add 2 to 1 gearbox module
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2021-06-03 11:26:54 -05:00 |
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glitch_free_mux.v
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fpga: lib: add glitch free mux module
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2020-12-03 09:02:17 -06:00 |
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gpio_atr_io.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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gpio_atr.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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gray2bin.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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handshake_latch.sv
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fpga: lib: Add handshake_latch module
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2025-07-10 17:09:54 +02:00 |
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handshake.v
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fpga: lib: add handshake to replace FIFO for ctrlport CDC
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2020-08-13 07:46:14 -05:00 |
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jtag_regmap_utils.vh
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fpga: lib: move ctrlport_to_jtag to lib sirectory
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2026-08-14 16:32:09 -05:00 |
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Makefile.srcs
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fpga: lib: move ctrlport_to_jtag to lib sirectory
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2026-08-14 16:32:09 -05:00 |
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mdio_master.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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por_gen.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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priority_encoder_one_hot.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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priority_encoder.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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pulse_stretch_min.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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pulse_stretch.v
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fpga: lib: simplify timing in pulse stretch
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2025-01-23 19:18:48 -06:00 |
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pulse_synchronizer.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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ram_2port_impl.vh
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fpga: lib: Add initial value to ram_2port
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2025-04-09 13:50:17 -05:00 |
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ram_2port.v
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fpga: lib: Add initial value to ram_2port
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2025-04-09 13:50:17 -05:00 |
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regport_if.sv
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fpga: lib: Add RegPort SystemVerilog interface
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2022-08-29 17:01:45 -05:00 |
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regport_resp_mux.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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regport_to_settingsbus.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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regport_to_xbar_settingsbus.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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reset_sync.v
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fpga: fix various warnings in CPLD related code
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2025-06-27 10:27:14 -05:00 |
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s7_icap_wb.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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serial_to_settings_tb.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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serial_to_settings.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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setting_reg.v
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fpga: lib: Fix indentation in setting_reg.v
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2023-01-10 14:18:59 -08:00 |
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settings_bus_mux.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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settings_bus_timed_2clk.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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simple_i2c_core.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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simple_spi_core_64bit.v
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fpga: fix various warnings in CPLD related code
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2025-06-27 10:27:14 -05:00 |
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simple_spi_core.v
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fpga: lib: Update simple_spi_core documentation
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2025-02-10 16:46:53 -06:00 |
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synchronizer_impl.v
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fpga: lib: Add default wiretypes to synchronizer
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2023-11-14 17:15:53 -06:00 |
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synchronizer_sync_in.sv
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fpga: lib: Add synchronizer_sync_in module
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2025-04-22 10:21:25 -05:00 |
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synchronizer.v
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fpga: lib: Add default wiretypes to synchronizer
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2023-11-14 17:15:53 -06:00 |
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user_settings.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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usrp_utils.svh
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fpga: lib: Add TO_SIGNED to usrp_utils.svh
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2025-02-12 22:06:20 -06:00 |
