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dd708a46f4
Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Tony Liecthy <tony.liechty@ni.com>
136 lines
3.5 KiB
Systemverilog
136 lines
3.5 KiB
Systemverilog
//
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// Copyright 2026 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_to_ctrlport
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//
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// Description:
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//
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// Converts an AXI-Stream bus into a readable CtrlPort interface. Read
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// requests get responded to as soon as data becomes available on the
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// AXI-Stream input.
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//
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// Parameters:
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//
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// WIDTH : Width of the data path in bits
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// FIFO_SIZE_LOG2 : Log base 2 of the depth of the input AXI-Stream FIFO.
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// This FIFO is optional. Depth can be set to -1 to remove
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// it entirely.
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//
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// Signals:
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//
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// clk : Clock
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// rst : Active-high synchronous reset
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// s_axis_tdata : AXI-Stream data input
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// s_axis_tvalid : AXI-Stream valid
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// s_axis_tready : AXI-Stream ready
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// ctrl_rd : CtrlPort read request strobe (single-cycle pulse)
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// ctrl_data : CtrlPort read data output
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// ctrl_ack : CtrlPort acknowledgement strobe (single-cycle pulse)
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//
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`default_nettype none
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module axis_to_ctrlport #(
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parameter int WIDTH = 32,
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parameter int FIFO_SIZE_LOG2 = 0
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) (
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input wire clk,
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input wire rst,
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// AXI-Stream slave
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input wire [WIDTH-1:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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// CtrlPort read interface
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input wire ctrl_rd,
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output logic [WIDTH-1:0] ctrl_data,
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output logic ctrl_ack
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);
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//---------------------------------------------------------------------------
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// Declarations
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//---------------------------------------------------------------------------
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typedef enum logic { ST_IDLE, ST_WAIT } state_t;
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state_t state;
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// Internal stream between the input FIFO and the FSM.
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logic [WIDTH-1:0] fifo_o_tdata;
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logic fifo_o_tvalid;
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logic fifo_o_tready;
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//---------------------------------------------------------------------------
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// Input FIFO
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//---------------------------------------------------------------------------
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axi_fifo #(
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.WIDTH (WIDTH),
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.SIZE (FIFO_SIZE_LOG2)
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) input_fifo_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.i_tdata (s_axis_tdata),
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.i_tvalid (s_axis_tvalid),
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.i_tready (s_axis_tready),
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.o_tdata (fifo_o_tdata),
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.o_tvalid (fifo_o_tvalid),
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.o_tready (fifo_o_tready),
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.space (),
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.occupied ()
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);
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//---------------------------------------------------------------------------
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// State Machine
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//---------------------------------------------------------------------------
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assign ctrl_data = fifo_o_tdata;
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assign fifo_o_tready = ctrl_ack;
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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ctrl_ack <= 1'b0;
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end else begin
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// Default: deassert ACK every cycle.
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ctrl_ack <= 1'b0;
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case (state)
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ST_IDLE: begin
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if (ctrl_rd) begin
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if (fifo_o_tvalid) begin
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// If we have data available, then ACK on next clock cycle.
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ctrl_ack <= 1'b1;
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end else begin
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// If we don't have data yet, then wait until it arrives.
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state <= ST_WAIT;
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end
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end
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end
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ST_WAIT: begin
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// ACK after we get a new data word
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if (fifo_o_tvalid) begin
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ctrl_ack <= 1'b1;
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state <= ST_IDLE;
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end
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end
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default: begin
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state <= ST_IDLE;
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end
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endcase
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end
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end
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endmodule : axis_to_ctrlport
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`default_nettype wire
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