Commit Graph

11232 Commits

Author SHA1 Message Date
Max Köhler
a323d55cf7 ci: trigger mono pipeline on FPGA changes 2025-04-07 09:22:41 +02:00
Jörg Hofrichter
084329d24f ci: re-introduce uhdFpgaArtifactSource parameter for test pipelines 2025-04-06 13:21:37 +02:00
Martin Braun
6ef4e4c9eb rfnoc: Make e31x the default device for OOT modules
The E31x has the advantage that it can be targeted from the free tier of
Vivado, which means users can start writing blocks and running
testbenches without having to purchase a Vivado license. This is already
possible today by specifying -DUHD_FPGA_DEFAULT_DEVICE=e31x when running
cmake, but we think this will further lower the entry level for RFNoC
developers by making the free-tier option the default.
2025-04-04 15:28:05 +02:00
Wade Fife
ff12e4a2fd fpga: lib: Update FFT IP for parallel builds 2025-04-04 08:11:57 -05:00
Sam Lane
13d004fa90 fpga: tools: Add assert option to synthesis
Add -assert option to Vivado synthesis to allow VHDL assert statements
to be checked during synthesis.
2025-04-03 11:01:14 -05:00
Wade Fife
9dc2e089d8 fpga: tools: Fix escape sequence warnings
This adds to 11c60ee to fix a few additional escape sequence warnings.
2025-04-03 09:51:54 +02:00
Jörg Hofrichter
4ed588ab3c ci: utils: set fixed dependency versions to avoid breakages 2025-04-03 09:50:08 +02:00
Abhishek Verma
7615602b7c examples: tx_waveforms: improved comments and help
Improving user experience with examples.
- added example's functionality and intent in --help
- added each arg help description in --help
- added summary to each function module
- added more prints in during operation
2025-04-03 08:17:23 +02:00
Michael Cho
2725c664ce examples: update for upcoming Boost 1.88.0
Boost.Process 1.88.0 will make `boost::process::v2` the default which
breaks compilation of rx_samples_to_file.cpp. This change uses v1
headers and inline namespace to fix build.
2025-04-02 10:50:48 +02:00
NI\asalman
fef432b75a host: default to rw regs in get_changed_addrs() 2025-04-02 09:26:26 +02:00
Max Köhler
22b4a35da2 fpga: x4xx: add reset option for gearboxes 2025-04-02 08:02:11 +02:00
Max Köhler
780b1a3887 mpm: reset ADC & DAC chains after synchronize 2025-04-02 08:02:11 +02:00
Frank Dietze
dec2031710 ci: Added condition to avoid propagating empty parameters 2025-04-01 17:36:48 +02:00
Jörg Hofrichter
14af6f6f58 ci: Allow using "Mono Pipeline PR" and "FPGA Pipeline" as source
... for the changeset analyser.
2025-04-01 14:42:44 +02:00
Lars Amsel
255c634b6d host: Check request queue for items before access
Request queue should always contain items if we receive responses.
To ensure we do not assert on front() call for empty request queue
we check for empty first and print a warning otherwise.
2025-04-01 08:26:45 +02:00
Jörg Hofrichter
a5305f1ece ci: add RFNoC block testing to hardware tests 2025-03-30 08:16:34 +02:00
Jordan Yamada
b076843206 docs: Updating cpld instructions for x4xx
- Adding guidance to contact support for bricked devices
- Changed commands for copying rpd file to encourage users to copy
  correct file
2025-03-28 16:00:47 +01:00
Grant Meyerhoff
97c604139e cal: use atomic<bool> to wait until transmitting starts 2025-03-28 07:29:12 +01:00
Max Köhler
4ebbd61cb1 ci: fpga: add FPGA pipeline to execute mono pipeline subset 2025-03-26 14:23:20 +01:00
Max Köhler
dc38f9041d ci: fpga: add option for FPGA compile success rate runs 2025-03-26 14:23:20 +01:00
Max Köhler
8722a8b60c ci: fpga: allow FPGA jobs to get cancelled 2025-03-26 14:23:20 +01:00
Max Köhler
b0e2d86aa9 ci: add option to skip rule checking, only execute given add tests 2025-03-26 14:23:20 +01:00
Max Köhler
e4cbbe7145 fpga: x440: bring back TX control remap in RFDC BD 2025-03-25 07:50:14 +01:00
Grant Meyerhoff
d4ad6451b0 ci: add back ability to select streaming tests 2025-03-25 07:50:04 +01:00
Max Köhler
95e227edaa fpga: x400: zbx: update projects for new ctrlport modules 2025-03-21 09:09:09 -05:00
Max Köhler
6bcb44df7b fpga: x400: cpld: update projects for new ctrlport modules 2025-03-21 09:09:09 -05:00
Max Köhler
bf294111b9 fpga: lib: redirect old ctrlport modules to interface based ones 2025-03-21 09:09:09 -05:00
Max Köhler
c4ceb8c314 mpm: apply formatting to base.py 2025-03-21 10:55:09 +01:00
Max Köhler
f345bc83b9 mpm: fix type error in DB override printout 2025-03-21 10:55:09 +01:00
Frank Dietze
b224359097 ci: pytest: using sfp0ip environment variable in ats config and devtest 2025-03-20 21:02:43 +01:00
Jörg Hofrichter
4aa4c77043 ci: Fix matrix for X410/X440 FPGA build 2025-03-20 09:07:06 +01:00
Max Köhler
be2e0a5c24 mpm: apply linting to x4xx_rfdc_regs.py 2025-03-20 09:07:06 +01:00
Max Köhler
894ecb691e mpm: bump FPGA compat number to 10.0 2025-03-20 09:07:06 +01:00
Max Köhler
1cb4898519 fpga: bump compat number to 10.0 2025-03-20 09:07:06 +01:00
Max Köhler
24dd961f10 mpm: read ADC/DAC mapping from RFDC memory 2025-03-20 09:07:06 +01:00
Max Köhler
6c6d52fd65 fpga: x4xx: replace ADC/DAC info by RFDC memory 2025-03-20 09:07:06 +01:00
Frank Dietze
4d44beec8e ci: pytest: separate BIST tests 2025-03-19 08:59:41 +01:00
Lars Amsel
108d30d646 host: Increase initial timeout to contain start_time
If start_time is far in the future (acutally bigger that the default
timeout of 0.1s) we have to increase the initial timout by that time
interval to ensure we do not timeout because the transmission did not start yet.
2025-03-18 14:24:26 +01:00
Wade Fife
d9f8c08dfb fpga: rfnoc: Move synthesizable code from sim to lib 2025-03-17 17:47:16 -05:00
Wade Fife
f094aa7ae0 fpga: tools: Disable common simulation warnings
This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.
2025-03-17 13:40:26 -05:00
Wade Fife
7ab4e9a4e2 fpga: tools: Change -onfinish to final
This changes the -onfinish setting from "stop" to "final" for Questa
and ModelSim. The "final" setting is required so that SystemVerilog
final blocks run. This also has the same effect as "stop" in that it
won't ask you in the GUI if you want to exit the simulator when
$finish() is called.
2025-03-17 13:40:26 -05:00
Wade Fife
4cc3a19f56 fpga: docs: Add Questa to simulation instructions 2025-03-17 13:40:26 -05:00
Wade Fife
247f9fd2ac fpga: tools: Add support for Questa 2025-03-17 13:40:26 -05:00
Martin Braun
59ee5aa6cb examples: Fix calloc() call in tx_samples_c.c
The arguments were transposed. Modern gcc checks for that and throws
a warning. Now the call signature matches its documentation.
2025-03-17 18:39:03 +01:00
Martin Braun
c7255dacc6 uhd: dpdk: Fix compiler warnings for gcc15
- Some DPDK methods were not checking their return values; now they do
  and trigger exceptions upon failure.
- cstdbool was included, despite us using C++17 which makes that
  obsolete.
2025-03-17 18:39:03 +01:00
Martin Braun
b767b4e628 tools: Remove uhd_dump
This tool was originally written to aid with X3x0 development, prior to
the development of current-day RFNoC. Basically, it's a poor-man's
version of Wireshark.

However, it implements an old version of the network protocol, which is
currently not in use. The tool is therefore obsolete, and our Wireshark
dissectors are a perfectly reasonable substitute. We therefore remove it
from UHD.
2025-03-14 15:25:57 +01:00
Lars Amsel
d370974bc1 host: add semicolon to UHD_SAFE_CALL
UHD_SAFE_CALL macro had no semicolon after the code part. This
force the code using the macro to write something like

    UHD_SAFE_CALL(some_func(););

which looks bit awkward. Adding a semicolon to allow writing
on liners like

    UHD_SAFE_CALL(some_func());

Multi line code could still use a semicolon after the last
statement, as the compiler does not bother about double semicolon.
2025-03-14 12:57:58 +01:00
Martin Braun
191ec394ec tools: uhd_dump: Remove unused type bool
This is a redeclaration of built-in bool, and thus causes problems on
modern compilers.
2025-03-14 11:42:44 +01:00
Jaroslav Škarvada
14337e23e4 uhd: Add some missing cstdint includes
This aids with making UHD gcc-15 compatible (more fixes are required for
full compatibility).
2025-03-14 11:42:44 +01:00
Wade Fife
81ccd8cb51 fpga: tools: Fix issues in run_testbenches.py
This commit addresses several issues that can occur with different
simulators. It changes the following:

- Update documentation
- Ignore testbenches in build-ip folders
- Tolerate extra lines in the testbench results regular expression
- Match numbers using \d instead of + to avoid ValueError exceptions
- Only fetch the start_time if it exists
- Allow any simulator make target (don't limit it to specific choices)
2025-03-14 08:03:34 +01:00