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mpm: read ADC/DAC mapping from RFDC memory
This commit is contained in:
Max Köhler
Jörg Hofrichter
parent
6c6d52fd65
commit
24dd961f10
@ -196,44 +196,21 @@ RF_PLL_ENABLE_RF1_CLK 0x16000[20] 0 enable, disable
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RF_PLL_ENABLE_RF1_CLK_x2 0x16000[24] 0 enable, disable
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CLEAR_DATA_CLK_UNLOCKED 0x16000[16] 0 enable, disable
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MMCM_LOCKED 0x16008[20] ro
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ADC_TILEMAP_DB0_CHAN0_TILE 0x17000[0:1] ro
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ADC_TILEMAP_DB0_CHAN0_BLOCK 0x17000[2:3] ro
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ADC_TILEMAP_DB0_CHAN1_TILE 0x17000[4:5] ro
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ADC_TILEMAP_DB0_CHAN1_BLOCK 0x17000[6:7] ro
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ADC_TILEMAP_DB0_CHAN2_TILE 0x17000[8:9] ro
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ADC_TILEMAP_DB0_CHAN2_BLOCK 0x17000[10:11] ro
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ADC_TILEMAP_DB0_CHAN3_TILE 0x17000[12:13] ro
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ADC_TILEMAP_DB0_CHAN3_BLOCK 0x17000[14:15] ro
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ADC_TILEMAP_DB1_CHAN0_TILE 0x17000[16:17] ro
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ADC_TILEMAP_DB1_CHAN0_BLOCK 0x17000[18:19] ro
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ADC_TILEMAP_DB1_CHAN1_TILE 0x17000[20:21] ro
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ADC_TILEMAP_DB1_CHAN1_BLOCK 0x17000[22:23] ro
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ADC_TILEMAP_DB1_CHAN2_TILE 0x17000[24:25] ro
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ADC_TILEMAP_DB1_CHAN2_BLOCK 0x17000[26:27] ro
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ADC_TILEMAP_DB1_CHAN3_TILE 0x17000[28:29] ro
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ADC_TILEMAP_DB1_CHAN3_BLOCK 0x17000[30:31] ro
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DAC_TILEMAP_DB0_CHAN0_TILE 0x17008[0:1] ro
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DAC_TILEMAP_DB0_CHAN0_BLOCK 0x17008[2:3] ro
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DAC_TILEMAP_DB0_CHAN1_TILE 0x17008[4:5] ro
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DAC_TILEMAP_DB0_CHAN1_BLOCK 0x17008[6:7] ro
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DAC_TILEMAP_DB0_CHAN2_TILE 0x17008[8:9] ro
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DAC_TILEMAP_DB0_CHAN2_BLOCK 0x17008[10:11] ro
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DAC_TILEMAP_DB0_CHAN3_TILE 0x17008[12:13] ro
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DAC_TILEMAP_DB0_CHAN3_BLOCK 0x17008[14:15] ro
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DAC_TILEMAP_DB1_CHAN0_TILE 0x17008[16:17] ro
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DAC_TILEMAP_DB1_CHAN0_BLOCK 0x17008[18:19] ro
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DAC_TILEMAP_DB1_CHAN1_TILE 0x17008[20:21] ro
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DAC_TILEMAP_DB1_CHAN1_BLOCK 0x17008[22:23] ro
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DAC_TILEMAP_DB1_CHAN2_TILE 0x17008[24:25] ro
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DAC_TILEMAP_DB1_CHAN2_BLOCK 0x17008[26:27] ro
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DAC_TILEMAP_DB1_CHAN3_TILE 0x17008[28:29] ro
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DAC_TILEMAP_DB1_CHAN3_BLOCK 0x17008[30:31] ro
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RFDC_INFO_DB0_XTRA_RESAMP 0x18000[0:3] ro
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RFDC_INFO_DB0_SPC_RX 0x18000[4:6] ro
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RFDC_INFO_DB0_SPC_TX 0x18000[7:9] ro
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RFDC_INFO_DB1_XTRA_RESAMP 0x18000[16:19] ro
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RFDC_INFO_DB1_SPC_RX 0x18000[20:22] ro
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RFDC_INFO_DB1_SPC_TX 0x18000[23:25] ro
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########################################################################
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## RFDC information
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########################################################################
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RFDC_INFO_BLOCK_MODE[16] 0x17000[0:1] 0 ENABLED, RESERVED1, RESERVED2, DISABLED
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RFDC_INFO_BLOCK[16] 0x17000[2:3] 0
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RFDC_INFO_TILE[16] 0x17000[4:5] 0
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RFDC_INFO_CHANNEL[16] 0x17000[8:9] 0
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RFDC_INFO_DB[16] 0x17000[10] 0
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RFDC_INFO_IS_ADC[16] 0x17000[11] 0
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"""
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########################################################################
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@ -281,7 +258,7 @@ def set_reg(self, addr, reg):
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# Now the arrays
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% for addr in sorted(set([r.get_addr() for r in regs if r.is_array])):
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<% if_state = 'if' if loop.index == 0 else 'elif' %> \
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<% reglist = [r for r in regs if r.get_addr() == addr] %>
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<% reglist = [r for r in regs if r.get_addr() == addr] %>
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${if_state} ${addr} <= addr < ${addr} + ${reglist[0].get_array_len()} * 4:
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index = (addr - ${addr}) // 4
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% for reg in reglist:
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@ -13,6 +13,9 @@ from usrp_mpm.chips.ic_reg_maps.x4xx_rfdc_regmap import x4xx_rfdc_regmap_t
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from usrp_mpm.mpmutils import poll_with_timeout
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from usrp_mpm.periph_manager.x4xx_clock_lookup import MMCM_LOCKGROUP_LOOKUP, MMCM_FILTERGROUP_LOOKUP
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# Number of ADCs and DACs in the RFDC.
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NUM_CONVERTERS = 16
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class RfdcRegsControl:
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"""
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Control the FPGA RFDC registers external to the XRFdc API
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@ -44,8 +47,8 @@ class RfdcRegsControl:
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self._update_reg('CAL_ENABLE_DB0_CHAN0')
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self._update_reg('FABRIC_DSP_INFO_BW')
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self._update_reg('RFDC_INFO_DB0_XTRA_RESAMP')
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self._update_reg('ADC_TILEMAP_DB0_CHAN0_TILE')
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self._update_reg('DAC_TILEMAP_DB0_CHAN0_TILE')
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for conv in range(NUM_CONVERTERS):
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self._update_reg("RFDC_INFO_BLOCK_MODE", conv)
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self._regs.save_state()
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# From now on, we can use _commit() to write registers instead of going
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# through peek/poke.
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@ -95,23 +98,31 @@ class RfdcRegsControl:
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This means there are 2 dboards. On the first dboard, we have 2 channels,
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and channel 0 uses tile 0, block 1.
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"""
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# define helper function to extract content from device memory
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def get_tuple(db, channel, is_adc):
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for i in range(NUM_CONVERTERS):
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if (
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(
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self._regs.RFDC_INFO_BLOCK_MODE[i]
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== self._regs.RFDC_INFO_BLOCK_MODE_t.RFDC_INFO_BLOCK_MODE_ENABLED
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)
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and (self._regs.RFDC_INFO_DB[i] == db)
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and (self._regs.RFDC_INFO_CHANNEL[i] == channel)
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and (self._regs.RFDC_INFO_IS_ADC[i] == is_adc)
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):
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return tuple((self._regs.RFDC_INFO_TILE[i], self._regs.RFDC_INFO_BLOCK[i]))
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else:
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raise ValueError(f"Could not find mapping for {db}, {channel}, {is_adc}")
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adc_mapping = tuple(
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tuple(
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tuple((
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getattr(self._regs, f'ADC_TILEMAP_DB{db}_CHAN{chan}_TILE'),
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getattr(self._regs, f'ADC_TILEMAP_DB{db}_CHAN{chan}_BLOCK'),
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))
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for chan in range(num_channels)
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get_tuple(db, chan, True) for chan in range(num_channels)
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)
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for db, num_channels in enumerate(self.get_num_rx_channels())
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)
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dac_mapping = tuple(
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tuple(
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tuple((
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getattr(self._regs, f'DAC_TILEMAP_DB{db}_CHAN{chan}_TILE'),
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getattr(self._regs, f'DAC_TILEMAP_DB{db}_CHAN{chan}_BLOCK'),
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))
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for chan in range(num_channels)
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get_tuple(db, chan, False) for chan in range(num_channels)
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)
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for db, num_channels in enumerate(self.get_num_tx_channels())
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)
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@ -212,7 +223,7 @@ class RfdcRegsControl:
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self._poke(
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self._regs.get_addr("MMCM_LOAD_SEN"),
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self._regs.get_reg(self._regs.get_addr("MMCM_LOAD_SEN")))
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self.log.trace('MMCM Configuration applied, now waiting for MMCM to lock...')
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self.wait_for_mmcm_drp_done()
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self.clear_data_clk_unlocked()
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@ -597,10 +608,10 @@ class RfdcRegsControl:
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self._poke(addr, self._regs.get_reg(addr))
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self._regs.save_state()
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def _update_reg(self, reg_name):
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def _update_reg(self, reg_name, idx=0):
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"""
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Update the saved state of a register from the hardware
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"""
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addr = self._regs.get_addr(reg_name)
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reg_val = self._peek(addr)
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self._regs.set_reg(addr, reg_val)
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reg_val = self._peek(addr + 4 * idx)
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self._regs.set_reg(addr + 4 * idx, reg_val)
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